1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
10 * Configuration settings for the Freescale i.MX6Q SabreSD board.
12 #ifndef __ARISTAINETOS_COMMON_CONFIG_H
13 #define __ARISTAINETOS_COMMON_CONFIG_H
15 #include "mx6_common.h"
17 #define CONFIG_MACH_TYPE 4501
18 #define CONFIG_MMCROOT "/dev/mmcblk0p1"
20 /* Size of malloc() pool */
21 #define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)
23 #define CONFIG_MXC_UART
26 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
28 #define CONFIG_FEC_MXC
29 #define IMX_FEC_BASE ENET_BASE_ADDR
30 #define CONFIG_ETHPRIME "FEC"
31 #define CONFIG_FEC_MXC_PHYADDR 0
33 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
35 #define CONFIG_EXTRA_ENV_SETTINGS \
36 "script=u-boot.scr\0" \
37 "fit_file=/boot/system.itb\0" \
38 "loadaddr=0x12000000\0" \
39 "fit_addr_r=0x14000000\0" \
40 "uboot=/boot/u-boot.imx\0" \
42 "rescue_sys_addr=f0000\0" \
43 "rescue_sys_length=f10000\0" \
46 "console=" CONSOLE_DEV "\0" \
47 "fdt_high=0xffffffff\0" \
48 "initrd_high=0xffffffff\0" \
49 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
50 "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
51 "default ${board_type}\0" \
52 "get_env=mw ${loadaddr} 0 0x20000;" \
54 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
55 "env import -t ${loadaddr}\0" \
56 "default_env=mw ${loadaddr} 0 0x20000;" \
57 "env export -t ${loadaddr} serial# ethaddr eth1addr " \
60 "env import -t ${loadaddr}\0" \
62 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
63 "bootscript=echo Running bootscript from mmc ...; " \
67 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
68 "mmcargs=setenv bootargs console=${console},${baudrate} " \
70 "mmcboot=echo Booting from mmc ...; " \
71 "run mmcargs addmtd addmisc set_fit_default;" \
72 "bootm ${fit_addr_r}\0" \
73 "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
75 "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
77 "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
78 "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
79 "setexpr uboot_maxsize ${uboot_sz} - 400;" \
80 "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
81 "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
82 "sf write ${loadaddr} 400 ${filesize};" \
83 "sf read ${cmp_buf} 400 ${uboot_sz};" \
84 "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
85 "ubiboot=echo Booting from ubi ...; " \
86 "run ubiargs addmtd addmisc set_fit_default;" \
87 "bootm ${fit_addr_r}\0" \
88 "rescueargs=setenv bootargs console=${console},${baudrate} " \
89 "root=/dev/ram rw\0 " \
90 "rescueboot=echo Booting rescue system from NOR ...; " \
91 "run rescueargs addmtd addmisc set_fit_default;" \
92 "bootm ${fit_addr_r}\0" \
93 "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
94 "${rescue_sys_length}; imi ${fit_addr_r}\0" \
95 CONFIG_EXTRA_ENV_BOARD_SETTINGS
97 #define CONFIG_BOOTCOMMAND \
98 "mmc dev ${mmcdev};" \
99 "if mmc rescan; then " \
100 "if run loadbootscript; then " \
103 "if run mmc_load_fit; then " \
106 "if run ubifs_load_fit; then " \
109 "if run rescue_load_fit; then " \
112 "echo RESCUE SYSTEM BOOT " \
119 "if run ubifs_load_fit; then " \
122 "if run rescue_load_fit; then " \
125 "echo RESCUE SYSTEM BOOT FAILURE;" \
130 #define CONFIG_ARP_TIMEOUT 200UL
132 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
133 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
134 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
136 /* Physical Memory Map */
137 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
139 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
140 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
141 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
143 #define CONFIG_SYS_INIT_SP_OFFSET \
144 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
145 #define CONFIG_SYS_INIT_SP_ADDR \
146 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
148 /* Environment organization */
150 #define CONFIG_SYS_FSL_USDHC_NUM 2
153 #define CONFIG_SYS_I2C
154 #define CONFIG_SYS_I2C_MXC
155 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
156 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
157 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
158 #define CONFIG_SYS_I2C_SPEED 100000
159 #define CONFIG_SYS_I2C_SLAVE 0x7f
160 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
163 #define CONFIG_SYS_MAX_NAND_DEVICE 1
164 #define CONFIG_SYS_NAND_BASE 0x40000000
165 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
166 #define CONFIG_SYS_NAND_ONFI_DETECTION
168 /* DMA stuff, needed for GPMI/MXS NAND support */
171 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
172 #define CONFIG_SYS_RTC_BUS_NUM 2
173 #define CONFIG_RTC_M41T11
176 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
177 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
178 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
179 #define CONFIG_MXC_USB_FLAGS 0
184 /* check this console not needed, after test remove it */
185 #define CONFIG_VIDEO_BMP_RLE8
186 #define CONFIG_SPLASH_SCREEN
187 #define CONFIG_SPLASH_SCREEN_ALIGN
188 #define CONFIG_BMP_16BPP
189 #define CONFIG_VIDEO_LOGO
190 #define CONFIG_VIDEO_BMP_LOGO
191 #define CONFIG_IMX_VIDEO_SKIP
193 #define CONFIG_IMX6_PWM_PER_CLK 66000000
195 #endif /* __ARISTAINETOS_COMMON_CONFIG_H */