1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Configuration settings for the Armadeus Project motherboard APF27
6 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
12 #define CONFIG_ENV_VERSION 10
13 #define CONFIG_BOARD_NAME apf27
18 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
19 #define CONFIG_MACH_TYPE 1698 /* APF27 */
22 * Enable the call to miscellaneous platform dependent initialization.
28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29 #define CONFIG_SPL_MAX_SIZE 2048
31 /* NAND boot config */
32 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
34 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
40 #define CONFIG_BOOTP_BOOTFILESIZE
41 #define CONFIG_BOOTP_DNS2
43 #define CONFIG_HOSTNAME "apf27"
44 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
47 * Memory configurations
49 #define CONFIG_NR_DRAM_POPULATED 1
51 #define ACFG_SDRAM_MBYTE_SYZE 64
53 #define PHYS_SDRAM_1 0xA0000000
54 #define PHYS_SDRAM_2 0xB0000000
55 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
58 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
59 + PHYS_SDRAM_1_SIZE - 0x0100000)
64 #define ACFG_MONITOR_OFFSET 0x00000000
65 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
66 #define CONFIG_ENV_OVERWRITE
67 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
68 #define CONFIG_FIRMWARE_OFFSET 0x00200000
69 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
70 #define CONFIG_KERNEL_OFFSET 0x00300000
71 #define CONFIG_ROOTFS_OFFSET 0x00800000
74 * U-Boot general configurations
76 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
77 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
78 /* Boot argument buffer size */
83 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
84 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
85 #define CONFIG_INITRD_TAG /* send initrd params */
87 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
89 #define ACFG_CONSOLE_DEV ttySMX0
90 #define CONFIG_BOOTCOMMAND "run ubifsboot"
91 #define CONFIG_SYS_AUTOLOAD "no"
93 * Default load address for user programs and kernel
95 #define CONFIG_LOADADDR 0xA0000000
96 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
101 #define CONFIG_EXTRA_ENV_SETTINGS \
102 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
103 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
104 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
105 "partition=nand0,6\0" \
106 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
107 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
108 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
109 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
110 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
111 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
112 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
113 "kernel_addr_r=A0000000\0" \
114 "check_env=if test -n ${flash_env_version}; " \
115 "then env default env_version; " \
116 "else env set flash_env_version ${env_version}; env save; "\
118 "if itest ${flash_env_version} < ${env_version}; then " \
119 "echo \"*** Warning - Environment version" \
120 " change suggests: run flash_reset_env; reset\"; "\
121 "env default flash_reset_env; "\
123 "check_flash=nand lock; nand unlock ${env_addr}; \0" \
124 "flash_reset_env=env default -f -a; saveenv; run update_env;" \
125 "echo Flash environment variables erased!\0" \
126 "download_uboot=tftpboot ${loadaddr} ${board_name}" \
127 "-u-boot-with-spl.bin\0" \
128 "flash_uboot=nand unlock ${u-boot_addr} ;" \
129 "nand erase.part u-boot;" \
130 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
131 "then nand lock; nand unlock ${env_addr};" \
132 "echo Flashing of uboot succeed;" \
133 "else echo Flashing of uboot failed;" \
135 "update_uboot=run download_uboot flash_uboot\0" \
136 "download_env=tftpboot ${loadaddr} ${board_name}" \
137 "-u-boot-env.txt\0" \
138 "flash_env=env import -t ${loadaddr}; env save; \0" \
139 "update_env=run download_env flash_env\0" \
140 "update_all=run update_env update_uboot\0" \
141 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
146 #define CONFIG_MXC_UART
147 #define CONFIG_MXC_UART_BASE UART1_BASE
157 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
158 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
159 #define CONFIG_SYS_MAX_NAND_DEVICE 1
161 #define CONFIG_MXC_NAND_HWECC
162 #define CONFIG_SYS_NAND_LARGEPAGE
163 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
164 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
165 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
166 CONFIG_SYS_NAND_PAGE_SIZE
167 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
168 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
169 #define NAND_MAX_CHIPS 1
171 #define CONFIG_FLASH_SHOW_PROGRESS 45
172 #define CONFIG_SYS_NAND_QUIET 1
175 * Partitions & Filsystems
179 * Ethernet (on SOC imx FEC)
181 #define CONFIG_FEC_MXC
182 #define CONFIG_FEC_MXC_PHYADDR 0x1f
187 #define CONFIG_FPGA_COUNT 1
188 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
189 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
190 #define CONFIG_SYS_FPGA_CHECK_CTRLC
191 #define CONFIG_SYS_FPGA_CHECK_ERROR
196 #ifdef CONFIG_CMD_IMX_FUSE
197 #define IIM_MAC_BANK 0
198 #define IIM_MAC_ROW 5
199 #define IIM0_SCC_KEY 11
207 #ifdef CONFIG_CMD_I2C
208 #define CONFIG_SYS_I2C
209 #define CONFIG_SYS_I2C_MXC
210 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
211 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
212 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
213 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
214 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
215 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
216 #define CONFIG_SYS_I2C_NOPROBES { }
218 #ifdef CONFIG_CMD_EEPROM
219 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
220 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
223 #endif /* CONFIG_CMD_EEPROM */
224 #endif /* CONFIG_CMD_I2C */
229 #ifdef CONFIG_CMD_MMC
230 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000
236 #ifdef CONFIG_CMD_DATE
237 #define CONFIG_RTC_DS1374
238 #define CONFIG_SYS_RTC_BUS_NUM 0
239 #endif /* CONFIG_CMD_DATE */
244 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
245 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
247 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
249 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
251 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
252 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
255 #if (ACFG_SDRAM_MBYTE_SYZE == 128)
257 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
258 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
261 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
263 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
264 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
267 #endif /* __CONFIG_H */