1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Renesas Solutions AP-325RXA board
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
12 #define CONFIG_CPU_SH7723 1
14 #define CONFIG_DISPLAY_BOARDINFO
15 #undef CONFIG_SHOW_BOOT_PROGRESS
18 #define AP325RXA_SDRAM_BASE (0x88000000)
19 #define AP325RXA_FLASH_BASE_1 (0xA0000000)
20 #define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
22 /* undef to save memory */
23 /* Monitor Command Prompt */
24 /* Buffer size for Console output */
25 #define CONFIG_SYS_PBSIZE 256
26 /* List of legal baudrate settings for this board */
27 #define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
30 #define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
31 #define CONFIG_CONS_SCIF5 1
33 /* Suppress display of console information at boot */
35 #define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
36 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
38 /* Enable alternate, more extensive, memory test */
39 /* Scratch address used by the alternate memory test */
40 #undef CONFIG_SYS_MEMTEST_SCRATCH
42 /* Enable temporary baudrate change while serial download */
43 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
45 #define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
46 /* maybe more, but if so u-boot doesn't know about it... */
47 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
48 /* default load address for scripts ?!? */
49 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
51 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
52 #define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
54 #define CONFIG_SYS_MONITOR_LEN (128 * 1024)
55 /* Size of DRAM reserved for malloc() use */
56 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
57 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
60 #define CONFIG_FLASH_CFI_DRIVER 1
61 #define CONFIG_SYS_FLASH_CFI
62 #undef CONFIG_SYS_FLASH_QUIET_TEST
63 /* print 'E' for empty sector on flinfo */
64 #define CONFIG_SYS_FLASH_EMPTY_INFO
65 /* Physical start address of Flash memory */
66 #define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
67 /* Max number of sectors on each Flash chip */
68 #define CONFIG_SYS_MAX_FLASH_SECT 512
73 #define CONFIG_IDE_RESET 1
74 #define CONFIG_SYS_PIO_MODE 1
75 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
76 #define CONFIG_SYS_IDE_MAXDEVICE 1
77 #define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
78 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
79 #define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
80 #define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
81 #define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
82 #define CONFIG_IDE_SWAP_IO
84 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
85 #define CONFIG_SYS_MAX_FLASH_BANKS 1
86 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
88 /* Timeout for Flash erase operations (in ms) */
89 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
90 /* Timeout for Flash write operations (in ms) */
91 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
92 /* Timeout for Flash set sector lock bit operations (in ms) */
93 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
94 /* Timeout for Flash clear lock bit operations (in ms) */
95 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
98 * Use hardware flash sectors protection instead
99 * of U-Boot software protection
101 #undef CONFIG_SYS_FLASH_PROTECTION
102 #undef CONFIG_SYS_DIRECT_FLASH_TFTP
105 #define CONFIG_ENV_OVERWRITE 1
106 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
107 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
108 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
109 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
110 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
111 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
114 #define CONFIG_SYS_CLK_FREQ 33333333
115 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
116 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
117 #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
119 #endif /* __AP325RXA_H */