include/configs/amcore.h

   1 /*
   2  * Sysam AMCORE board configuration
   3  *
   4  * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __AMCORE_CONFIG_H
  10 #define __AMCORE_CONFIG_H
  11
  12 #define CONFIG_AMCORE
  13 #define CONFIG_HOSTNAME                 AMCORE
  14
  15 #define CONFIG_MCFTMR
  16 #define CONFIG_MCFUART
  17 #define CONFIG_SYS_UART_PORT            0
  18 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  19
  20 #define CONFIG_BOOTCOMMAND              "bootm ffc20000"
  21 #define CONFIG_EXTRA_ENV_SETTINGS                               \
  22         "upgrade_uboot=loady; "                                 \
  23                 "protect off 0xffc00000 0xffc1ffff; "           \
  24                 "erase 0xffc00000 0xffc1ffff; "                 \
  25                 "cp.b 0x20000 0xffc00000 ${filesize}\0"         \
  26         "upgrade_kernel=loady; "                                \
  27                 "erase 0xffc20000 0xffefffff; "                 \
  28                 "cp.b 0x20000 0xffc20000 ${filesize}\0"         \
  29         "upgrade_jffs2=loady; "                                 \
  30                 "erase 0xfff00000 0xffffffff; "                 \
  31                 "cp.b 0x20000 0xfff00000 ${filesize}\0"
  32
  33 /* undef to save memory */
  34 #undef  CONFIG_SYS_LONGHELP
  35
  36 /* max number of command args   */
  37 #define CONFIG_SYS_MAXARGS              16
  38 /* Boot argument buffer size    */
  39 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  40
  41 #define CONFIG_AUTO_COMPLETE            1 /* add autocompletion support */
  42 #define CONFIG_MX_CYCLIC                1 /* enable mdc/mwc commands    */
  43
  44 #define CONFIG_SYS_LOAD_ADDR            0x20000 /* default load address */
  45
  46 #define CONFIG_SYS_MEMTEST_START        0x0
  47 #define CONFIG_SYS_MEMTEST_END          0x1000000
  48
  49 #define CONFIG_SYS_HZ                   1000
  50
  51 #define CONFIG_SYS_CLK                  45000000
  52 #define CONFIG_SYS_CPU_CLK              (CONFIG_SYS_CLK * 2)
  53 /* Register Base Addrs */
  54 #define CONFIG_SYS_MBAR                 0x10000000
  55 /* Definitions for initial stack pointer and data area (in DPRAM) */
  56 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  57 /* size of internal SRAM */
  58 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
  59 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  60                                          GENERATED_GBL_DATA_SIZE)
  61 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  62
  63 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  64 #define CONFIG_SYS_SDRAM_SIZE           0x1000000
  65 #define CONFIG_SYS_FLASH_BASE           0xffc00000
  66 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  67 #define CONFIG_SYS_MAX_FLASH_SECT       1024
  68 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
  69
  70 #define CONFIG_SYS_FLASH_CFI
  71 #define CONFIG_FLASH_CFI_DRIVER
  72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  73 /* amcore design has flash data bytes wired swapped */
  74 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  75 /* reserve 128-4KB */
  76 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
  77 #define CONFIG_SYS_MONITOR_LEN          ((128 - 4) * 1024)
  78 #define CONFIG_SYS_MALLOC_LEN           (1 * 1024 * 1024)
  79 #define CONFIG_SYS_BOOTPARAMS_LEN       (64 * 1024)
  80
  81 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + \
  82                                          CONFIG_SYS_MONITOR_LEN)
  83 #define CONFIG_ENV_SIZE                 0x1000
  84 #define CONFIG_ENV_SECT_SIZE            0x1000
  85
  86 #define LDS_BOARD_TEXT \
  87         . = DEFINED(env_offset) ? env_offset : .; \
  88         env/embedded.o(.text*);
  89
  90 /* memory map space for linux boot data */
  91 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
  92
  93 /*
  94  * Cache Configuration
  95  *
  96  * Special 8K version 3 core cache.
  97  * This is a single unified instruction/data cache.
  98  * sdram - single region - no masks
  99  */
 100 #define CONFIG_SYS_CACHELINE_SIZE       16
 101
 102 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 103                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 104 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 105                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 106 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 107 #define CONFIG_SYS_CACHE_ACR0           (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
 108                                          CF_ACR_EN)
 109 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_DCM_P | CF_CACR_ESB | \
 110                                          CF_CACR_EC)
 111
 112 /* CS0 - AMD Flash, address 0xffc00000 */
 113 #define CONFIG_SYS_CS0_BASE             (CONFIG_SYS_FLASH_BASE>>16)
 114 /* 4MB, AA=0,V=1  C/I BIT for errata */
 115 #define CONFIG_SYS_CS0_MASK             0x003f0001
 116 /* WS=10, AA=1, PS=16bit (10) */
 117 #define CONFIG_SYS_CS0_CTRL             0x1980
 118 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
 119 #define CONFIG_SYS_CS1_BASE             0x3000
 120 #define CONFIG_SYS_CS1_MASK             0x00070001
 121 #define CONFIG_SYS_CS1_CTRL             0x0100
 122
 123 #endif  /* __AMCORE_CONFIG_H */
 124