2 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
4 * Author: Srinath.R <srinath@mistralsolutions.com>
6 * Based on include/configs/am3517evm.h
8 * Copyright (C) 2011 Mistral Solutions pvt Ltd
10 * SPDX-License-Identifier: GPL-2.0+
17 * High Level Configuration Options
19 #define CONFIG_OMAP 1 /* in a TI OMAP core */
20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
21 #define CONFIG_OMAP_COMMON
22 /* Common ARM Erratas */
23 #define CONFIG_ARM_ERRATA_454179
24 #define CONFIG_ARM_ERRATA_430973
25 #define CONFIG_ARM_ERRATA_621766
27 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
29 #include <asm/arch/cpu.h> /* get chip and board defs */
30 #include <asm/arch/omap.h>
33 * Display CPU and Board information
35 #define CONFIG_DISPLAY_CPUINFO 1
36 #define CONFIG_DISPLAY_BOARDINFO 1
39 #define V_OSCK 26000000 /* Clock output from T2 */
40 #define V_SCLK (V_OSCK >> 1)
42 #define CONFIG_MISC_INIT_R
44 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
45 #define CONFIG_SETUP_MEMORY_TAGS 1
46 #define CONFIG_INITRD_TAG 1
47 #define CONFIG_REVISION_TAG 1
50 * Size of malloc() pool
52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
53 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
58 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
65 * NS16550 Configuration
67 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
69 #define CONFIG_SYS_NS16550_SERIAL
70 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
71 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
74 * select serial console configuration
76 #define CONFIG_CONS_INDEX 3
77 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
78 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
80 /* allow to overwrite serial and ethaddr */
81 #define CONFIG_ENV_OVERWRITE
82 #define CONFIG_BAUDRATE 115200
83 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
85 #define CONFIG_GENERIC_MMC 1
87 #define CONFIG_OMAP_HSMMC 1
88 #define CONFIG_DOS_PARTITION 1
92 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
93 * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
95 #define CONFIG_USB_AM35X 1
96 #define CONFIG_USB_MUSB_HCD 1
98 #ifdef CONFIG_USB_AM35X
100 #ifdef CONFIG_USB_MUSB_HCD
101 #define CONFIG_CMD_USB
103 #define CONFIG_USB_STORAGE
104 #define CONGIG_CMD_STORAGE
105 #define CONFIG_CMD_FAT
107 #ifdef CONFIG_USB_KEYBOARD
108 #define CONFIG_SYS_USB_EVENT_POLL
109 #define CONFIG_PREBOOT "usb start"
110 #endif /* CONFIG_USB_KEYBOARD */
112 #endif /* CONFIG_USB_MUSB_HCD */
114 #ifdef CONFIG_USB_MUSB_UDC
115 /* USB device configuration */
116 #define CONFIG_USB_DEVICE 1
117 #define CONFIG_USB_TTY 1
118 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
119 /* Change these to suit your needs */
120 #define CONFIG_USBD_VENDORID 0x0451
121 #define CONFIG_USBD_PRODUCTID 0x5678
122 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
123 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
124 #endif /* CONFIG_USB_MUSB_UDC */
126 #endif /* CONFIG_USB_AM35X */
128 /* commands to include */
129 #define CONFIG_CMD_EXT2 /* EXT2 Support */
130 #define CONFIG_CMD_FAT /* FAT support */
131 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
133 #define CONFIG_CMD_I2C /* I2C serial bus support */
134 #define CONFIG_CMD_MMC /* MMC support */
135 #define CONFIG_CMD_NAND /* NAND support */
136 #define CONFIG_CMD_DHCP
137 #undef CONFIG_CMD_PING
140 #define CONFIG_SYS_NO_FLASH
141 #define CONFIG_SYS_I2C
142 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
143 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
144 #define CONFIG_SYS_I2C_OMAP34XX
149 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
151 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
158 #define CONFIG_JFFS2_NAND
159 /* nand device jffs2 lives on */
160 #define CONFIG_JFFS2_DEV "nand0"
161 /* start of jffs2 partition */
162 #define CONFIG_JFFS2_PART_OFFSET 0x680000
163 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
165 /* Environment information */
166 #define CONFIG_BOOTDELAY 10
168 #define CONFIG_BOOTFILE "uImage"
170 #define CONFIG_EXTRA_ENV_SETTINGS \
171 "loadaddr=0x82000000\0" \
172 "console=ttyS2,115200n8\0" \
174 "mmcargs=setenv bootargs console=${console} " \
175 "root=/dev/mmcblk0p2 rw " \
176 "rootfstype=ext3 rootwait\0" \
177 "nandargs=setenv bootargs console=${console} " \
178 "root=/dev/mtdblock4 rw " \
179 "rootfstype=jffs2\0" \
180 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
181 "bootscript=echo Running bootscript from mmc ...; " \
182 "source ${loadaddr}\0" \
183 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
184 "mmcboot=echo Booting from mmc ...; " \
186 "bootm ${loadaddr}\0" \
187 "nandboot=echo Booting from nand ...; " \
189 "nand read ${loadaddr} 280000 400000; " \
190 "bootm ${loadaddr}\0" \
192 #define CONFIG_BOOTCOMMAND \
193 "mmc dev ${mmcdev}; if mmc rescan; then " \
194 "if run loadbootscript; then " \
197 "if run loaduimage; then " \
199 "else run nandboot; " \
202 "else run nandboot; fi"
204 #define CONFIG_AUTO_COMPLETE 1
206 * Miscellaneous configurable options
208 #define CONFIG_SYS_LONGHELP /* undef to save memory */
209 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
210 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
211 /* Print Buffer Size */
212 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
213 sizeof(CONFIG_SYS_PROMPT) + 16)
214 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
216 /* Boot Argument Buffer Size */
217 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
218 /* memtest works on */
219 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
220 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
221 0x01F00000) /* 31MB */
223 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
227 * AM3517 has 12 GP timers, they can be driven by the system clock
228 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
229 * This rate is divided by a local divisor.
231 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
232 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
234 /*-----------------------------------------------------------------------
235 * Physical Memory Map
237 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
238 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
239 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
241 /*-----------------------------------------------------------------------
242 * FLASH and environment organization
245 /* **** PISMO SUPPORT *** */
246 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
248 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
249 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
251 #define CONFIG_SYS_FLASH_BASE NAND_BASE
253 /* Monitor at start of flash */
254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
256 #define CONFIG_NAND_OMAP_GPMC
257 #define CONFIG_ENV_IS_IN_NAND 1
258 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
260 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
261 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
262 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
264 /*-----------------------------------------------------------------------
265 * CFI FLASH driver setup
267 /* timeout values are in ticks */
268 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
269 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
271 /* Flash banks JFFS2 should use */
272 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
273 CONFIG_SYS_MAX_NAND_DEVICE)
274 #define CONFIG_SYS_JFFS2_MEM_NAND
275 /* use flash_info[2] */
276 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
277 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
279 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
280 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
281 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
282 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
283 CONFIG_SYS_INIT_RAM_SIZE - \
284 GENERATED_GBL_DATA_SIZE)
286 /* Defines for SPL */
287 #define CONFIG_SPL_FRAMEWORK
288 #define CONFIG_SPL_BOARD_INIT
289 #define CONFIG_SPL_NAND_SIMPLE
290 #define CONFIG_SPL_TEXT_BASE 0x40200800
291 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
293 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
294 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
296 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
297 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
298 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
299 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
301 #define CONFIG_SPL_LIBCOMMON_SUPPORT
302 #define CONFIG_SPL_LIBDISK_SUPPORT
303 #define CONFIG_SPL_I2C_SUPPORT
304 #define CONFIG_SPL_LIBGENERIC_SUPPORT
305 #define CONFIG_SPL_MMC_SUPPORT
306 #define CONFIG_SPL_FAT_SUPPORT
307 #define CONFIG_SPL_SERIAL_SUPPORT
308 #define CONFIG_SPL_NAND_SUPPORT
309 #define CONFIG_SPL_NAND_BASE
310 #define CONFIG_SPL_NAND_DRIVERS
311 #define CONFIG_SPL_NAND_ECC
312 #define CONFIG_SPL_POWER_SUPPORT
313 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
315 /* NAND boot config */
316 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
317 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
318 #define CONFIG_SYS_NAND_PAGE_COUNT 64
319 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
320 #define CONFIG_SYS_NAND_OOBSIZE 64
321 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
322 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
323 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
325 #define CONFIG_SYS_NAND_ECCSIZE 512
326 #define CONFIG_SYS_NAND_ECCBYTES 3
327 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
328 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
329 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
332 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
333 * 64 bytes before this address should be set aside for u-boot.img's
334 * header. That is 0x800FFFC0--0x80100000 should not be used for any
337 #define CONFIG_SYS_TEXT_BASE 0x80100000
338 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
339 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
341 #endif /* __CONFIG_H */