2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38 #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39 #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
40 #define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
41 #define CONFIG_AEVFIFO 1
42 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
44 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
45 #define BOOTFLAG_WARM 0x02 /* Software reboot */
48 * Serial console configuration
50 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
51 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
52 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
61 #define CONFIG_PCI_PNP 1
62 /* #define CONFIG_PCI_SCAN_SHOW 1 */
64 #define CONFIG_PCI_MEM_BUS 0x40000000
65 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
66 #define CONFIG_PCI_MEM_SIZE 0x10000000
68 #define CONFIG_PCI_IO_BUS 0x50000000
69 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
70 #define CONFIG_PCI_IO_SIZE 0x01000000
72 #define CONFIG_NET_MULTI 1
73 #define CONFIG_EEPRO100 1
74 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
75 #define CONFIG_NS8382X 1
76 #endif /* CONFIG_AEVFIFO */
79 #define CONFIG_MAC_PARTITION
80 #define CONFIG_DOS_PARTITION
81 #define CONFIG_ISO_PARTITION
84 #define CONFIG_POST (CFG_POST_MEMORY | \
89 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
90 /* preserve space for the post_word at end of on-chip SRAM */
91 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
93 #define CFG_CMD_POST_DIAG 0
98 * Command line configuration.
100 #include <config_cmd_default.h>
102 #define CONFIG_CMD_ASKENV
103 #define CONFIG_CMD_DATE
104 #define CONFIG_CMD_DHCP
105 #define CONFIG_CMD_ECHO
106 #define CONFIG_CMD_EEPROM
107 #define CONFIG_CMD_I2C
108 #define CONFIG_CMD_MII
109 #define CONFIG_CMD_NFS
110 #define CONFIG_CMD_PCI
111 #define CONFIG_CMD_PING
112 #define CONFIG_CMD_POST
113 #define CONFIG_CMD_REGINFO
114 #define CONFIG_CMD_SNTP
117 #define CONFIG_TIMESTAMP /* display image timestamps */
119 #if (TEXT_BASE == 0xFC000000) /* Boot low */
120 # define CFG_LOWBOOT 1
126 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
128 #define CONFIG_PREBOOT "echo;" \
129 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
132 #undef CONFIG_BOOTARGS
134 #define CONFIG_EXTRA_ENV_SETTINGS \
136 "rootpath=/opt/eldk/ppc_6xx\0" \
137 "ramargs=setenv bootargs root=/dev/ram rw\0" \
138 "nfsargs=setenv bootargs root=/dev/nfs rw " \
139 "nfsroot=${serverip}:${rootpath} " \
140 "console=ttyS0,${baudrate}\0" \
141 "addip=setenv bootargs ${bootargs} " \
142 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
143 ":${hostname}:${netdev}:off panic=1\0" \
144 "flash_self=run ramargs addip;" \
145 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
146 "flash_nfs=run nfsargs addip;" \
147 "bootm ${kernel_addr}\0" \
148 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
149 "bootfile=/tftpboot/tqm5200/uImage\0" \
150 "load=tftp 200000 ${u-boot}\0" \
151 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
152 "update=protect off FC000000 FC05FFFF;" \
153 "erase FC000000 FC05FFFF;" \
154 "cp.b 200000 FC000000 ${filesize};" \
155 "protect on FC000000 FC05FFFF\0" \
158 #define CONFIG_BOOTCOMMAND "run net_nfs"
161 * IPB Bus clocking configuration.
163 #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
165 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
167 * PCI Bus clocking configuration
169 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
170 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
171 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
173 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
179 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
180 #ifdef CONFIG_TQM5200_REV100
181 #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
183 #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
187 * I2C clock frequency
189 * Please notice, that the resulting clock frequency could differ from the
190 * configured value. This is because the I2C clock is derived from system
191 * clock over a frequency divider with only a few divider values. U-boot
192 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
193 * approximation allways lies below the configured value, never above.
195 #define CFG_I2C_SPEED 100000 /* 100 kHz */
196 #define CFG_I2C_SLAVE 0x7F
199 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
200 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
201 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
202 * same configuration could be used.
204 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
205 #define CFG_I2C_EEPROM_ADDR_LEN 2
206 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
207 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
210 * Flash configuration
212 #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
214 /* use CFI flash driver if no module variant is spezified */
215 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
216 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
217 #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
218 #define CFG_FLASH_EMPTY_INFO
219 #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
220 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
221 #undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
223 #if !defined(CFG_LOWBOOT)
224 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
225 #else /* CFG_LOWBOOT */
226 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
227 #endif /* CFG_LOWBOOT */
228 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
230 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
231 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
235 * Environment settings
237 #define CFG_ENV_IS_IN_FLASH 1
238 #define CFG_ENV_SIZE 0x10000
239 #define CFG_ENV_SECT_SIZE 0x20000
240 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
241 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
246 #define CFG_MBAR 0xF0000000
247 #define CFG_SDRAM_BASE 0x00000000
248 #define CFG_DEFAULT_MBAR 0x80000000
250 /* Use ON-Chip SRAM until RAM will be available */
251 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
253 /* preserve space for the post_word at end of on-chip SRAM */
254 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
256 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
260 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
261 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
262 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
264 #define CFG_MONITOR_BASE TEXT_BASE
265 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
266 # define CFG_RAMBOOT 1
269 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
270 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
271 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
274 * Ethernet configuration
276 #define CONFIG_MPC5xxx_FEC 1
278 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
280 /* #define CONFIG_FEC_10MBIT 1 */
281 #define CONFIG_PHY_ADDR 0x00
286 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
287 * Bit 0 (mask: 0x80000000): 1
288 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
289 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
290 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
291 * Use for REV200 STK52XX boards. Do not use with REV100 modules
292 * (because, there I2C1 is used as I2C bus)
293 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
294 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
295 * 000 -> All PSC2 pins are GIOPs
296 * 001 -> CAN1/2 on PSC2 pins
297 * Use for REV100 STK52xx boards
300 * use as UART. Pins PSC6_0 to PSC6_3 are used.
301 * Bits 9:11 (mask: 0x00700000):
302 * 101 -> PSC6 : Extended POST test is not available
303 * on MINI-FAP and TQM5200_IB:
304 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
305 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
306 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
309 #define CFG_GPS_PORT_CONFIG 0x81500014
314 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
317 * Miscellaneous configurable options
319 #define CFG_LONGHELP /* undef to save memory */
320 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
321 #if defined(CONFIG_CMD_KGDB)
322 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
324 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
326 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
327 #define CFG_MAXARGS 16 /* max number of command args */
328 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
330 /* Enable an alternate, more extensive memory test */
331 #define CFG_ALT_MEMTEST
333 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
334 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
336 #define CFG_LOAD_ADDR 0x100000 /* default load address */
338 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
340 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
341 #if defined(CONFIG_CMD_KGDB)
342 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
346 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
347 * which is normally part of the default commands (CFV_CMD_DFL)
352 * Various low-level settings
354 #if defined(CONFIG_MPC5200)
355 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
356 #define CFG_HID0_FINAL HID0_ICE
358 #define CFG_HID0_INIT 0
359 #define CFG_HID0_FINAL 0
362 #define CFG_BOOTCS_START CFG_FLASH_BASE
363 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
364 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
365 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
367 #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
369 #define CFG_CS0_START CFG_FLASH_BASE
370 #define CFG_CS0_SIZE CFG_FLASH_SIZE
372 #define CONFIG_LAST_STAGE_INIT
375 * SRAM - Do not map below 2 GB in address space, because this area is used
376 * for SDRAM autosizing.
378 #define CFG_CS2_START 0xE5000000
379 #define CFG_CS2_SIZE 0x80000 /* 512 kByte */
380 #define CFG_CS2_CFG 0x0004D930
383 * Grafic controller - Do not map below 2 GB in address space, because this
384 * area is used for SDRAM autosizing.
386 #define SM501_FB_BASE 0xE0000000
387 #define CFG_CS1_START (SM501_FB_BASE)
388 #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
389 #define CFG_CS1_CFG 0x8F48FF70
390 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
392 #define CFG_CS_BURST 0x00000000
393 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
395 #define CFG_RESET_ADDRESS 0xff000000
397 #endif /* __CONFIG_H */