2 * (C) Copyright 2007, 2008 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * ADS5121 board configuration file
30 #define CONFIG_ADS5121 1
32 * Memory map for the ADS5121 board:
34 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
35 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
36 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
37 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
38 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
39 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
40 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
41 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
45 * High Level Configuration Options
47 #define CONFIG_E300 1 /* E300 Family */
48 #define CONFIG_MPC512X 1 /* MPC512X family */
49 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
54 #if defined(CONFIG_VIDEO)
55 #define CONFIG_CFB_CONSOLE
56 #define CONFIG_VGA_AS_SINGLE_DEVICE
59 /* CONFIG_PCI is defined at config time */
61 #define CFG_MPC512X_CLKIN 66000000 /* in Hz */
63 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
64 #define CONFIG_MISC_INIT_R
66 #define CFG_IMMR 0x80000000
67 #define CFG_DIU_ADDR (CFG_IMMR+0x2100)
69 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
70 #define CFG_MEMTEST_END 0x00400000
73 * DDR Setup - manually set all parameters as there's no SPD etc.
75 #define CFG_DDR_SIZE 256 /* MB */
76 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
77 #define CFG_SDRAM_BASE CFG_DDR_BASE
79 /* DDR Controller Configuration
82 * [31:31] MDDRC Soft Reset: Diabled
83 * [30:30] DRAM CKE pin: Enabled
84 * [29:29] DRAM CLK: Enabled
85 * [28:28] Command Mode: Enabled (For initialization only)
86 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
87 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
88 * [20:19] Read Test: DON'T USE
89 * [18:18] Self Refresh: Enabled
90 * [17:17] 16bit Mode: Disabled
91 * [16:13] Ready Delay: 2
92 * [12:12] Half DQS Delay: Disabled
93 * [11:11] Quarter DQS Delay: Disabled
94 * [10:08] Write Delay: 2
95 * [07:07] Early ODT: Disabled
96 * [06:06] On DIE Termination: Disabled
97 * [05:05] FIFO Overflow Clear: DON'T USE here
98 * [04:04] FIFO Underflow Clear: DON'T USE here
99 * [03:03] FIFO Overflow Pending: DON'T USE here
100 * [02:02] FIFO Underlfow Pending: DON'T USE here
101 * [01:01] FIFO Overlfow Enabled: Enabled
102 * [00:00] FIFO Underflow Enabled: Enabled
104 * [31:16] DRAM Refresh Time: 0 CSB clocks
105 * [15:8] DRAM Command Time: 0 CSB clocks
106 * [07:00] DRAM Precharge Time: 0 CSB clocks
110 * [20:17] DRAM tWRT1:
117 * [22:19] DRAM tRTW1:
124 #define CFG_MDDRC_SYS_CFG 0xF8604A00
125 #define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
126 #define CFG_MDDRC_SYS_CFG_EN 0xF0000000
127 #define CFG_MDDRC_TIME_CFG0 0x00003D2E
128 #define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
129 #define CFG_MDDRC_TIME_CFG1 0x54EC1168
130 #define CFG_MDDRC_TIME_CFG2 0x35210864
132 #define CFG_MICRON_NOP 0x01380000
133 #define CFG_MICRON_PCHG_ALL 0x01100400
134 #define CFG_MICRON_EM2 0x01020000
135 #define CFG_MICRON_EM3 0x01030000
136 #define CFG_MICRON_EN_DLL 0x01010000
137 #define CFG_MICRON_RFSH 0x01080000
138 #define CFG_MICRON_INIT_DEV_OP 0x01000432
139 #define CFG_MICRON_OCD_DEFAULT 0x01010780
141 /* DDR Priority Manager Configuration */
142 #define CFG_MDDRCGRP_PM_CFG1 0x00077777
143 #define CFG_MDDRCGRP_PM_CFG2 0x00000000
144 #define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001
145 #define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC
146 #define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA
147 #define CFG_MDDRCGRP_LUT1_MU 0x66666666
148 #define CFG_MDDRCGRP_LUT1_ML 0x55555555
149 #define CFG_MDDRCGRP_LUT2_MU 0x44444444
150 #define CFG_MDDRCGRP_LUT2_ML 0x44444444
151 #define CFG_MDDRCGRP_LUT3_MU 0x55555555
152 #define CFG_MDDRCGRP_LUT3_ML 0x55555558
153 #define CFG_MDDRCGRP_LUT4_MU 0x11111111
154 #define CFG_MDDRCGRP_LUT4_ML 0x11111122
155 #define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa
156 #define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa
157 #define CFG_MDDRCGRP_LUT1_AU 0x66666666
158 #define CFG_MDDRCGRP_LUT1_AL 0x66666666
159 #define CFG_MDDRCGRP_LUT2_AU 0x11111111
160 #define CFG_MDDRCGRP_LUT2_AL 0x11111111
161 #define CFG_MDDRCGRP_LUT3_AU 0x11111111
162 #define CFG_MDDRCGRP_LUT3_AL 0x11111111
163 #define CFG_MDDRCGRP_LUT4_AU 0x11111111
164 #define CFG_MDDRCGRP_LUT4_AL 0x11111111
167 * NOR FLASH on the Local Bus
169 #define CFG_FLASH_CFI /* use the Common Flash Interface */
170 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
171 #define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
172 #define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
173 #define CFG_FLASH_USE_BUFFER_WRITE
175 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
176 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
177 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
179 #undef CFG_FLASH_CHECKSUM
182 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
185 #define CFG_CPLD_BASE 0x82000000
186 #define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
188 #define CFG_SRAM_BASE 0x30000000
189 #define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
191 #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
192 #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
194 /* Use SRAM for initial stack */
195 #define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
196 #define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
198 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
199 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
200 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
202 #define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
203 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
204 #ifdef CONFIG_FSL_DIU_FB
205 #define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
207 #define CFG_MALLOC_LEN (512 * 1024)
213 #define CONFIG_CONS_INDEX 1
214 #undef CONFIG_SERIAL_SOFTWARE_FIFO
217 * Serial console configuration
219 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
220 #if CONFIG_PSC_CONSOLE != 3
221 #error CONFIG_PSC_CONSOLE must be 3
223 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
224 #define CFG_BAUDRATE_TABLE \
225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
227 #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
228 #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
229 #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
230 #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
232 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
233 /* Use the HUSH parser */
234 #define CFG_HUSH_PARSER
235 #ifdef CFG_HUSH_PARSER
236 #define CFG_PROMPT_HUSH_PS2 "> "
247 #define CFG_PCI_MEM_BASE 0xA0000000
248 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
249 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
250 #define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
251 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
252 #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
253 #define CFG_PCI_IO_BASE 0x00000000
254 #define CFG_PCI_IO_PHYS 0x84000000
255 #define CFG_PCI_IO_SIZE 0x01000000 /* 16M */
258 #define CONFIG_PCI_PNP /* do pci plug-and-play */
260 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
265 #define CONFIG_HARD_I2C /* I2C with hardware support */
266 #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
267 #define CONFIG_I2C_MULTI_BUS
268 #define CONFIG_I2C_CMD_TREE
269 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
270 #define CFG_I2C_SLAVE 0x7F
272 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
276 * EEPROM configuration
278 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
279 #define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
280 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
281 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
284 * Ethernet configuration
286 #define CONFIG_MPC512x_FEC 1
287 #define CONFIG_NET_MULTI
288 #define CONFIG_PHY_ADDR 0x1
289 #define CONFIG_MII 1 /* MII PHY management */
293 * Configure on-board RTC
295 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
296 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
302 #define CFG_ENV_IS_IN_FLASH 1
303 /* This has to be a multiple of the Flash sector size */
304 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
305 #define CFG_ENV_SIZE 0x2000
306 #define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
308 /* Address and size of Redundant Environment Sector */
309 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
310 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
312 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
313 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
315 #include <config_cmd_default.h>
317 #define CONFIG_CMD_ASKENV
318 #define CONFIG_CMD_DHCP
319 #define CONFIG_CMD_I2C
320 #define CONFIG_CMD_MII
321 #define CONFIG_CMD_NFS
322 #define CONFIG_CMD_PING
323 #define CONFIG_CMD_REGINFO
324 #define CONFIG_CMD_EEPROM
326 #if defined(CONFIG_PCI)
327 #define CONFIG_CMD_PCI
331 * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
332 * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
333 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
334 * to chapter 36 of the MPC5121e Reference Manual.
336 /* #define CONFIG_WATCHDOG */ /* enable watchdog */
337 #define CFG_WATCHDOG_VALUE 0xFFFF
340 * Miscellaneous configurable options
342 #define CFG_LONGHELP /* undef to save memory */
343 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
344 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
346 #ifdef CONFIG_CMD_KGDB
347 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
349 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
353 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
354 #define CFG_MAXARGS 16 /* max number of command args */
355 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
356 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
359 * For booting Linux, the board info and command line data
360 * have to be in the first 8 MB of memory, since this is
361 * the maximum mapped by the Linux kernel during initialization.
363 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
365 /* Cache Configuration */
366 #define CFG_DCACHE_SIZE 32768
367 #define CFG_CACHELINE_SIZE 32
368 #ifdef CONFIG_CMD_KGDB
369 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
372 #define CFG_HID0_INIT 0x000000000
373 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
374 #define CFG_HID2 HID2_HBE
376 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
379 * Internal Definitions
383 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
384 #define BOOTFLAG_WARM 0x02 /* Software reboot */
386 #ifdef CONFIG_CMD_KGDB
387 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
388 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
392 * Environment Configuration
394 #define CONFIG_TIMESTAMP
396 #define CONFIG_HOSTNAME ads5121
397 #define CONFIG_BOOTFILE ads5121/uImage
398 #define CONFIG_ROOTPATH /opt/eldk/pcc_6xx
400 #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
402 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
403 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
405 #define CONFIG_BAUDRATE 115200
407 #define CONFIG_PREBOOT "echo;" \
408 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
411 #define CONFIG_EXTRA_ENV_SETTINGS \
412 "u-boot_addr_r=200000\0" \
413 "kernel_addr_r=300000\0" \
414 "fdt_addr_r=400000\0" \
415 "ramdisk_addr_r=500000\0" \
416 "u-boot_addr=FFF00000\0" \
417 "kernel_addr=FC040000\0" \
418 "fdt_addr=FC2C0000\0" \
419 "ramdisk_addr=FC300000\0" \
420 "ramdiskfile=ads5121/uRamdisk\0" \
421 "fdtfile=ads5121/ads5121.dtb\0" \
422 "u-boot=ads5121/u-boot.bin\0" \
424 "consdev=ttyPSC0\0" \
425 "nfsargs=setenv bootargs root=/dev/nfs rw " \
426 "nfsroot=${serverip}:${rootpath}\0" \
427 "ramargs=setenv bootargs root=/dev/ram rw\0" \
428 "addip=setenv bootargs ${bootargs} " \
429 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
430 ":${hostname}:${netdev}:off panic=1\0" \
431 "addtty=setenv bootargs ${bootargs} " \
432 "console=${consdev},${baudrate}\0" \
433 "flash_nfs=run nfsargs addip addtty;" \
434 "bootm ${kernel_addr} - ${fdt_addr}\0" \
435 "flash_self=run ramargs addip addtty;" \
436 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
437 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
438 "tftp ${fdt_addr_r} ${fdtfile};" \
439 "run nfsargs addip addtty;" \
440 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
441 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
442 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
443 "tftp ${fdt_addr_r} ${fdtfile};" \
444 "run ramargs addip addtty;" \
445 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
446 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
447 "update=protect off ${u-boot_addr} +${filesize};" \
448 "era ${u-boot_addr} +${filesize};" \
449 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
450 "upd=run load update\0" \
453 #define CONFIG_BOOTCOMMAND "run flash_self"
455 #define CONFIG_OF_LIBFDT 1
456 #define CONFIG_OF_BOARD_SETUP 1
458 #define OF_CPU "PowerPC,5121@0"
459 #define OF_SOC "soc@80000000"
460 #define OF_SOC_OLD "soc5121@80000000"
461 #define OF_TBCLK (bd->bi_busfreq / 4)
462 #define OF_STDOUT_PATH "/soc@80000000/serial@11300"
464 #endif /* __CONFIG_H */