include/configs/adp-ag101p.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include <asm/arch-ag101/ag101.h>
  13
  14 /*
  15  * CPU and Board Configuration Options
  16  */
  17 #define CONFIG_USE_INTERRUPT
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_CMDLINE_EDITING
  22
  23 #define CONFIG_ARCH_MAP_SYSMEM
  24
  25 #define CONFIG_BOOTP_SEND_HOSTNAME
  26 #define CONFIG_BOOTP_SERVERIP
  27
  28 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  29 #define CONFIG_MEM_REMAP
  30 #endif
  31
  32 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  33 #define CONFIG_SYS_TEXT_BASE    0x00500000
  34 #ifdef CONFIG_OF_CONTROL
  35 #undef CONFIG_OF_SEPARATE
  36 #define CONFIG_OF_EMBED
  37 #endif
  38 #else
  39 #ifdef CONFIG_MEM_REMAP
  40 #define CONFIG_SYS_TEXT_BASE    0x80000000
  41 #else
  42 #define CONFIG_SYS_TEXT_BASE    0x00000000
  43 #endif
  44 #endif
  45
  46 /*
  47  * Timer
  48  */
  49 #define CONFIG_SYS_CLK_FREQ     39062500
  50 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  51
  52 /*
  53  * Use Externel CLOCK or PCLK
  54  */
  55 #undef CONFIG_FTRTC010_EXTCLK
  56
  57 #ifndef CONFIG_FTRTC010_EXTCLK
  58 #define CONFIG_FTRTC010_PCLK
  59 #endif
  60
  61 #ifdef CONFIG_FTRTC010_EXTCLK
  62 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  63 #else
  64 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  65 #endif
  66
  67 #define TIMER_LOAD_VAL  0xffffffff
  68
  69 /*
  70  * Real Time Clock
  71  */
  72 #define CONFIG_RTC_FTRTC010
  73
  74 /*
  75  * Real Time Clock Divider
  76  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  77  */
  78 #define OSC_5MHZ                        (5*1000000)
  79 #define OSC_CLK                         (4*OSC_5MHZ)
  80 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  81
  82 /*
  83  * Serial console configuration
  84  */
  85
  86 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  87 #define CONFIG_CONS_INDEX               1
  88 #define CONFIG_SYS_NS16550_SERIAL
  89 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  90 #ifndef CONFIG_DM_SERIAL
  91 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  92 #endif
  93 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  94
  95 /*
  96  * SD (MMC) controller
  97  */
  98 #define CONFIG_FTSDC010_NUMBER          1
  99 #define CONFIG_FTSDC010_SDIO
 100
 101 /*
 102  * Miscellaneous configurable options
 103  */
 104 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 105
 106 /*
 107  * Size of malloc() pool
 108  */
 109 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
 110 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 111
 112 /*
 113  * AHB Controller configuration
 114  */
 115 #define CONFIG_FTAHBC020S
 116
 117 #ifdef CONFIG_FTAHBC020S
 118 #include <faraday/ftahbc020s.h>
 119
 120 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 121 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 122
 123 /*
 124  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 125  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 126  * in C language.
 127  */
 128 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 129         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 130                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 131 #endif
 132
 133 /*
 134  * Watchdog
 135  */
 136 #define CONFIG_FTWDT010_WATCHDOG
 137
 138 /*
 139  * PMU Power controller configuration
 140  */
 141 #define CONFIG_PMU
 142 #define CONFIG_FTPMU010_POWER
 143
 144 #ifdef CONFIG_FTPMU010_POWER
 145 #include <faraday/ftpmu010.h>
 146 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 147 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 148                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 149                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 150                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 151                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 152                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 153                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 154 #endif
 155
 156 /*
 157  * SDRAM controller configuration
 158  */
 159 #define CONFIG_FTSDMC021
 160
 161 #ifdef CONFIG_FTSDMC021
 162 #include <faraday/ftsdmc021.h>
 163
 164 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 165                                          FTSDMC021_TP1_TRP(1)   |       \
 166                                          FTSDMC021_TP1_TRCD(1)  |       \
 167                                          FTSDMC021_TP1_TRF(3)   |       \
 168                                          FTSDMC021_TP1_TWR(1)   |       \
 169                                          FTSDMC021_TP1_TCL(2))
 170
 171 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 172                                          FTSDMC021_TP2_INI_REFT(8) |    \
 173                                          FTSDMC021_TP2_REF_INTV(0x180))
 174
 175 /*
 176  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 177  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 178  * C language.
 179  */
 180 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 181                                          FTSDMC021_CR1_DSZ(3)    |      \
 182                                          FTSDMC021_CR1_MBW(2)    |      \
 183                                          FTSDMC021_CR1_BNKSIZE(6))
 184
 185 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 186                                          FTSDMC021_CR2_IREF      |      \
 187                                          FTSDMC021_CR2_ISMR)
 188
 189 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 190 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 191                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 192
 193 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 194         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 195 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 196                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 197 #endif
 198
 199 /*
 200  * Physical Memory Map
 201  */
 202 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 203 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 204 #else
 205 #ifdef CONFIG_MEM_REMAP
 206 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 207 #else
 208 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 209 #endif
 210 #endif
 211
 212 #define PHYS_SDRAM_1 \
 213         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 214
 215 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 216
 217 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 218 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 219 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 220 #else
 221 #ifdef CONFIG_MEM_REMAP
 222 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 223 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 224 #else
 225 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 226 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 227 #endif
 228 #endif
 229
 230 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 231
 232 #ifdef CONFIG_MEM_REMAP
 233 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 234                                         GENERATED_GBL_DATA_SIZE)
 235 #else
 236 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 237                                         GENERATED_GBL_DATA_SIZE)
 238 #endif /* CONFIG_MEM_REMAP */
 239
 240 /*
 241  * Load address and memory test area should agree with
 242  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 243  */
 244 #define CONFIG_SYS_LOAD_ADDR            0x300000
 245
 246 /* memtest works on 63 MB in DRAM */
 247 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 248 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 249
 250 /*
 251  * Static memory controller configuration
 252  */
 253 #define CONFIG_FTSMC020
 254
 255 #ifdef CONFIG_FTSMC020
 256 #include <faraday/ftsmc020.h>
 257
 258 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 259         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 260         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 261 }
 262
 263 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 264 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 265                                          FTSMC020_BANK_SIZE_32M |       \
 266                                          FTSMC020_BANK_MBW_32)
 267
 268 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 269                                          FTSMC020_TPR_AST(1)    |       \
 270                                          FTSMC020_TPR_CTW(1)    |       \
 271                                          FTSMC020_TPR_ATI(1)    |       \
 272                                          FTSMC020_TPR_AT2(1)    |       \
 273                                          FTSMC020_TPR_WTC(1)    |       \
 274                                          FTSMC020_TPR_AHT(1)    |       \
 275                                          FTSMC020_TPR_TRNA(1))
 276 #endif
 277
 278 /*
 279  * FLASH on ADP_AG101P is connected to BANK0
 280  * Just disalbe the other BANK to avoid detection error.
 281  */
 282 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 283                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 284                                  FTSMC020_BANK_SIZE_32M           |     \
 285                                  FTSMC020_BANK_MBW_32)
 286
 287 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 288                                  FTSMC020_TPR_CTW(3)   |        \
 289                                  FTSMC020_TPR_ATI(0xf) |        \
 290                                  FTSMC020_TPR_AT2(3)   |        \
 291                                  FTSMC020_TPR_WTC(3)   |        \
 292                                  FTSMC020_TPR_AHT(3)   |        \
 293                                  FTSMC020_TPR_TRNA(0xf))
 294
 295 #define FTSMC020_BANK1_CONFIG   (0x00)
 296 #define FTSMC020_BANK1_TIMING   (0x00)
 297 #endif /* CONFIG_FTSMC020 */
 298
 299 /*
 300  * FLASH and environment organization
 301  */
 302 /* use CFI framework */
 303 #define CONFIG_SYS_FLASH_CFI
 304 #define CONFIG_FLASH_CFI_DRIVER
 305
 306 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 307 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 308 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 309
 310 /* support JEDEC */
 311
 312 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 313 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 314 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 315 #else
 316 #ifdef CONFIG_MEM_REMAP
 317 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 318 #else
 319 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 320 #endif
 321 #endif  /* CONFIG_MEM_REMAP */
 322
 323 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 324 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 325 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 326
 327 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 328 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 329
 330 /* max number of memory banks */
 331 /*
 332  * There are 4 banks supported for this Controller,
 333  * but we have only 1 bank connected to flash on board
 334  */
 335 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 336 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 337 #endif
 338 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 339
 340 /* max number of sectors on one chip */
 341 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 342 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
 343 #define CONFIG_SYS_MAX_FLASH_SECT       512
 344
 345 /* environments */
 346 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x140000)
 347 #define CONFIG_ENV_SIZE                 8192
 348 #define CONFIG_ENV_OVERWRITE
 349
 350 /*
 351  * For booting Linux, the board info and command line data
 352  * have to be in the first 16 MB of memory, since this is
 353  * the maximum mapped by the Linux kernel during initialization.
 354  */
 355
 356 /* Initial Memory map for Linux*/
 357 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 358 /* Increase max gunzip size */
 359 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 360
 361 #endif  /* __CONFIG_H */