2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <asm/arch/ag101.h>
30 * CPU and Board Configuration Options
32 #define CONFIG_ADP_AG101
34 #define CONFIG_USE_INTERRUPT
36 #define CONFIG_SKIP_LOWLEVEL_INIT
38 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
39 #define CONFIG_MEM_REMAP
42 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
43 #define CONFIG_SYS_TEXT_BASE 0x03200000
45 #define CONFIG_SYS_TEXT_BASE 0x00000000
53 * According to the discussion in u-boot mailing list before,
54 * CONFIG_SYS_HZ at 1000 is mandatory.
56 #define CONFIG_SYS_HZ 1000
57 #define CONFIG_SYS_CLK_FREQ 48000000
58 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
61 * Use Externel CLOCK or PCLK
63 #undef CONFIG_FTRTC010_EXTCLK
65 #ifndef CONFIG_FTRTC010_EXTCLK
66 #define CONFIG_FTRTC010_PCLK
69 #ifdef CONFIG_FTRTC010_EXTCLK
70 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
72 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
75 #define TIMER_LOAD_VAL 0xffffffff
80 #define CONFIG_RTC_FTRTC010
83 * Real Time Clock Divider
84 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
86 #define OSC_5MHZ (5*1000000)
87 #define OSC_CLK (2*OSC_5MHZ)
88 #define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
91 * Serial console configuration
94 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
95 #define CONFIG_BAUDRATE 38400
96 #define CONFIG_CONS_INDEX 1
97 #define CONFIG_SYS_NS16550
98 #define CONFIG_SYS_NS16550_SERIAL
99 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
100 #define CONFIG_SYS_NS16550_REG_SIZE -4
101 #define CONFIG_SYS_NS16550_CLK ((46080000 * 20) / 25) /* AG101 */
106 #define CONFIG_FTMAC100
108 #define CONFIG_BOOTDELAY 3
111 * SD (MMC) controller
114 #define CONFIG_CMD_MMC
115 #define CONFIG_GENERIC_MMC
116 #define CONFIG_DOS_PARTITION
117 #define CONFIG_FTSDC010
118 #define CONFIG_FTSDC010_NUMBER 1
119 #define CONFIG_FTSDC010_SDIO
120 #define CONFIG_CMD_FAT
121 #define CONFIG_CMD_EXT2
124 * Command line configuration.
126 #include <config_cmd_default.h>
128 #define CONFIG_CMD_CACHE
129 #define CONFIG_CMD_DATE
130 #define CONFIG_CMD_PING
133 * Miscellaneous configurable options
135 #define CONFIG_SYS_LONGHELP /* undef to save memory */
136 #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
137 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
139 /* Print Buffer Size */
140 #define CONFIG_SYS_PBSIZE \
141 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
143 /* max number of command args */
144 #define CONFIG_SYS_MAXARGS 16
146 /* Boot Argument Buffer Size */
147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
150 * Size of malloc() pool
152 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
153 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
156 * size in bytes reserved for initial data
158 #define CONFIG_SYS_GBL_DATA_SIZE 128
161 * AHB Controller configuration
163 #define CONFIG_FTAHBC020S
165 #ifdef CONFIG_FTAHBC020S
166 #include <faraday/ftahbc020s.h>
168 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
169 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
172 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
173 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
176 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
177 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
178 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
184 #define CONFIG_FTWDT010_WATCHDOG
187 * PMU Power controller configuration
190 #define CONFIG_FTPMU010_POWER
192 #ifdef CONFIG_FTPMU010_POWER
193 #include <faraday/ftpmu010.h>
194 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
195 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
196 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
197 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
198 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
199 FTPMU010_SDRAMHTC_CKE_DCSR | \
200 FTPMU010_SDRAMHTC_DQM_DCSR | \
201 FTPMU010_SDRAMHTC_SDCLK_DCSR)
205 * SDRAM controller configuration
207 #define CONFIG_FTSDMC021
209 #ifdef CONFIG_FTSDMC021
210 #include <faraday/ftsdmc021.h>
212 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRP(1) | \
213 FTSDMC021_TP1_TRCD(1) | \
214 FTSDMC021_TP1_TRF(3) | \
215 FTSDMC021_TP1_TWR(1) | \
216 FTSDMC021_TP1_TCL(2))
218 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
219 FTSDMC021_TP2_INI_REFT(8) | \
220 FTSDMC021_TP2_REF_INTV(0x180))
223 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
224 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
227 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
228 FTSDMC021_CR1_DSZ(3) | \
229 FTSDMC021_CR1_MBW(2) | \
230 FTSDMC021_CR1_BNKSIZE(6))
232 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
233 FTSDMC021_CR2_IREF | \
236 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
237 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
238 CONFIG_SYS_FTSDMC021_BANK0_BASE)
240 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
241 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
242 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
243 CONFIG_SYS_FTSDMC021_BANK1_BASE)
248 * Physical Memory Map
250 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
251 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
252 #if defined(CONFIG_MEM_REMAP)
253 #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
255 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
256 #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
258 #define PHYS_SDRAM_1 \
259 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
261 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
262 #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
263 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
265 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
267 #ifdef CONFIG_MEM_REMAP
268 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
269 GENERATED_GBL_DATA_SIZE)
271 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
272 GENERATED_GBL_DATA_SIZE)
273 #endif /* CONFIG_MEM_REMAP */
276 * Load address and memory test area should agree with
277 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
279 #define CONFIG_SYS_LOAD_ADDR 0x300000
281 /* memtest works on 63 MB in DRAM */
282 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
283 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
286 * Static memory controller configuration
288 #define CONFIG_FTSMC020
290 #ifdef CONFIG_FTSMC020
291 #include <faraday/ftsmc020.h>
293 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
294 #define CONFIG_SYS_FTSMC020_CONFIGS { \
295 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
296 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
299 #define CONFIG_SYS_FTSMC020_CONFIGS { \
300 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
305 * There are 2 bank connected to FTSMC020 on ADP-AG101.
306 * You can use jumper and switch to force it booted from ROM or FLASH.
307 * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
308 * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
310 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
311 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
312 FTSMC020_BANK_SIZE_32M | \
313 FTSMC020_BANK_MBW_32)
315 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
316 FTSMC020_TPR_AST(1) | \
317 FTSMC020_TPR_CTW(1) | \
318 FTSMC020_TPR_ATI(1) | \
319 FTSMC020_TPR_AT2(1) | \
320 FTSMC020_TPR_WTC(1) | \
321 FTSMC020_TPR_AHT(1) | \
322 FTSMC020_TPR_TRNA(1))
326 * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
327 * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
328 * Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
329 * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
331 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_SIZE_32M | \
332 FTSMC020_BANK_MBW_32)
334 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
335 FTSMC020_TPR_AST(3) | \
336 FTSMC020_TPR_CTW(3) | \
337 FTSMC020_TPR_ATI(0xf) | \
338 FTSMC020_TPR_AT2(3) | \
339 FTSMC020_TPR_WTC(3) | \
340 FTSMC020_TPR_AHT(3) | \
341 FTSMC020_TPR_TRNA(0xf))
343 #define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
344 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
345 FTSMC020_BANK_SIZE_32M | \
346 FTSMC020_BANK_MBW_32)
348 #define FTSMC020_BANK1_TIMING (FTSMC020_TPR_RBE | \
349 FTSMC020_TPR_AST(1) | \
350 FTSMC020_TPR_CTW(1) | \
351 FTSMC020_TPR_ATI(1) | \
352 FTSMC020_TPR_AT2(1) | \
353 FTSMC020_TPR_WTC(1) | \
354 FTSMC020_TPR_AHT(1) | \
355 FTSMC020_TPR_TRNA(1))
356 #endif /* CONFIG_FTSMC020 */
359 * FLASH and environment organization
361 /* use CFI framework */
362 #define CONFIG_SYS_FLASH_CFI
363 #define CONFIG_FLASH_CFI_DRIVER
365 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
366 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
370 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
371 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
372 #define PHYS_FLASH_1 0x80400000 /* BANK 1 */
373 #else /* !CONFIG_SKIP_LOWLEVEL_INIT */
374 #ifdef CONFIG_MEM_REMAP
375 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
377 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
378 #endif /* CONFIG_MEM_REMAP */
379 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
381 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
382 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
383 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
385 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
386 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
388 /* max number of memory banks */
390 * There are 4 banks supported for this Controller,
391 * but we have only 1 bank connected to flash on board
393 #define CONFIG_SYS_MAX_FLASH_BANKS 1
395 /* max number of sectors on one chip */
396 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
397 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
398 #define CONFIG_SYS_MAX_FLASH_SECT 128
401 #define CONFIG_ENV_IS_IN_FLASH
402 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
403 #define CONFIG_ENV_SIZE 8192
404 #define CONFIG_ENV_OVERWRITE
406 #endif /* __CONFIG_H */