2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-ag101/ag101.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_ADP_AG101
19 #define CONFIG_USE_INTERRUPT
21 #define CONFIG_SKIP_LOWLEVEL_INIT
24 * Definitions related to passing arguments to kernel.
26 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
27 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
28 #define CONFIG_INITRD_TAG /* send initrd params */
30 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
31 #define CONFIG_MEM_REMAP
34 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
35 #define CONFIG_SYS_TEXT_BASE 0x03200000
37 #define CONFIG_SYS_TEXT_BASE 0x00000000
43 #define CONFIG_SYS_CLK_FREQ 48000000
44 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
47 * Use Externel CLOCK or PCLK
49 #undef CONFIG_FTRTC010_EXTCLK
51 #ifndef CONFIG_FTRTC010_EXTCLK
52 #define CONFIG_FTRTC010_PCLK
55 #ifdef CONFIG_FTRTC010_EXTCLK
56 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
58 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
61 #define TIMER_LOAD_VAL 0xffffffff
66 #define CONFIG_RTC_FTRTC010
69 * Real Time Clock Divider
70 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
72 #define OSC_5MHZ (5*1000000)
73 #define OSC_CLK (2*OSC_5MHZ)
74 #define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
77 * Serial console configuration
80 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
81 #define CONFIG_BAUDRATE 38400
82 #define CONFIG_CONS_INDEX 1
83 #define CONFIG_SYS_NS16550
84 #define CONFIG_SYS_NS16550_SERIAL
85 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
86 #define CONFIG_SYS_NS16550_REG_SIZE -4
87 #define CONFIG_SYS_NS16550_CLK ((46080000 * 20) / 25) /* AG101 */
92 #define CONFIG_FTMAC100
94 #define CONFIG_BOOTDELAY 3
100 #define CONFIG_CMD_MMC
101 #define CONFIG_GENERIC_MMC
102 #define CONFIG_DOS_PARTITION
103 #define CONFIG_FTSDC010
104 #define CONFIG_FTSDC010_NUMBER 1
105 #define CONFIG_FTSDC010_SDIO
106 #define CONFIG_CMD_FAT
107 #define CONFIG_CMD_EXT2
110 * Command line configuration.
112 #define CONFIG_CMD_CACHE
113 #define CONFIG_CMD_DATE
114 #define CONFIG_CMD_PING
117 * Miscellaneous configurable options
119 #define CONFIG_SYS_LONGHELP /* undef to save memory */
120 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
122 /* Print Buffer Size */
123 #define CONFIG_SYS_PBSIZE \
124 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126 /* max number of command args */
127 #define CONFIG_SYS_MAXARGS 16
129 /* Boot Argument Buffer Size */
130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
133 * Size of malloc() pool
135 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
136 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
139 * AHB Controller configuration
141 #define CONFIG_FTAHBC020S
143 #ifdef CONFIG_FTAHBC020S
144 #include <faraday/ftahbc020s.h>
146 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
147 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
150 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
151 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
154 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
155 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
156 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
162 #define CONFIG_FTWDT010_WATCHDOG
165 * PMU Power controller configuration
168 #define CONFIG_FTPMU010_POWER
170 #ifdef CONFIG_FTPMU010_POWER
171 #include <faraday/ftpmu010.h>
172 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
173 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
174 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
175 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
176 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
177 FTPMU010_SDRAMHTC_CKE_DCSR | \
178 FTPMU010_SDRAMHTC_DQM_DCSR | \
179 FTPMU010_SDRAMHTC_SDCLK_DCSR)
183 * SDRAM controller configuration
185 #define CONFIG_FTSDMC021
187 #ifdef CONFIG_FTSDMC021
188 #include <faraday/ftsdmc021.h>
190 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRP(1) | \
191 FTSDMC021_TP1_TRCD(1) | \
192 FTSDMC021_TP1_TRF(3) | \
193 FTSDMC021_TP1_TWR(1) | \
194 FTSDMC021_TP1_TCL(2))
196 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
197 FTSDMC021_TP2_INI_REFT(8) | \
198 FTSDMC021_TP2_REF_INTV(0x180))
201 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
202 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
205 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
206 FTSDMC021_CR1_DSZ(3) | \
207 FTSDMC021_CR1_MBW(2) | \
208 FTSDMC021_CR1_BNKSIZE(6))
210 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
211 FTSDMC021_CR2_IREF | \
214 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
215 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
216 CONFIG_SYS_FTSDMC021_BANK0_BASE)
218 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
219 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
220 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
221 CONFIG_SYS_FTSDMC021_BANK1_BASE)
226 * Physical Memory Map
228 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
229 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
230 #if defined(CONFIG_MEM_REMAP)
231 #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
233 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
234 #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
236 #define PHYS_SDRAM_1 \
237 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
239 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
240 #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
241 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
243 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
245 #ifdef CONFIG_MEM_REMAP
246 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
247 GENERATED_GBL_DATA_SIZE)
249 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
250 GENERATED_GBL_DATA_SIZE)
251 #endif /* CONFIG_MEM_REMAP */
254 * Load address and memory test area should agree with
255 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
257 #define CONFIG_SYS_LOAD_ADDR 0x300000
259 /* memtest works on 63 MB in DRAM */
260 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
261 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
264 * Static memory controller configuration
266 #define CONFIG_FTSMC020
268 #ifdef CONFIG_FTSMC020
269 #include <faraday/ftsmc020.h>
271 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
272 #define CONFIG_SYS_FTSMC020_CONFIGS { \
273 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
274 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
277 #define CONFIG_SYS_FTSMC020_CONFIGS { \
278 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
283 * There are 2 bank connected to FTSMC020 on ADP-AG101.
284 * You can use jumper and switch to force it booted from ROM or FLASH.
285 * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
286 * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
288 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
289 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
290 FTSMC020_BANK_SIZE_32M | \
291 FTSMC020_BANK_MBW_32)
293 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
294 FTSMC020_TPR_AST(1) | \
295 FTSMC020_TPR_CTW(1) | \
296 FTSMC020_TPR_ATI(1) | \
297 FTSMC020_TPR_AT2(1) | \
298 FTSMC020_TPR_WTC(1) | \
299 FTSMC020_TPR_AHT(1) | \
300 FTSMC020_TPR_TRNA(1))
304 * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
305 * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
306 * Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
307 * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
309 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_SIZE_32M | \
310 FTSMC020_BANK_MBW_32)
312 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
313 FTSMC020_TPR_AST(3) | \
314 FTSMC020_TPR_CTW(3) | \
315 FTSMC020_TPR_ATI(0xf) | \
316 FTSMC020_TPR_AT2(3) | \
317 FTSMC020_TPR_WTC(3) | \
318 FTSMC020_TPR_AHT(3) | \
319 FTSMC020_TPR_TRNA(0xf))
321 #define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
322 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
323 FTSMC020_BANK_SIZE_32M | \
324 FTSMC020_BANK_MBW_32)
326 #define FTSMC020_BANK1_TIMING (FTSMC020_TPR_RBE | \
327 FTSMC020_TPR_AST(1) | \
328 FTSMC020_TPR_CTW(1) | \
329 FTSMC020_TPR_ATI(1) | \
330 FTSMC020_TPR_AT2(1) | \
331 FTSMC020_TPR_WTC(1) | \
332 FTSMC020_TPR_AHT(1) | \
333 FTSMC020_TPR_TRNA(1))
334 #endif /* CONFIG_FTSMC020 */
337 * FLASH and environment organization
339 /* use CFI framework */
340 #define CONFIG_SYS_FLASH_CFI
341 #define CONFIG_FLASH_CFI_DRIVER
343 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
344 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
348 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
349 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
350 #define PHYS_FLASH_1 0x80400000 /* BANK 1 */
351 #else /* !CONFIG_SKIP_LOWLEVEL_INIT */
352 #ifdef CONFIG_MEM_REMAP
353 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
355 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
356 #endif /* CONFIG_MEM_REMAP */
357 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
359 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
360 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
361 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
363 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
364 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
366 /* max number of memory banks */
368 * There are 4 banks supported for this Controller,
369 * but we have only 1 bank connected to flash on board
371 #define CONFIG_SYS_MAX_FLASH_BANKS 1
373 /* max number of sectors on one chip */
374 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
375 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
376 #define CONFIG_SYS_MAX_FLASH_SECT 128
379 #define CONFIG_ENV_IS_IN_FLASH
380 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
381 #define CONFIG_ENV_SIZE 8192
382 #define CONFIG_ENV_OVERWRITE
384 #endif /* __CONFIG_H */