2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
37 #define CONFIG_A4M072 1 /* ... on A4M072 board */
38 #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
40 #define CONFIG_MISC_INIT_R
42 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
44 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
45 #define BOOTFLAG_WARM 0x02 /* Software reboot */
47 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
50 * Serial console configuration
52 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
53 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
54 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
55 /* define to enable silent console */
56 #define CONFIG_SILENT_CONSOLE
57 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
61 * 0x40000000 - 0x4fffffff - PCI Memory
62 * 0x50000000 - 0x50ffffff - PCI IO Space
66 #if defined(CONFIG_PCI)
67 #define CONFIG_PCI_PNP 1
68 #define CONFIG_PCI_SCAN_SHOW 1
69 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
71 #define CONFIG_PCI_MEM_BUS 0x40000000
72 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
73 #define CONFIG_PCI_MEM_SIZE 0x10000000
75 #define CONFIG_PCI_IO_BUS 0x50000000
76 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
77 #define CONFIG_PCI_IO_SIZE 0x01000000
80 #define CONFIG_SYS_XLB_PIPELINING 1
82 #undef CONFIG_NET_MULTI
83 #undef CONFIG_EEPRO100
86 #define CONFIG_MAC_PARTITION
87 #define CONFIG_DOS_PARTITION
90 #define CONFIG_USB_OHCI_NEW
91 #define CONFIG_USB_STORAGE
92 #define CONFIG_SYS_OHCI_BE_CONTROLLER
93 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
94 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
95 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
96 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
97 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
99 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
104 #define CONFIG_BOOTP_BOOTFILESIZE
105 #define CONFIG_BOOTP_BOOTPATH
106 #define CONFIG_BOOTP_GATEWAY
107 #define CONFIG_BOOTP_HOSTNAME
111 * Command line configuration.
113 #include <config_cmd_default.h>
115 #define CONFIG_CMD_EEPROM
116 #define CONFIG_CMD_FAT
117 #define CONFIG_CMD_I2C
118 #define CONFIG_CMD_IDE
119 #define CONFIG_CMD_NFS
120 #define CONFIG_CMD_SNTP
121 #define CONFIG_CMD_USB
122 #define CONFIG_CMD_MII
123 #define CONFIG_CMD_DHCP
124 #define CONFIG_CMD_PING
125 #define CONFIG_CMD_DISPLAY
127 #if defined(CONFIG_PCI)
128 #define CONFIG_CMD_PCI
131 #if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
132 #define CONFIG_SYS_LOWBOOT 1
133 #define CONFIG_SYS_LOWBOOT32 1
139 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
141 #define CONFIG_SYS_AUTOLOAD "n"
143 #define CONFIG_AUTOBOOT_KEYED
144 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
145 #define CONFIG_AUTOBOOT_DELAY_STR "asdfg"
147 #undef CONFIG_BOOTARGS
148 #define CONFIG_PREBOOT "run try_update"
150 #define CONFIG_EXTRA_ENV_SETTINGS \
151 "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
152 "cf1=diskboot 200000 0:1\0" \
153 "bootcmd_cf1=run bcf1\0" \
154 "bcf=setenv bootargs root=/dev/hda3\0" \
155 "bootcmd_nfs=run bnfs\0" \
156 "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0" \
157 "bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0" \
158 "bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0" \
159 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
160 "try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0" \
161 "env_addr=FE060000\0" \
162 "kernel_addr=FE100000\0" \
163 "rootfs_addr=FE200000\0" \
164 "add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
165 "bcf1=run cf1; run bcf; run addip; run bk\0" \
166 "add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0" \
167 "addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0" \
169 "ethaddr=00:00:00:00:00:00\0" \
171 "bootcmd=run bootcmd_nor\0" \
174 * IPB Bus clocking configuration.
176 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
181 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
182 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
184 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
185 #define CONFIG_SYS_I2C_SLAVE 0x7F
188 * EEPROM configuration
190 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */
191 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
192 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
193 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
194 #define CONFIG_SYS_EEPROM_WREN 1
195 #define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4
198 * Flash configuration
200 #define CONFIG_SYS_FLASH_BASE 0xFE000000
201 #define CONFIG_SYS_FLASH_SIZE 0x02000000
202 #if !defined(CONFIG_SYS_LOWBOOT)
203 #error "CONFIG_SYS_LOWBOOT not defined?"
204 #else /* CONFIG_SYS_LOWBOOT */
205 #if defined(CONFIG_SYS_LOWBOOT32)
206 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
208 #endif /* CONFIG_SYS_LOWBOOT */
210 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
211 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
212 #define CONFIG_FLASH_CFI_DRIVER
213 #define CONFIG_SYS_FLASH_CFI
214 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
215 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
218 * Environment settings
220 #define CONFIG_ENV_IS_IN_FLASH 1
221 #define CONFIG_ENV_SIZE 0x10000
222 #define CONFIG_ENV_SECT_SIZE 0x20000
223 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
224 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
226 #define CONFIG_ENV_OVERWRITE 1
231 #define CONFIG_SYS_MBAR 0xF0000000
232 #define CONFIG_SYS_SDRAM_BASE 0x00000000
233 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
235 /* Use SRAM until RAM will be available */
236 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
237 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
240 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
241 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
242 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
244 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
245 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
246 # define CONFIG_SYS_RAMBOOT 1
249 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
250 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
251 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
254 * Ethernet configuration
256 #define CONFIG_MPC5xxx_FEC 1
257 #define CONFIG_MPC5xxx_FEC_MII100
259 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
261 /* #define CONFIG_MPC5xxx_FEC_MII10 */
262 #define CONFIG_PHY_ADDR 0x1f
263 #define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */
268 #define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004
271 * Miscellaneous configurable options
273 #define CONFIG_SYS_HUSH_PARSER
274 #define CONFIG_CMDLINE_EDITING 1
275 #ifdef CONFIG_SYS_HUSH_PARSER
276 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
278 #define CONFIG_SYS_LONGHELP /* undef to save memory */
279 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
280 #if defined(CONFIG_CMD_KGDB)
281 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
283 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
285 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
286 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
287 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
289 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
290 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
292 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
294 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
296 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
297 #if defined(CONFIG_CMD_KGDB)
298 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
303 * Various low-level settings
305 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
306 #define CONFIG_SYS_HID0_FINAL HID0_ICE
307 /* Flash at CSBoot, CS0 */
308 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
309 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
310 #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
311 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
312 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
313 /* External SRAM at CS1 */
314 #define CONFIG_SYS_CS1_START 0x62000000
315 #define CONFIG_SYS_CS1_SIZE 0x00400000
316 #define CONFIG_SYS_CS1_CFG 0x00009930
317 #define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START
318 #define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
319 /* LED display at CS7 */
320 #define CONFIG_SYS_CS7_START 0x6a000000
321 #define CONFIG_SYS_CS7_SIZE (64*1024)
322 #define CONFIG_SYS_CS7_CFG 0x0000bf30
324 #define CONFIG_SYS_CS_BURST 0x00000000
325 #define CONFIG_SYS_CS_DEADCYCLE 0x33333003
327 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
329 /*-----------------------------------------------------------------------
331 *-----------------------------------------------------------------------
333 #define CONFIG_USB_CLOCK 0x0001BBBB
334 #define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */
336 /*-----------------------------------------------------------------------
337 * IDE/ATA stuff Supports IDE harddisk
338 *-----------------------------------------------------------------------
341 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
343 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
344 #undef CONFIG_IDE_LED /* LED for ide not supported */
346 #define CONFIG_IDE_PREINIT
348 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
349 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
351 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
353 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
355 /* Offset for data I/O */
356 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
358 /* Offset for normal register accesses */
359 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
361 /* Offset for alternate registers */
362 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
364 /* Interval between registers */
365 #define CONFIG_SYS_ATA_STRIDE 4
367 #define CONFIG_ATAPI 1
369 /*-----------------------------------------------------------------------
370 * Open firmware flat tree support
371 *-----------------------------------------------------------------------
373 #define CONFIG_OF_LIBFDT 1
374 #define CONFIG_OF_BOARD_SETUP 1
376 #define OF_CPU "PowerPC,5200@0"
377 #define OF_SOC "soc5200@f0000000"
378 #define OF_TBCLK (bd->bi_busfreq / 4)
379 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
381 /* Support for the 7-segment display */
382 #define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START
383 #define CONFIG_SHOW_ACTIVITY /* used for display realization */
385 #endif /* __CONFIG_H */