2 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 * High Level Configuration Options
15 #define CONFIG_MPC5200
16 #define CONFIG_A3M071 /* A3M071 board */
17 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_SYS_GENERIC_BOARD
20 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
22 #define CONFIG_SPL_TARGET "u-boot-img.bin"
24 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
26 #define CONFIG_MISC_INIT_R
27 #define CONFIG_SYS_LOWBOOT /* Enable lowboot */
30 #define CONFIG_HOSTNAME a4m2k
32 #define CONFIG_HOSTNAME a3m071
35 #define CONFIG_BOOTCOUNT_LIMIT
38 * Serial console configuration
40 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
41 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
42 #define CONFIG_SYS_BAUDRATE_TABLE \
43 { 9600, 19200, 38400, 57600, 115200, 230400 }
46 * Command line configuration.
48 #include <config_cmd_default.h>
50 #define CONFIG_CMD_BSP
51 #define CONFIG_CMD_CACHE
52 #define CONFIG_CMD_MII
53 #define CONFIG_CMD_REGINFO
54 #define CONFIG_CMD_DHCP
55 #define CONFIG_BOOTP_SEND_HOSTNAME
56 #define CONFIG_BOOTP_SERVERIP
57 #define CONFIG_BOOTP_MAY_FAIL
58 #define CONFIG_BOOTP_BOOTPATH
59 #define CONFIG_BOOTP_GATEWAY
60 #define CONFIG_BOOTP_SERVERIP
61 #define CONFIG_NET_RETRY_COUNT 3
62 #define CONFIG_CMD_LINK_LOCAL
63 #define CONFIG_NETCONSOLE
64 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
65 #define CONFIG_CMD_PING
66 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
67 #define CONFIG_MTD_PARTITIONS /* needed for UBI */
68 #define CONFIG_FLASH_CFI_MTD
69 #define MTDIDS_DEFAULT "nor0=fc000000.flash"
70 #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
83 #define CONFIG_LZO /* needed for UBI */
84 #define CONFIG_RBTREE /* needed for UBI */
85 #define CONFIG_CMD_MTDPARTS
86 #define CONFIG_CMD_UBI
87 #define CONFIG_CMD_UBIFS
91 * IPB Bus clocking configuration.
93 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
94 /* define for 66MHz speed - undef for 33MHz PCI clock speed */
96 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
98 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
101 /* pass open firmware flat tree */
102 #define CONFIG_OF_LIBFDT
103 #define CONFIG_OF_BOARD_SETUP
105 /* maximum size of the flat tree (8K) */
106 #define OF_FLAT_TREE_MAX_SIZE 8192
108 #define OF_CPU "PowerPC,5200@0"
109 #define OF_SOC "soc5200@f0000000"
110 #define OF_TBCLK (bd->bi_busfreq / 4)
111 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
114 * NOR flash configuration
116 #define CONFIG_SYS_FLASH_BASE 0xfc000000
117 #define CONFIG_SYS_FLASH_SIZE 0x02000000
118 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
120 #define CONFIG_SYS_MAX_FLASH_BANKS 1
121 #define CONFIG_SYS_MAX_FLASH_SECT 256
122 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
123 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
124 #define CONFIG_SYS_FLASH_LOCK_TOUT 5
125 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
126 #define CONFIG_SYS_FLASH_PROTECTION
127 #define CONFIG_FLASH_CFI_DRIVER
128 #define CONFIG_SYS_FLASH_CFI
129 #define CONFIG_SYS_FLASH_EMPTY_INFO
130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
131 #define CONFIG_FLASH_VERIFY
134 * Environment settings
136 #define CONFIG_ENV_IS_IN_FLASH
137 #define CONFIG_ENV_SIZE 0x10000
138 #define CONFIG_ENV_SECT_SIZE 0x20000
139 #define CONFIG_ENV_OVERWRITE
140 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
141 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
146 #define CONFIG_SYS_MBAR 0xf0000000
147 #define CONFIG_SYS_SDRAM_BASE 0x00000000
148 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
150 /* Use SRAM until RAM will be available */
151 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
152 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
154 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
155 GENERATED_GBL_DATA_SIZE)
156 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
158 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
160 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
161 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
162 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
165 * Ethernet configuration
167 #define CONFIG_MPC5xxx_FEC
168 #define CONFIG_MPC5xxx_FEC_MII100
170 #define CONFIG_PHY_ADDR 0x01
172 #define CONFIG_PHY_ADDR 0x00
180 * GPIO-config depends on failsave-level
181 * failsave 0 means just MPX-config, no digiboard, no fpga
182 * 1 means digiboard ok
187 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
189 /* for failsave-level 0 - full failsave */
190 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
191 /* for failsave-level 1 - only digiboard ok */
192 #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
193 /* for failsave-level 2 - all ok */
194 #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
197 #define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
198 #if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
199 #define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
203 * Configuration matrix
205 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
206 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
207 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
208 * || ||| || | ||| | | | |
209 * || ||| || | ||| | | | | bit rev name
210 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
211 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
212 * ||| || | ||| | | | | 2 29 ALTs
213 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
214 * ++-++--+---+++-+---+---+---+- 4 27 CS7
215 * +-++--+---+++-+---+---+---+- 5 26 CS6
216 * || | ||| | | | | 6 25 ATA
217 * ++--+---+++-+---+---+---+- 7 24 ATA
218 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
219 * | ||| | | | | 9 22 IRDA
220 * | ||| | | | | 10 21 IRDA
221 * +---+++-+---+---+---+- 11 20 IRDA
222 * ||| | | | | 12 19 Ether
223 * ||| | | | | 13 18 Ether
224 * ||| | | | | 14 17 Ether
225 * +++-+---+---+---+- 15 16 Ether
226 * ++-+---+---+---+- 16 15 PCI_DIS
227 * +-+---+---+---+- 17 14 USB_SE
229 * +---+---+---+- 19 12 USB
233 * +---+---+- 23 8 PSC3
246 * Miscellaneous configurable options
248 #define CONFIG_SYS_LONGHELP
250 #define CONFIG_CMDLINE_EDITING
251 #define CONFIG_SYS_HUSH_PARSER
252 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
254 #if defined(CONFIG_CMD_KGDB)
255 #define CONFIG_SYS_CBSIZE 1024
257 #define CONFIG_SYS_CBSIZE 256
259 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
260 #define CONFIG_SYS_MAXARGS 16
261 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
263 #define CONFIG_SYS_MEMTEST_START 0x00100000
264 #define CONFIG_SYS_MEMTEST_END 0x00f00000
266 #define CONFIG_SYS_LOAD_ADDR 0x00100000
269 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
272 * Various low-level settings
274 #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
275 #define CONFIG_SYS_HID0_FINAL HID0_ICE
277 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
278 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
279 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
280 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
284 #define CONFIG_SYS_CS1_START 0xf1000000
285 #define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
288 #define CONFIG_SYS_CS2_START 0xe0000000
289 #define CONFIG_SYS_CS2_SIZE 0x00100000
291 /* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
292 #define CONFIG_SYS_CS3_START 0xE9000000
294 #define CONFIG_SYS_CS3_SIZE 0x00100000
296 #define CONFIG_SYS_CS3_SIZE 0x00080000
298 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
299 #define CONFIG_SYS_CS3_CFG 0x0032B900
302 /* Diagnosis Interface - see ticket #63 */
303 #define CONFIG_SYS_CS4_START 0xEA000000
304 #define CONFIG_SYS_CS4_SIZE 0x00000001
305 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
306 #define CONFIG_SYS_CS4_CFG 0x0002B900
309 /* FPGA master io (64kiB / 1MiB) - see ticket #66 */
310 #define CONFIG_SYS_CS5_START 0xE8000000
312 #define CONFIG_SYS_CS5_SIZE 0x00100000
314 #define CONFIG_SYS_CS5_SIZE 0x00010000
316 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
317 #define CONFIG_SYS_CS5_CFG 0x0032B900
319 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
320 #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
321 #define CONFIG_SYS_CS1_CFG 0x0008FD00
322 #define CONFIG_SYS_CS2_CFG 0x0006F90C
323 #else /* for pci_clk = 33 MHz */
324 #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
325 #define CONFIG_SYS_CS1_CFG 0x0001FB00
326 #define CONFIG_SYS_CS2_CFG 0x0002F90C
329 #define CONFIG_SYS_CS_BURST 0x00000000
330 /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
331 /* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
332 /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
333 #define CONFIG_SYS_CS_DEADCYCLE 0x33030000
335 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
338 * Environment Configuration
341 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
342 #undef CONFIG_BOOTARGS
343 #define CONFIG_ZERO_BOOTDELAY_CHECK
345 #define CONFIG_SYS_AUTOLOAD "n"
347 #define CONFIG_PREBOOT "echo;" \
348 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
349 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
352 #undef CONFIG_BOOTARGS
354 #define CONFIG_SYS_OS_BASE 0xfc200000
355 #define CONFIG_SYS_FDT_BASE 0xfc1e0000
357 #define CONFIG_EXTRA_ENV_SETTINGS \
360 "loadaddr=200000\0" \
361 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
362 "kernel_addr_r=1000000\0" \
363 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
364 "fdt_addr_r=1800000\0" \
365 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
366 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
367 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
368 "rootpath=/opt/eldk-5.2.1/powerpc/" \
369 "core-image-minimal-mtdutils-dropbear-generic\0" \
370 "consoledev=ttyPSC0\0" \
371 "nfsargs=setenv bootargs root=/dev/nfs rw " \
372 "nfsroot=${serverip}:${rootpath}\0" \
373 "ramargs=setenv bootargs root=/dev/ram rw\0" \
374 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
375 "rootfstype=squashfs,jffs2\0" \
376 "addhost=setenv bootargs ${bootargs} " \
377 "hostname=${hostname}\0" \
378 "addip=setenv bootargs ${bootargs} " \
379 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
380 ":${hostname}:${netdev}:off panic=1\0" \
381 "addtty=setenv bootargs ${bootargs} " \
382 "console=${consoledev},${baudrate}\0" \
383 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
384 "bootm ${kernel_addr} - ${fdt_addr}\0" \
385 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
386 "bootm ${kernel_addr} - ${fdt_addr}\0" \
387 "flash_self=run ramargs addip addtty addmtd addhost;" \
388 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
389 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
390 "tftp ${fdt_addr_r} ${fdtfile};" \
391 "run nfsargs addip addtty addmtd addhost;" \
392 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
393 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
394 "/u-boot-img.bin\0" \
395 "update=protect off fc000000 fc07ffff;" \
396 "era fc000000 fc07ffff;" \
397 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
398 "upd=run load;run update\0" \
399 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
400 "run mtdargs addip addtty addmtd addhost;" \
401 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
402 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
403 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
404 "erase fc200000 fc6fffff;" \
405 "cp.b 1000000 fc200000 ${filesize}" \
406 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
407 "mtdids=" MTDIDS_DEFAULT "\0" \
408 "mtdparts=" MTDPARTS_DEFAULT "\0" \
411 #define CONFIG_BOOTCOMMAND "run flash_mtd"
414 * SPL related defines
416 #define CONFIG_SPL_FRAMEWORK
417 #define CONFIG_SPL_BOARD_INIT
418 #define CONFIG_SPL_NOR_SUPPORT
419 #define CONFIG_SPL_TEXT_BASE 0xfc000000
420 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
421 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
422 #define CONFIG_SPL_SERIAL_SUPPORT
424 /* Place BSS for SPL near end of SDRAM */
425 #define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
426 #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
428 #define CONFIG_SPL_OS_BOOT
429 #define CONFIG_SPL_ENV_SUPPORT
430 /* Place patched DT blob (fdt) at this address */
431 #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
433 /* Settings for real U-Boot to be loaded from NOR flash */
435 extern char __spl_flash_end[];
437 #define CONFIG_SYS_UBOOT_BASE __spl_flash_end
438 #define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
439 #define CONFIG_SYS_UBOOT_START 0x1000100
441 #endif /* __CONFIG_H */