2 * Copyright (C) 2003 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
6 * This port was developed and tested on Revision C board.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
31 #define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
32 #define CPU_ID_STR "MPC8265"
36 #undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */
38 /* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
39 #define CONFIG_ENV_OVERWRITE
42 * Select serial console configuration
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
49 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50 #undef CONFIG_CONS_NONE /* It's not on external UART */
51 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
54 * Select ethernet configuration
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
61 * must be defined elsewhere (as for the console), or CFG_CMD_NET must
62 * be removed from CONFIG_COMMANDS to remove support for networking.
64 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
65 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
66 #undef CONFIG_ETHER_NONE /* No external Ethernet */
68 #ifdef CONFIG_ETHER_ON_FCC
70 #define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
72 #if (CONFIG_ETHER_INDEX == 2)
76 * - Select bus for bd/buffers (see 28-13)
79 # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
80 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
81 # define CFG_CPMFCR_RAMTYPE 0
82 # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
84 #endif /* CONFIG_ETHER_INDEX */
86 #define CONFIG_MII /* MII PHY management */
87 #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
89 * GPIO pins used for bit-banged MII communications
91 #define MDIO_PORT 2 /* Port C */
92 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
93 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
94 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
96 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
97 else iop->pdat &= ~0x00400000
99 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
100 else iop->pdat &= ~0x00200000
102 #define MIIDELAY udelay(1)
104 #endif /* CONFIG_ETHER_ON_FCC */
106 #ifndef CONFIG_8260_CLKIN
107 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
110 #define CONFIG_BAUDRATE 9600
112 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
140 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
141 #include <cmd_confdefs.h>
143 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
144 #define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
145 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
147 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
148 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
149 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
150 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
151 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
152 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
155 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
156 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
159 * Miscellaneous configurable options
161 #define CFG_HUSH_PARSER
162 #define CFG_PROMPT_HUSH_PS2 "> "
163 #define CFG_LONGHELP /* undef to save memory */
164 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
165 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
166 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
168 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
170 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
171 #define CFG_MAXARGS 16 /* max number of command args */
172 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
174 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
175 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
177 #define CFG_LOAD_ADDR 0x100000 /* default load address */
179 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
181 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
183 #define CFG_FLASH_BASE 0xFFE00000
184 #define CFG_FLASH_CFI
185 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
186 #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
188 #define CFG_DEFAULT_IMMR 0x0F010000
190 #define CFG_IMMR 0xF0000000
191 #define CFG_SDRAM_BASE 0x00000000
192 #define CFG_SDRAM_SIZE 64
193 #define CFG_FLSIMM_BASE 0xFC000000
194 #define CFG_LSDRAM_BASE 0xFE000000
195 #define CFG_BCSR 0xFEA00000
196 #define CFG_EEPROM 0xFEB00000
198 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
200 #define BCSR_PCI_MODE 0x01
202 #define CFG_INIT_RAM_ADDR CFG_IMMR
203 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
204 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
205 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
206 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
208 /* Hard reset configuration word */
209 #define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 |\
210 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
215 #define CFG_HRCW_SLAVE1 0
216 #define CFG_HRCW_SLAVE2 0
217 #define CFG_HRCW_SLAVE3 0
218 #define CFG_HRCW_SLAVE4 0
219 #define CFG_HRCW_SLAVE5 0
220 #define CFG_HRCW_SLAVE6 0
221 #define CFG_HRCW_SLAVE7 0
223 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
224 #define BOOTFLAG_WARM 0x02 /* Software reboot */
226 #define CFG_MONITOR_BASE TEXT_BASE
227 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
231 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
232 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
233 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
235 #if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM)
236 #define CFG_ENV_IS_IN_NVRAM 1
239 #ifdef CFG_ENV_IS_IN_FLASH
240 # define CFG_ENV_SECT_SIZE 0x10000
241 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
243 # define CFG_ENV_ADDR (CFG_EEPROM + 0x400)
244 # define CFG_ENV_SIZE 0x200
245 # define CFG_NVRAM_ACCESS_ROUTINE
248 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
249 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
250 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
253 #define CFG_HID0_INIT 0
254 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
258 #define CFG_SIUMCR 0x42200000
259 #define CFG_SYPCR 0xFFFFFFC3
260 #define CFG_BCR 0x90400000
261 #define CFG_SCCR SCCR_DFBRG01
263 #define CFG_RMR RMR_CSRE
264 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
265 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
268 #define CFG_PSDMR 0x014EB45A
269 #define CFG_PSRT 0x0C
270 #define CFG_LSDMR 0x008AB552
271 #define CFG_LSRT 0x0E
272 #define CFG_MPTPR 0x4000
274 #define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801
275 #define CFG_OR0_PRELIM 0xFFE00856
276 #define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801
277 #define CFG_OR5_PRELIM 0xFFFF03F6
278 #define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801
279 #define CFG_OR6_PRELIM 0xFE000856
280 #define CFG_BR7_PRELIM CFG_BCSR | 0x00000801
281 #define CFG_OR7_PRELIM 0xFFFF83F6
283 #define CFG_RESET_ADDRESS 0xC0000000
285 #endif /* __CONFIG_H */