2 * Copyright (C) 2003-2005 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
6 * This port was developed and tested on Revision C board.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
31 #define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
32 #define CPU_ID_STR "MPC8265"
33 #define CONFIG_CPM2 1 /* Has a CPM2 */
35 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
36 #define CONFIG_ENV_OVERWRITE
39 * Select serial console configuration
41 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
42 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
45 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
46 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
47 #undef CONFIG_CONS_NONE /* It's not on external UART */
48 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
51 * Select ethernet configuration
53 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
54 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
57 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
58 * must be defined elsewhere (as for the console), or CFG_CMD_NET must
59 * be removed from CONFIG_COMMANDS to remove support for networking.
61 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
62 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
63 #undef CONFIG_ETHER_NONE /* No external Ethernet */
65 #ifdef CONFIG_ETHER_ON_FCC
67 #define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
69 #if (CONFIG_ETHER_INDEX == 2)
73 * - Select bus for bd/buffers (see 28-13)
76 # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
77 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
78 # define CFG_CPMFCR_RAMTYPE 0
79 # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
81 #endif /* CONFIG_ETHER_INDEX */
83 #define CONFIG_MII /* MII PHY management */
84 #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
86 * GPIO pins used for bit-banged MII communications
88 #define MDIO_PORT 2 /* Port C */
89 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
90 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
91 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
93 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
94 else iop->pdat &= ~0x00400000
96 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
97 else iop->pdat &= ~0x00200000
99 #define MIIDELAY udelay(1)
101 #endif /* CONFIG_ETHER_ON_FCC */
103 #ifndef CONFIG_8260_CLKIN
104 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
107 #define CONFIG_BAUDRATE 38400
109 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
117 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
118 #include <cmd_confdefs.h>
120 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
121 #define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
122 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
124 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
125 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
126 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
127 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
128 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
129 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
132 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
133 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
136 * Miscellaneous configurable options
138 #define CFG_HUSH_PARSER
139 #define CFG_PROMPT_HUSH_PS2 "> "
140 #define CFG_LONGHELP /* undef to save memory */
141 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
142 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
143 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
145 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
147 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
148 #define CFG_MAXARGS 16 /* max number of command args */
149 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
151 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
152 #define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
154 #define CFG_LOAD_ADDR 0x400000 /* default load address */
156 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
158 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
160 #define CFG_SDRAM_BASE 0x00000000
161 #define CFG_SDRAM_SIZE 64
163 #define CFG_IMMR 0xF0000000
164 #define CFG_LSDRAM_BASE 0xFC000000
165 #define CFG_FLASH_BASE 0xFE000000
166 #define CFG_BCSR 0xFEA00000
167 #define CFG_EEPROM 0xFEB00000
168 #define CFG_FLSIMM_BASE 0xFF000000
170 #define CFG_FLASH_CFI
171 #define CFG_FLASH_CFI_DRIVER
172 #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
173 #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
175 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE }
177 #define BCSR_PCI_MODE 0x01
179 #define CFG_INIT_RAM_ADDR CFG_IMMR
180 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
181 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
182 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
183 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
185 /* Hard reset configuration word */
186 #define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
187 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
188 HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
192 #define CFG_HRCW_SLAVE1 0
193 #define CFG_HRCW_SLAVE2 0
194 #define CFG_HRCW_SLAVE3 0
195 #define CFG_HRCW_SLAVE4 0
196 #define CFG_HRCW_SLAVE5 0
197 #define CFG_HRCW_SLAVE6 0
198 #define CFG_HRCW_SLAVE7 0
200 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
201 #define BOOTFLAG_WARM 0x02 /* Software reboot */
203 #define CFG_MONITOR_BASE TEXT_BASE
204 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
208 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
209 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
210 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
212 #if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM)
213 #define CFG_ENV_IS_IN_NVRAM 1
216 #ifdef CFG_ENV_IS_IN_FLASH
217 # define CFG_ENV_SECT_SIZE 0x10000
218 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
220 # define CFG_ENV_ADDR (CFG_EEPROM + 0x400)
221 # define CFG_ENV_SIZE 0x1000
222 # define CFG_NVRAM_ACCESS_ROUTINE
225 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
226 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
227 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
230 #define CFG_HID0_INIT (HID0_ICFI)
231 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
235 #define CFG_SIUMCR 0x42200000
236 #define CFG_SYPCR 0xFFFFFFC3
237 #define CFG_BCR 0x90000000
238 #define CFG_SCCR SCCR_DFBRG01
240 #define CFG_RMR RMR_CSRE
241 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
242 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
245 #define CFG_PSDMR /* 0x834DA43B */0x014DA43A
246 #define CFG_PSRT 0x0F/* 0x0C */
247 #define CFG_LSDMR 0x0085A562
248 #define CFG_LSRT 0x0F
249 #define CFG_MPTPR 0x4000
251 #define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041
252 #define CFG_PSDRAM_OR 0xFC0028C0
253 #define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861
254 #define CFG_LSDRAM_OR 0xFF803480
256 #define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801
257 #define CFG_OR0_PRELIM 0xFFE00856
258 #define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801
259 #define CFG_OR5_PRELIM 0xFFFF03F6
260 #define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801
261 #define CFG_OR6_PRELIM 0xFF000856
262 #define CFG_BR7_PRELIM CFG_BCSR | 0x00000801
263 #define CFG_OR7_PRELIM 0xFFFF83F6
265 #define CFG_RESET_ADDRESS 0xC0000000
267 #endif /* __CONFIG_H */