2 * (C) Copyright 2002, 2003
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <gj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
8 * Configuation settings for the MPL VCMA9 board.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * If we are developing, we might want to start armboot from ram
34 * so we MUST NOT initialize critical regs like mem-timing ...
36 #define CONFIG_INIT_CRITICAL /* undef for developing */
39 * High Level Configuration Options
42 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
43 #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
44 #define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
46 /* input clock of PLL */
47 #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
49 #define USE_920T_MMU 1
50 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
52 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
53 #define CONFIG_SETUP_MEMORY_TAGS 1
54 #define CONFIG_INITRD_TAG 1
56 /***********************************************************
58 ***********************************************************/
59 #define CONFIG_COMMANDS \
72 /* this must be included after the definiton of CONFIG_COMMANDS */
73 #include <cmd_confdefs.h>
75 #define CFG_HUSH_PARSER
76 #define CFG_PROMPT_HUSH_PS2 "> "
77 /***********************************************************
79 * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
80 * address 0x50 with 16bit addressing
81 ***********************************************************/
82 #define CONFIG_HARD_I2C /* I2C with hardware support */
83 #define CFG_I2C_SPEED 100000 /* I2C speed */
84 #define CFG_I2C_SLAVE 0x7F /* I2C slave addr */
86 #define CFG_I2C_EEPROM_ADDR 0x50
87 #define CFG_I2C_EEPROM_ADDR_LEN 2
88 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
89 #define CFG_ENV_OFFSET 0x000 /* environment starts at offset 0 */
90 #define CFG_ENV_SIZE 0x800 /* 2KB should be more than enough */
92 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
93 #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */
94 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
97 * Size of malloc() pool
99 #define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
101 #define CFG_MONITOR_LEN (256 * 1024)
102 #define CFG_MALLOC_LEN (128 * 1024)
107 #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
108 #define CS8900_BASE 0x20000300
109 #define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
111 #define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */
114 * select serial console configuration
116 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
118 /************************************************************
120 ************************************************************/
122 #define CONFIG_USB_OHCI
123 #define CONFIG_USB_KEYBOARD
124 #define CONFIG_USB_STORAGE
126 /* Enable needed helper functions */
127 #define CFG_DEVICE_DEREGISTER /* needs device_deregister */
130 /************************************************************
132 ************************************************************/
133 #define CONFIG_RTC_S3C24X0 1
136 /* allow to overwrite serial and ethaddr */
137 #define CONFIG_ENV_OVERWRITE
139 #define CONFIG_BAUDRATE 9600
141 #define CONFIG_BOOTDELAY 3
142 #define CONFIG_NETMASK 255.255.255.0
143 #define CONFIG_IPADDR 10.0.0.110
144 #define CONFIG_SERVERIP 10.0.0.1
146 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
147 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
148 /* what's this ? it's not used anywhere */
149 #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
153 * Miscellaneous configurable options
155 #define CFG_LONGHELP /* undef to save memory */
156 #define CFG_PROMPT "VCMA9 # " /* Monitor Command Prompt */
157 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
158 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
159 #define CFG_MAXARGS 16 /* max number of command args */
160 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
162 #define CFG_MEMTEST_START 0x30000000 /* memtest works on */
163 #define CFG_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */
165 #define CFG_ALT_MEMTEST
166 #define CFG_LOAD_ADDR 0x30800000 /* default load address */
169 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
171 /* we configure PWM Timer 4 to 1us ~ 1MHz */
172 /*#define CFG_HZ 1000000 */
173 #define CFG_HZ 1562500
175 /* valid baudrates */
176 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
178 /************************************************************
180 ************************************************************/
181 /*#define VERSION_TAG "released"*/
182 #define VERSION_TAG "unstable"
183 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
185 /*-----------------------------------------------------------------------
188 * The stack sizes are set up in start.S using the settings below
190 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
191 #ifdef CONFIG_USE_IRQ
192 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
193 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
196 /*-----------------------------------------------------------------------
197 * Physical Memory Map
199 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
200 #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
201 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
203 #define CFG_FLASH_BASE PHYS_FLASH_1
205 /*-----------------------------------------------------------------------
206 * FLASH and environment organization
209 #define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
211 #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
214 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
215 #ifdef CONFIG_AMD_LV800
216 #define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
217 #define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
218 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
220 #ifdef CONFIG_AMD_LV400
221 #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
222 #define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
223 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
226 /* timeout values are in ticks */
227 #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
228 #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
231 #define CFG_ENV_IS_IN_FLASH 1
232 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
236 #define CFG_JFFS2_FIRST_BANK 0
237 #define CFG_JFFS2_NUM_BANKS 1
239 #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
241 /*-----------------------------------------------------------------------
242 * NAND flash settings
244 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
246 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
247 #define SECTORSIZE 512
249 #define ADDR_COLUMN 1
251 #define ADDR_COLUMN_PAGE 3
253 #define NAND_ChipID_UNKNOWN 0x00
254 #define NAND_MAX_FLOORS 1
255 #define NAND_MAX_CHIPS 1
257 #define NAND_WAIT_READY(nand) NF_WaitRB()
259 #define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
260 #define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
263 #define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
264 #define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
265 #define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
266 #define WRITE_NAND(d, adr) NF_Write(d)
267 #define READ_NAND(adr) NF_Read()
268 /* the following functions are NOP's because S3C24X0 handles this in hardware */
269 #define NAND_CTL_CLRALE(nandptr)
270 #define NAND_CTL_SETALE(nandptr)
271 #define NAND_CTL_CLRCLE(nandptr)
272 #define NAND_CTL_SETCLE(nandptr)
274 #define CONFIG_MTD_NAND_VERIFY_WRITE 1
275 #define CONFIG_MTD_NAND_ECC_JFFS2 1
277 #endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
279 #endif /* __CONFIG_H */