2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * Check valid setting of revision define.
32 * Total5100 and Total5200 Rev.1 are identical except for the processor.
34 #if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
35 #error CONFIG_TOTAL5200_REV must be 1 or 2
39 * High Level Configuration Options
43 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44 #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
45 #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
48 * Valid values for CONFIG_SYS_TEXT_BASE are:
49 * 0xFFF00000 boot high (standard configuration)
51 * 0x00100000 boot from RAM (for testing only)
53 #ifndef CONFIG_SYS_TEXT_BASE
54 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
57 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
59 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
60 #define BOOTFLAG_WARM 0x02 /* Software reboot */
62 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
65 * Serial console configuration
67 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
68 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
69 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
75 #define CONFIG_VIDEO_SED13806
76 #define CONFIG_VIDEO_SED13806_16BPP
78 #define CONFIG_CFB_CONSOLE
79 #define CONFIG_VIDEO_LOGO
80 /* #define CONFIG_VIDEO_BMP_LOGO */
81 #define CONFIG_CONSOLE_EXTRA_INFO
82 #define CONFIG_VGA_AS_SINGLE_DEVICE
83 #define CONFIG_VIDEO_SW_CURSOR
84 #define CONFIG_SPLASH_SCREEN
89 * 0x40000000 - 0x4fffffff - PCI Memory
90 * 0x50000000 - 0x50ffffff - PCI IO Space
93 #define CONFIG_PCI_PNP 1
94 #define CONFIG_PCI_SCAN_SHOW 1
95 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
97 #define CONFIG_PCI_MEM_BUS 0x40000000
98 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
99 #define CONFIG_PCI_MEM_SIZE 0x10000000
101 #define CONFIG_PCI_IO_BUS 0x50000000
102 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
103 #define CONFIG_PCI_IO_SIZE 0x01000000
105 #define CONFIG_NET_MULTI 1
107 #define CONFIG_EEPRO100 1
108 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
109 #define CONFIG_NS8382X 1
112 #define CONFIG_MAC_PARTITION
113 #define CONFIG_DOS_PARTITION
116 #define CONFIG_USB_OHCI
117 #define CONFIG_USB_STORAGE
123 #define CONFIG_BOOTP_BOOTFILESIZE
124 #define CONFIG_BOOTP_BOOTPATH
125 #define CONFIG_BOOTP_GATEWAY
126 #define CONFIG_BOOTP_HOSTNAME
130 * Command line configuration.
132 #include <config_cmd_default.h>
134 #define CONFIG_CMD_PCI
136 #define CONFIG_CMD_BMP
137 #define CONFIG_CMD_EEPROM
138 #define CONFIG_CMD_FAT
139 #define CONFIG_CMD_I2C
140 #define CONFIG_CMD_IDE
141 #define CONFIG_CMD_PING
142 #define CONFIG_CMD_USB
145 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
146 # define CONFIG_SYS_LOWBOOT 1
152 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
154 #define CONFIG_PREBOOT \
155 "setenv stdout serial;setenv stderr serial;" \
157 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
160 #undef CONFIG_BOOTARGS
162 #define CONFIG_EXTRA_ENV_SETTINGS \
164 "nfsargs=setenv bootargs root=/dev/nfs rw " \
165 "nfsroot=${serverip}:${rootpath}\0" \
166 "ramargs=setenv bootargs root=/dev/ram rw\0" \
167 "addip=setenv bootargs ${bootargs} " \
168 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
169 ":${hostname}:${netdev}:off panic=1\0" \
170 "flash_nfs=run nfsargs addip;" \
171 "bootm ${kernel_addr}\0" \
172 "flash_self=run ramargs addip;" \
173 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
174 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
175 "rootpath=/opt/eldk/ppc_82xx\0" \
176 "bootfile=/tftpboot/MPC5200/uImage\0" \
179 #define CONFIG_BOOTCOMMAND "run flash_self"
182 * IPB Bus clocking configuration.
184 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
189 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
190 #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
192 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
193 #define CONFIG_SYS_I2C_SLAVE 0x7F
196 * EEPROM configuration
198 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
199 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
201 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
204 * Flash configuration
206 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
207 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
208 #if CONFIG_TOTAL5200_REV==2
209 # define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
210 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
212 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
213 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
215 #define CONFIG_SYS_FLASH_EMPTY_INFO
216 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
218 #if CONFIG_TOTAL5200_REV==1
219 # define CONFIG_SYS_FLASH_BASE 0xFE000000
220 # define CONFIG_SYS_FLASH_SIZE 0x02000000
221 #elif CONFIG_TOTAL5200_REV==2
222 # define CONFIG_SYS_FLASH_BASE 0xFA000000
223 # define CONFIG_SYS_FLASH_SIZE 0x06000000
224 #endif /* CONFIG_TOTAL5200_REV */
226 #if defined(CONFIG_SYS_LOWBOOT)
227 # define CONFIG_ENV_ADDR 0xFE040000
228 #else /* CONFIG_SYS_LOWBOOT */
229 # define CONFIG_ENV_ADDR 0xFFF40000
230 #endif /* CONFIG_SYS_LOWBOOT */
233 * Environment settings
235 #define CONFIG_ENV_IS_IN_FLASH 1
236 #define CONFIG_ENV_SIZE 0x40000
237 #define CONFIG_ENV_SECT_SIZE 0x40000
238 #define CONFIG_ENV_OVERWRITE 1
243 #define CONFIG_SYS_SDRAM_BASE 0x00000000
244 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
245 #define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */
246 #define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */
247 #define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */
248 #define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */
250 /* Use SRAM until RAM will be available */
251 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
252 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
254 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
255 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
256 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
258 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
259 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
260 # define CONFIG_SYS_RAMBOOT 1
263 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
264 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
265 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
268 * Ethernet configuration
270 #define CONFIG_MPC5xxx_FEC 1
271 #define CONFIG_MPC5xxx_FEC_SEVENWIRE
272 /* dummy, 7-wire FEC does not have phy address */
273 #define CONFIG_PHY_ADDR 0x00
278 * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
280 * ALTs: CAN1/2 on PSC2, SPI on PSC3 00
281 * CS7: Interrupt GPIO on PSC3_5 0
282 * CS8: Interrupt GPIO on PSC3_4 0
283 * ATA: reset default, changed in ATA driver 00
284 * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
285 * IRDA: reset default, changed in IrDA driver 000
286 * ETHER: reset default, changed in Ethernet driver 0000
287 * PCI_DIS: reset default, changed in PCI driver 0
288 * USB_SE: reset default, changed in USB driver 0
289 * USB: reset default, changed in USB driver 00
290 * PSC3: SPI and UART functionality without CD 1100
294 * PSC1: reset default, changed in AC'97 driver 000
297 #define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10
300 * Miscellaneous configurable options
302 #define CONFIG_SYS_LONGHELP /* undef to save memory */
303 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
304 #if defined(CONFIG_CMD_KGDB)
305 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
307 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
309 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
310 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
311 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
313 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
314 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
316 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
318 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
320 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
321 #if defined(CONFIG_CMD_KGDB)
322 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
327 * Various low-level settings
329 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
330 #define CONFIG_SYS_HID0_FINAL HID0_ICE
332 #if CONFIG_TOTAL5200_REV==1
333 # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
334 # define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
335 # define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
336 # define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
337 # define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */
339 # define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
340 # define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
341 # define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
342 # define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
343 # define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */
344 # define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
345 # define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE
346 # define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */
347 # define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
350 #define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE
351 #define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */
352 #define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
354 #define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE
355 #define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */
356 #define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
358 #if CONFIG_TOTAL5200_REV==1
359 # define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
360 # define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
361 # define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
363 # define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
364 # define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
365 # define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
368 #define CONFIG_SYS_CS_BURST 0x00000000
369 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
371 /*-----------------------------------------------------------------------
373 *-----------------------------------------------------------------------
375 #define CONFIG_USB_CLOCK 0x0001BBBB
376 #define CONFIG_USB_CONFIG 0x00001000
378 /*-----------------------------------------------------------------------
379 * IDE/ATA stuff Supports IDE harddisk
380 *-----------------------------------------------------------------------
383 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
385 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
386 #undef CONFIG_IDE_LED /* LED for ide not supported */
388 #define CONFIG_IDE_RESET /* reset for ide supported */
389 #define CONFIG_IDE_PREINIT
391 #define CONFIG_SYS_ATA_CS_ON_I2C2
392 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
393 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
395 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
397 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
399 /* Offset for data I/O */
400 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
402 /* Offset for normal register accesses */
403 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
405 /* Offset for alternate registers */
406 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
408 /* Interval between registers */
409 #define CONFIG_SYS_ATA_STRIDE 4
411 #endif /* __CONFIG_H */