2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * Check valid setting of revision define.
32 * Total5100 and Total5200 Rev.1 are identical except for the processor.
34 #if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
35 #error CONFIG_TOTAL5200_REV must be 1 or 2
39 * High Level Configuration Options
43 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44 #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
46 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
48 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
49 #define BOOTFLAG_WARM 0x02 /* Software reboot */
51 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
52 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
53 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
57 * Serial console configuration
59 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
60 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
61 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
67 #define CONFIG_VIDEO_SED13806
68 #define CONFIG_VIDEO_SED13806_16BPP
70 #define CONFIG_CFB_CONSOLE
71 #define CONFIG_VIDEO_LOGO
72 /* #define CONFIG_VIDEO_BMP_LOGO */
73 #define CONFIG_CONSOLE_EXTRA_INFO
74 #define CONFIG_VGA_AS_SINGLE_DEVICE
75 #define CONFIG_VIDEO_SW_CURSOR
76 #define CONFIG_SPLASH_SCREEN
78 #define ADD_VIDEO_CMD CFG_CMD_BMP
80 #define ADD_VIDEO_CMD 0
83 #ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */
86 * 0x40000000 - 0x4fffffff - PCI Memory
87 * 0x50000000 - 0x50ffffff - PCI IO Space
90 #define CONFIG_PCI_PNP 1
91 #define CONFIG_PCI_SCAN_SHOW 1
93 #define CONFIG_PCI_MEM_BUS 0x40000000
94 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
95 #define CONFIG_PCI_MEM_SIZE 0x10000000
97 #define CONFIG_PCI_IO_BUS 0x50000000
98 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
99 #define CONFIG_PCI_IO_SIZE 0x01000000
101 #define CONFIG_NET_MULTI 1
102 #define CONFIG_EEPRO100 1
103 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
104 #define CONFIG_NS8382X 1
106 #define ADD_PCI_CMD CFG_CMD_PCI
110 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
115 #define CONFIG_MAC_PARTITION
116 #define CONFIG_DOS_PARTITION
120 #define CONFIG_USB_OHCI
121 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
122 #define CONFIG_USB_STORAGE
124 #define ADD_USB_CMD 0
130 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
140 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
141 #include <cmd_confdefs.h>
143 #if (TEXT_BASE == 0xFE000000) /* Boot low */
144 # define CFG_LOWBOOT 1
150 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
152 #define CONFIG_PREBOOT \
153 "setenv stdout serial;setenv stderr serial;" \
155 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
158 #undef CONFIG_BOOTARGS
160 #define CONFIG_EXTRA_ENV_SETTINGS \
162 "nfsargs=setenv bootargs root=/dev/nfs rw " \
163 "nfsroot=$(serverip):$(rootpath)\0" \
164 "ramargs=setenv bootargs root=/dev/ram rw\0" \
165 "addip=setenv bootargs $(bootargs) " \
166 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
167 ":$(hostname):$(netdev):off panic=1\0" \
168 "flash_nfs=run nfsargs addip;" \
169 "bootm $(kernel_addr)\0" \
170 "flash_self=run ramargs addip;" \
171 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
172 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
173 "rootpath=/opt/eldk/ppc_82xx\0" \
174 "bootfile=/tftpboot/MPC5200/uImage\0" \
178 #define CONFIG_BOOTCOMMAND "run flash_self"
180 #if defined(CONFIG_MPC5200)
182 * IPB Bus clocking configuration.
184 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
190 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
191 #define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
193 #define CFG_I2C_SPEED 100000 /* 100 kHz */
194 #define CFG_I2C_SLAVE 0x7F
197 * EEPROM configuration
199 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
200 #define CFG_I2C_EEPROM_ADDR_LEN 1
201 #define CFG_EEPROM_PAGE_WRITE_BITS 3
202 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
205 * Flash configuration
207 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
208 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
209 #if CONFIG_TOTAL5200_REV==2
210 # define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */
211 # define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
213 # define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
214 # define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
216 #define CFG_FLASH_EMPTY_INFO
217 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
219 #if CONFIG_TOTAL5200_REV==1
220 # define CFG_FLASH_BASE 0xFE000000
221 # define CFG_FLASH_SIZE 0x02000000
222 #elif CONFIG_TOTAL5200_REV==2
223 # define CFG_FLASH_BASE 0xFA000000
224 # define CFG_FLASH_SIZE 0x06000000
225 #endif /* CONFIG_TOTAL5200_REV */
227 #if defined(CFG_LOWBOOT)
228 # define CFG_ENV_ADDR 0xFE040000
229 #else /* CFG_LOWBOOT */
230 # define CFG_ENV_ADDR 0xFFF40000
231 #endif /* CFG_LOWBOOT */
234 * Environment settings
236 #define CFG_ENV_IS_IN_FLASH 1
237 #define CFG_ENV_SIZE 0x40000
238 #define CFG_ENV_SECT_SIZE 0x40000
239 #define CONFIG_ENV_OVERWRITE 1
244 #define CFG_SDRAM_BASE 0x00000000
245 #define CFG_DEFAULT_MBAR 0x80000000
246 #define CFG_MBAR 0xF0000000 /* 64 kB */
247 #define CFG_FPGA_BASE 0xF0010000 /* 64 kB */
248 #define CFG_CPLD_BASE 0xF0020000 /* 64 kB */
249 #define CFG_LCD_BASE 0xF1000000 /* 4096 kB */
251 /* Use SRAM until RAM will be available */
252 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
253 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
255 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
256 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
257 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
259 #define CFG_MONITOR_BASE TEXT_BASE
260 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
261 # define CFG_RAMBOOT 1
264 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
265 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
266 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
269 * Ethernet configuration
271 #define CONFIG_MPC5xxx_FEC 1
272 /* dummy, 7-wire FEC does not have phy address */
273 #define CONFIG_PHY_ADDR 0x00
278 * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
280 * ALTs: CAN1/2 on PSC2, SPI on PSC3 00
281 * CS7: Interrupt GPIO on PSC3_5 0
282 * CS8: Interrupt GPIO on PSC3_4 0
283 * ATA: reset default, changed in ATA driver 00
284 * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
285 * IRDA: reset default, changed in IrDA driver 000
286 * ETHER: reset default, changed in Ethernet driver 0000
287 * PCI_DIS: reset default, changed in PCI driver 0
288 * USB_SE: reset default, changed in USB driver 0
289 * USB: reset default, changed in USB driver 00
290 * PSC3: SPI and UART functionality without CD 1100
294 * PSC1: reset default, changed in AC'97 driver 000
297 #define CFG_GPS_PORT_CONFIG 0x00000C10
300 * Miscellaneous configurable options
302 #define CFG_LONGHELP /* undef to save memory */
303 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
304 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
305 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
307 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
309 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
310 #define CFG_MAXARGS 16 /* max number of command args */
311 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
313 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
314 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
316 #define CFG_LOAD_ADDR 0x100000 /* default load address */
318 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
321 * Various low-level settings
323 #if defined(CONFIG_MPC5200)
324 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
325 #define CFG_HID0_FINAL HID0_ICE
327 #define CFG_HID0_INIT 0
328 #define CFG_HID0_FINAL 0
331 #if defined (CONFIG_MGT5100)
332 # define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */
335 #if CONFIG_TOTAL5200_REV==1
336 # define CFG_BOOTCS_START CFG_FLASH_BASE
337 # define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */
338 # define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
339 # define CFG_CS0_START CFG_FLASH_BASE
340 # define CFG_CS0_SIZE 0x02000000 /* 32 MB */
342 # define CFG_BOOTCS_START (CFG_CS4_START + CFG_CS4_SIZE)
343 # define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */
344 # define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
345 # define CFG_CS4_START (CFG_CS5_START + CFG_CS5_SIZE)
346 # define CFG_CS4_SIZE 0x02000000 /* 32 MB */
347 # define CFG_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
348 # define CFG_CS5_START CFG_FLASH_BASE
349 # define CFG_CS5_SIZE 0x02000000 /* 32 MB */
350 # define CFG_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
353 #define CFG_CS1_START CFG_FPGA_BASE
354 #define CFG_CS1_SIZE 0x00010000 /* 64 kB */
355 #define CFG_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
357 #define CFG_CS2_START CFG_LCD_BASE
358 #define CFG_CS2_SIZE 0x00400000 /* 4096 kB */
359 #define CFG_CS2_CFG 0x0032FD00 /* 50WS, MX, AL, AA, CE, AS_25, DS_16 */
361 #if CONFIG_TOTAL5200_REV==1
362 # define CFG_CS3_START CFG_CPLD_BASE
363 # define CFG_CS3_SIZE 0x00010000 /* 64 kB */
364 # define CFG_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
366 # define CFG_CS3_START CFG_CPLD_BASE
367 # define CFG_CS3_SIZE 0x00010000 /* 64 kB */
368 # define CFG_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
371 #define CFG_CS_BURST 0x00000000
372 #define CFG_CS_DEADCYCLE 0x33333333
374 /*-----------------------------------------------------------------------
376 *-----------------------------------------------------------------------
378 #define CONFIG_USB_CLOCK 0x0001BBBB
379 #define CONFIG_USB_CONFIG 0x00001000
381 /*-----------------------------------------------------------------------
382 * IDE/ATA stuff Supports IDE harddisk
383 *-----------------------------------------------------------------------
386 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
388 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
389 #undef CONFIG_IDE_LED /* LED for ide not supported */
391 #define CONFIG_IDE_RESET /* reset for ide supported */
392 #define CONFIG_IDE_PREINIT
394 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
395 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
397 #define CFG_ATA_IDE0_OFFSET 0x0000
399 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
401 /* Offset for data I/O */
402 #define CFG_ATA_DATA_OFFSET (0x0060)
404 /* Offset for normal register accesses */
405 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
407 /* Offset for alternate registers */
408 #define CFG_ATA_ALT_OFFSET (0x005C)
410 /* Interval between registers */
411 #define CFG_ATA_STRIDE 4
413 #endif /* __CONFIG_H */