2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * Check valid setting of revision define.
32 * Total5100 and Total5200 Rev.1 are identical except for the processor.
34 #if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
35 #error CONFIG_TOTAL5200_REV must be 1 or 2
39 * High Level Configuration Options
43 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44 #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
46 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
48 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
49 #define BOOTFLAG_WARM 0x02 /* Software reboot */
52 * Serial console configuration
54 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
55 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
56 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
62 #define CONFIG_VIDEO_SED13806
63 #define CONFIG_VIDEO_SED13806_16BPP
65 #define CONFIG_CFB_CONSOLE
66 #define CONFIG_VIDEO_LOGO
67 /* #define CONFIG_VIDEO_BMP_LOGO */
68 #define CONFIG_CONSOLE_EXTRA_INFO
69 #define CONFIG_VGA_AS_SINGLE_DEVICE
70 #define CONFIG_VIDEO_SW_CURSOR
71 #define CONFIG_SPLASH_SCREEN
74 #ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */
77 * 0x40000000 - 0x4fffffff - PCI Memory
78 * 0x50000000 - 0x50ffffff - PCI IO Space
81 #define CONFIG_PCI_PNP 1
82 #define CONFIG_PCI_SCAN_SHOW 1
83 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
85 #define CONFIG_PCI_MEM_BUS 0x40000000
86 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
87 #define CONFIG_PCI_MEM_SIZE 0x10000000
89 #define CONFIG_PCI_IO_BUS 0x50000000
90 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
91 #define CONFIG_PCI_IO_SIZE 0x01000000
93 #define CONFIG_NET_MULTI 1
95 #define CONFIG_EEPRO100 1
96 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
97 #define CONFIG_NS8382X 1
106 #define CONFIG_MAC_PARTITION
107 #define CONFIG_DOS_PARTITION
110 #define CONFIG_USB_OHCI
111 #define CONFIG_USB_STORAGE
117 #define CONFIG_BOOTP_BOOTFILESIZE
118 #define CONFIG_BOOTP_BOOTPATH
119 #define CONFIG_BOOTP_GATEWAY
120 #define CONFIG_BOOTP_HOSTNAME
124 * Command line configuration.
126 #include <config_cmd_default.h>
128 #if defined(CONFIG_MPC5200)
129 #define CONFIG_CMD_PCI
132 #define CONFIG_CMD_BMP
133 #define CONFIG_CMD_EEPROM
134 #define CONFIG_CMD_FAT
135 #define CONFIG_CMD_I2C
136 #define CONFIG_CMD_IDE
137 #define CONFIG_CMD_PING
138 #define CONFIG_CMD_USB
141 #if (TEXT_BASE == 0xFE000000) /* Boot low */
142 # define CFG_LOWBOOT 1
148 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
150 #define CONFIG_PREBOOT \
151 "setenv stdout serial;setenv stderr serial;" \
153 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
156 #undef CONFIG_BOOTARGS
158 #define CONFIG_EXTRA_ENV_SETTINGS \
160 "nfsargs=setenv bootargs root=/dev/nfs rw " \
161 "nfsroot=${serverip}:${rootpath}\0" \
162 "ramargs=setenv bootargs root=/dev/ram rw\0" \
163 "addip=setenv bootargs ${bootargs} " \
164 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
165 ":${hostname}:${netdev}:off panic=1\0" \
166 "flash_nfs=run nfsargs addip;" \
167 "bootm ${kernel_addr}\0" \
168 "flash_self=run ramargs addip;" \
169 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
170 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
171 "rootpath=/opt/eldk/ppc_82xx\0" \
172 "bootfile=/tftpboot/MPC5200/uImage\0" \
175 #define CONFIG_BOOTCOMMAND "run flash_self"
177 #if defined(CONFIG_MPC5200)
179 * IPB Bus clocking configuration.
181 #undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
187 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
188 #define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
190 #define CFG_I2C_SPEED 100000 /* 100 kHz */
191 #define CFG_I2C_SLAVE 0x7F
194 * EEPROM configuration
196 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
197 #define CFG_I2C_EEPROM_ADDR_LEN 1
198 #define CFG_EEPROM_PAGE_WRITE_BITS 3
199 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
202 * Flash configuration
204 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
205 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
206 #if CONFIG_TOTAL5200_REV==2
207 # define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */
208 # define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
210 # define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
211 # define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
213 #define CFG_FLASH_EMPTY_INFO
214 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
216 #if CONFIG_TOTAL5200_REV==1
217 # define CFG_FLASH_BASE 0xFE000000
218 # define CFG_FLASH_SIZE 0x02000000
219 #elif CONFIG_TOTAL5200_REV==2
220 # define CFG_FLASH_BASE 0xFA000000
221 # define CFG_FLASH_SIZE 0x06000000
222 #endif /* CONFIG_TOTAL5200_REV */
224 #if defined(CFG_LOWBOOT)
225 # define CFG_ENV_ADDR 0xFE040000
226 #else /* CFG_LOWBOOT */
227 # define CFG_ENV_ADDR 0xFFF40000
228 #endif /* CFG_LOWBOOT */
231 * Environment settings
233 #define CFG_ENV_IS_IN_FLASH 1
234 #define CFG_ENV_SIZE 0x40000
235 #define CFG_ENV_SECT_SIZE 0x40000
236 #define CONFIG_ENV_OVERWRITE 1
241 #define CFG_SDRAM_BASE 0x00000000
242 #define CFG_DEFAULT_MBAR 0x80000000
243 #define CFG_MBAR 0xF0000000 /* 64 kB */
244 #define CFG_FPGA_BASE 0xF0010000 /* 64 kB */
245 #define CFG_CPLD_BASE 0xF0020000 /* 64 kB */
246 #define CFG_LCD_BASE 0xF1000000 /* 4096 kB */
248 /* Use SRAM until RAM will be available */
249 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
250 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
252 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
253 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
254 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
256 #define CFG_MONITOR_BASE TEXT_BASE
257 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
258 # define CFG_RAMBOOT 1
261 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
262 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
263 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
266 * Ethernet configuration
268 #define CONFIG_MPC5xxx_FEC 1
269 /* dummy, 7-wire FEC does not have phy address */
270 #define CONFIG_PHY_ADDR 0x00
275 * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
277 * ALTs: CAN1/2 on PSC2, SPI on PSC3 00
278 * CS7: Interrupt GPIO on PSC3_5 0
279 * CS8: Interrupt GPIO on PSC3_4 0
280 * ATA: reset default, changed in ATA driver 00
281 * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
282 * IRDA: reset default, changed in IrDA driver 000
283 * ETHER: reset default, changed in Ethernet driver 0000
284 * PCI_DIS: reset default, changed in PCI driver 0
285 * USB_SE: reset default, changed in USB driver 0
286 * USB: reset default, changed in USB driver 00
287 * PSC3: SPI and UART functionality without CD 1100
291 * PSC1: reset default, changed in AC'97 driver 000
294 #define CFG_GPS_PORT_CONFIG 0x00000C10
297 * Miscellaneous configurable options
299 #define CFG_LONGHELP /* undef to save memory */
300 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
301 #if defined(CONFIG_CMD_KGDB)
302 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
304 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
306 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
307 #define CFG_MAXARGS 16 /* max number of command args */
308 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
310 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
311 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
313 #define CFG_LOAD_ADDR 0x100000 /* default load address */
315 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
317 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
318 #if defined(CONFIG_CMD_KGDB)
319 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
324 * Various low-level settings
326 #if defined(CONFIG_MPC5200)
327 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
328 #define CFG_HID0_FINAL HID0_ICE
330 #define CFG_HID0_INIT 0
331 #define CFG_HID0_FINAL 0
334 #if defined (CONFIG_MGT5100)
335 # define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */
338 #if CONFIG_TOTAL5200_REV==1
339 # define CFG_BOOTCS_START CFG_FLASH_BASE
340 # define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */
341 # define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
342 # define CFG_CS0_START CFG_FLASH_BASE
343 # define CFG_CS0_SIZE 0x02000000 /* 32 MB */
345 # define CFG_BOOTCS_START (CFG_CS4_START + CFG_CS4_SIZE)
346 # define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */
347 # define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
348 # define CFG_CS4_START (CFG_CS5_START + CFG_CS5_SIZE)
349 # define CFG_CS4_SIZE 0x02000000 /* 32 MB */
350 # define CFG_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
351 # define CFG_CS5_START CFG_FLASH_BASE
352 # define CFG_CS5_SIZE 0x02000000 /* 32 MB */
353 # define CFG_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
356 #define CFG_CS1_START CFG_FPGA_BASE
357 #define CFG_CS1_SIZE 0x00010000 /* 64 kB */
358 #define CFG_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
360 #define CFG_CS2_START CFG_LCD_BASE
361 #define CFG_CS2_SIZE 0x00400000 /* 4096 kB */
362 #define CFG_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
364 #if CONFIG_TOTAL5200_REV==1
365 # define CFG_CS3_START CFG_CPLD_BASE
366 # define CFG_CS3_SIZE 0x00010000 /* 64 kB */
367 # define CFG_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
369 # define CFG_CS3_START CFG_CPLD_BASE
370 # define CFG_CS3_SIZE 0x00010000 /* 64 kB */
371 # define CFG_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
374 #define CFG_CS_BURST 0x00000000
375 #define CFG_CS_DEADCYCLE 0x33333333
377 /*-----------------------------------------------------------------------
379 *-----------------------------------------------------------------------
381 #define CONFIG_USB_CLOCK 0x0001BBBB
382 #define CONFIG_USB_CONFIG 0x00001000
384 /*-----------------------------------------------------------------------
385 * IDE/ATA stuff Supports IDE harddisk
386 *-----------------------------------------------------------------------
389 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
391 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
392 #undef CONFIG_IDE_LED /* LED for ide not supported */
394 #define CONFIG_IDE_RESET /* reset for ide supported */
395 #define CONFIG_IDE_PREINIT
397 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
398 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
400 #define CFG_ATA_IDE0_OFFSET 0x0000
402 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
404 /* Offset for data I/O */
405 #define CFG_ATA_DATA_OFFSET (0x0060)
407 /* Offset for normal register accesses */
408 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
410 /* Offset for alternate registers */
411 #define CFG_ATA_ALT_OFFSET (0x005C)
413 /* Interval between registers */
414 #define CFG_ATA_STRIDE 4
416 #endif /* __CONFIG_H */