2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * board/config.h - configuration options, board specific
35 * High Level Configuration Options
39 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */
40 #define CONFIG_TQM885D 1 /* ...on a TQM88D module */
42 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
43 #define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
44 #define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
45 #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
46 /* (it will be used if there is no */
47 /* 'cpuclk' variable with valid value) */
49 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
51 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
53 #define CONFIG_BOOTCOUNT_LIMIT
55 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57 #define CONFIG_BOARD_TYPES 1 /* support board types */
59 #define CONFIG_PREBOOT "echo;" \
60 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
63 #undef CONFIG_BOOTARGS
65 #define CONFIG_EXTRA_ENV_SETTINGS \
67 "nfsargs=setenv bootargs root=/dev/nfs rw " \
68 "nfsroot=${serverip}:${rootpath}\0" \
69 "ramargs=setenv bootargs root=/dev/ram rw\0" \
70 "addip=setenv bootargs ${bootargs} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
72 ":${hostname}:${netdev}:off panic=1\0" \
73 "flash_nfs=run nfsargs addip;" \
74 "bootm ${kernel_addr}\0" \
75 "flash_self=run ramargs addip;" \
76 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
77 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
78 "rootpath=/opt/eldk/ppc_8xx\0" \
79 "bootfile=/tftpboot/TQM866M/uImage\0" \
80 "kernel_addr=40080000\0" \
81 "ramdisk_addr=40180000\0" \
83 #define CONFIG_BOOTCOMMAND "run flash_self"
85 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
86 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
88 #undef CONFIG_WATCHDOG /* watchdog disabled */
90 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
92 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
94 /* enable I2C and select the hardware/software driver */
95 #undef CONFIG_HARD_I2C /* I2C with hardware support */
96 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
98 #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
99 #define CFG_I2C_SLAVE 0xFE
101 #ifdef CONFIG_SOFT_I2C
103 * Software (bit-bang) I2C driver configuration
105 #define PB_SCL 0x00000020 /* PB 26 */
106 #define PB_SDA 0x00000010 /* PB 27 */
108 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
109 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
110 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
111 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
112 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
113 else immr->im_cpm.cp_pbdat &= ~PB_SDA
114 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
115 else immr->im_cpm.cp_pbdat &= ~PB_SCL
116 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
117 #endif /* CONFIG_SOFT_I2C */
119 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
120 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
121 #define CFG_EEPROM_PAGE_WRITE_BITS 4
122 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
124 # define CONFIG_RTC_DS1337 1
125 # define CFG_I2C_RTC_ADDR 0x68
130 #define CONFIG_BOOTP_SUBNETMASK
131 #define CONFIG_BOOTP_GATEWAY
132 #define CONFIG_BOOTP_HOSTNAME
133 #define CONFIG_BOOTP_BOOTPATH
134 #define CONFIG_BOOTP_BOOTFILESIZE
137 #define CONFIG_MAC_PARTITION
138 #define CONFIG_DOS_PARTITION
140 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
142 #define CONFIG_TIMESTAMP /* but print image timestmps */
146 * Command line configuration.
148 #include <config_cmd_default.h>
150 #define CONFIG_CMD_ASKENV
151 #define CONFIG_CMD_DATE
152 #define CONFIG_CMD_DHCP
153 #define CONFIG_CMD_EEPROM
154 #define CONFIG_CMD_I2C
155 #define CONFIG_CMD_IDE
156 #define CONFIG_CMD_MII
157 #define CONFIG_CMD_NFS
158 #define CONFIG_CMD_PING
162 * Miscellaneous configurable options
164 #define CFG_LONGHELP /* undef to save memory */
165 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
167 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
168 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
169 #ifdef CFG_HUSH_PARSER
170 #define CFG_PROMPT_HUSH_PS2 "> "
173 #if defined(CONFIG_CMD_KGDB)
174 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
176 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
178 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
179 #define CFG_MAXARGS 16 /* max number of command args */
180 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
182 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
183 #define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
184 #define CFG_ALT_MEMTEST /* alternate, more extensive
187 #define CFG_LOAD_ADDR 0x100000 /* default load address */
189 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
191 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
194 * Enable loopw command.
199 * Low Level Configuration Settings
200 * (address mappings, register initial values, etc.)
201 * You should know what you are doing if you make changes here.
203 /*-----------------------------------------------------------------------
204 * Internal Memory Mapped Register
206 #define CFG_IMMR 0xFFF00000
208 /*-----------------------------------------------------------------------
209 * Definitions for initial stack pointer and data area (in DPRAM)
211 #define CFG_INIT_RAM_ADDR CFG_IMMR
212 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
213 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
214 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
215 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
217 /*-----------------------------------------------------------------------
218 * Start addresses for the final memory configuration
219 * (Set up by the startup code)
220 * Please note that CFG_SDRAM_BASE _must_ start at 0
222 #define CFG_SDRAM_BASE 0x00000000
223 #define CFG_FLASH_BASE 0x40000000
224 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
225 #define CFG_MONITOR_BASE CFG_FLASH_BASE
226 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
229 * For booting Linux, the board info and command line data
230 * have to be in the first 8 MB of memory, since this is
231 * the maximum mapped by the Linux kernel during initialization.
233 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
235 /*-----------------------------------------------------------------------
238 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
239 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
241 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
242 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
244 #define CFG_ENV_IS_IN_FLASH 1
245 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
246 #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
247 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
249 /* Address and size of Redundant Environment Sector */
250 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
251 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
253 /*-----------------------------------------------------------------------
254 * Hardware Information Block
256 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
257 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
258 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
260 /*-----------------------------------------------------------------------
261 * Cache Configuration
263 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
264 #if defined(CONFIG_CMD_KGDB)
265 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
268 /*-----------------------------------------------------------------------
269 * SYPCR - System Protection Control 11-9
270 * SYPCR can only be written once after reset!
271 *-----------------------------------------------------------------------
272 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
274 #if defined(CONFIG_WATCHDOG)
275 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
276 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
278 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
281 /*-----------------------------------------------------------------------
282 * SIUMCR - SIU Module Configuration 11-6
283 *-----------------------------------------------------------------------
284 * PCMCIA config., multi-function pin tri-state
286 #ifndef CONFIG_CAN_DRIVER
287 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
288 #else /* we must activate GPL5 in the SIUMCR for CAN */
289 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
290 #endif /* CONFIG_CAN_DRIVER */
292 /*-----------------------------------------------------------------------
293 * TBSCR - Time Base Status and Control 11-26
294 *-----------------------------------------------------------------------
295 * Clear Reference Interrupt Status, Timebase freezing enabled
297 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
299 /*-----------------------------------------------------------------------
300 * PISCR - Periodic Interrupt Status and Control 11-31
301 *-----------------------------------------------------------------------
302 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
304 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
306 /*-----------------------------------------------------------------------
307 * SCCR - System Clock and reset Control Register 15-27
308 *-----------------------------------------------------------------------
309 * Set clock output, timebase and RTC source and divider,
310 * power management and some other internal clocks
312 #define SCCR_MASK SCCR_EBDF11
313 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
314 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
317 /*-----------------------------------------------------------------------
319 *-----------------------------------------------------------------------
322 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
323 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
324 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
325 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
326 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
327 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
328 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
329 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
331 /*-----------------------------------------------------------------------
332 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
333 *-----------------------------------------------------------------------
336 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
338 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
339 #undef CONFIG_IDE_LED /* LED for ide not supported */
340 #undef CONFIG_IDE_RESET /* reset for ide not supported */
342 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
343 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
345 #define CFG_ATA_IDE0_OFFSET 0x0000
347 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
349 /* Offset for data I/O */
350 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
352 /* Offset for normal register accesses */
353 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
355 /* Offset for alternate registers */
356 #define CFG_ATA_ALT_OFFSET 0x0100
358 /*-----------------------------------------------------------------------
360 *-----------------------------------------------------------------------
366 * Init Memory Controller:
368 * BR0/1 and OR0/1 (FLASH)
371 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
372 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
374 /* used to re-map FLASH both when starting from SRAM or FLASH:
375 * restrict access enough to keep SRAM working (if any)
376 * but not too much to meddle with FLASH accesses
378 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
379 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
382 * FLASH timing: Default value of OR0 after reset
384 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
385 OR_SCY_6_CLK | OR_TRLX)
387 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
388 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
389 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
391 #define CFG_OR1_REMAP CFG_OR0_REMAP
392 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
393 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
396 * BR2/3 and OR2/3 (SDRAM)
399 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
400 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
401 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
403 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
404 #define CFG_OR_TIMING_SDRAM 0x00000A00
406 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
407 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
409 #ifndef CONFIG_CAN_DRIVER
410 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
411 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
412 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
413 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
414 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
415 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
416 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
417 BR_PS_8 | BR_MS_UPMB | BR_V )
418 #endif /* CONFIG_CAN_DRIVER */
421 * 4096 Rows from SDRAM example configuration
422 * 1000 factor s -> ms
423 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
424 * 4 Number of refresh cycles per period
425 * 64 Refresh cycle in ms per number of rows
427 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
430 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
432 * CPUclock(MHz) * 31.2
433 * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
434 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
436 * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
437 * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
438 * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
439 * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
441 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
442 * be met also in the default configuration, i.e. if environment variable
443 * 'cpuclk' is not set.
445 #define CFG_MAMR_PTA 128
448 * Memory Periodic Timer Prescaler Register (MPTPR) values.
450 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
451 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
452 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
453 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
456 * MAMR settings for SDRAM
460 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
461 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
462 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
464 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
465 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
467 /* 10 column SDRAM */
468 #define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
469 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
473 * Internal Definitions
477 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
478 #define BOOTFLAG_WARM 0x02 /* Software reboot */
481 * Network configuration
483 #define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
484 #define CONFIG_FEC_ENET /* enable ethernet on FEC */
485 #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
486 #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
488 #if defined(CONFIG_CMD_MII)
489 #define CFG_DISCOVER_PHY
492 #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
493 switching to another netwok (if the
494 tried network is unreachable) */
496 #define CONFIG_ETHPRIME "SCC ETHERNET"
498 #endif /* __CONFIG_H */