2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * board/config.h - configuration options, board specific
35 * High Level Configuration Options
39 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */
40 #define CONFIG_TQM885D 1 /* ...on a TQM88D module */
42 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
43 #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
44 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
45 #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
46 /* (it will be used if there is no */
47 /* 'cpuclk' variable with valid value) */
49 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
51 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
53 #define CONFIG_BOOTCOUNT_LIMIT
55 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57 #define CONFIG_BOARD_TYPES 1 /* support board types */
59 #define CONFIG_PREBOOT "echo;" \
60 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
63 #undef CONFIG_BOOTARGS
65 #define CONFIG_EXTRA_ENV_SETTINGS \
67 "nfsargs=setenv bootargs root=/dev/nfs rw " \
68 "nfsroot=${serverip}:${rootpath}\0" \
69 "ramargs=setenv bootargs root=/dev/ram rw\0" \
70 "addip=setenv bootargs ${bootargs} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
72 ":${hostname}:${netdev}:off panic=1\0" \
73 "flash_nfs=run nfsargs addip;" \
74 "bootm ${kernel_addr}\0" \
75 "flash_self=run ramargs addip;" \
76 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
77 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
78 "rootpath=/opt/eldk/ppc_8xx\0" \
79 "bootfile=/tftpboot/TQM885D/uImage\0" \
80 "fdt_addr=400C0000\0" \
81 "kernel_addr=40100000\0" \
82 "ramdisk_addr=40280000\0" \
83 "load=tftp 200000 ${u-boot}\0" \
84 "update=protect off 40000000 +${filesize};" \
85 "erase 40000000 +${filesize};" \
86 "cp.b 200000 40000000 ${filesize};" \
87 "protect on 40000000 +${filesize}\0" \
89 #define CONFIG_BOOTCOMMAND "run flash_self"
91 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
92 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
94 #undef CONFIG_WATCHDOG /* watchdog disabled */
96 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
98 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
100 /* enable I2C and select the hardware/software driver */
101 #undef CONFIG_HARD_I2C /* I2C with hardware support */
102 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
104 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
105 #define CONFIG_SYS_I2C_SLAVE 0xFE
107 #ifdef CONFIG_SOFT_I2C
109 * Software (bit-bang) I2C driver configuration
111 #define PB_SCL 0x00000020 /* PB 26 */
112 #define PB_SDA 0x00000010 /* PB 27 */
114 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
115 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
116 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
117 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
118 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
119 else immr->im_cpm.cp_pbdat &= ~PB_SDA
120 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
121 else immr->im_cpm.cp_pbdat &= ~PB_SCL
122 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
123 #endif /* CONFIG_SOFT_I2C */
125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
127 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
128 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
130 # define CONFIG_RTC_DS1337 1
131 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
136 #define CONFIG_BOOTP_SUBNETMASK
137 #define CONFIG_BOOTP_GATEWAY
138 #define CONFIG_BOOTP_HOSTNAME
139 #define CONFIG_BOOTP_BOOTPATH
140 #define CONFIG_BOOTP_BOOTFILESIZE
143 #define CONFIG_MAC_PARTITION
144 #define CONFIG_DOS_PARTITION
146 #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
148 #define CONFIG_TIMESTAMP /* but print image timestmps */
152 * Command line configuration.
154 #include <config_cmd_default.h>
156 #define CONFIG_CMD_ASKENV
157 #define CONFIG_CMD_DATE
158 #define CONFIG_CMD_DHCP
159 #define CONFIG_CMD_EEPROM
160 #define CONFIG_CMD_EXT2
161 #define CONFIG_CMD_I2C
162 #define CONFIG_CMD_IDE
163 #define CONFIG_CMD_MII
164 #define CONFIG_CMD_NFS
165 #define CONFIG_CMD_PING
169 * Miscellaneous configurable options
171 #define CONFIG_SYS_LONGHELP /* undef to save memory */
172 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
174 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
175 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
176 #ifdef CONFIG_SYS_HUSH_PARSER
177 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
180 #if defined(CONFIG_CMD_KGDB)
181 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
183 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
185 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
186 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
187 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
189 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
190 #define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
191 #define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
194 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
196 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
198 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
201 * Enable loopw command.
206 * Low Level Configuration Settings
207 * (address mappings, register initial values, etc.)
208 * You should know what you are doing if you make changes here.
210 /*-----------------------------------------------------------------------
211 * Internal Memory Mapped Register
213 #define CONFIG_SYS_IMMR 0xFFF00000
215 /*-----------------------------------------------------------------------
216 * Definitions for initial stack pointer and data area (in DPRAM)
218 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
219 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
220 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
221 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
222 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
224 /*-----------------------------------------------------------------------
225 * Start addresses for the final memory configuration
226 * (Set up by the startup code)
227 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
229 #define CONFIG_SYS_SDRAM_BASE 0x00000000
230 #define CONFIG_SYS_FLASH_BASE 0x40000000
231 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
233 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
236 * For booting Linux, the board info and command line data
237 * have to be in the first 8 MB of memory, since this is
238 * the maximum mapped by the Linux kernel during initialization.
240 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
242 /*-----------------------------------------------------------------------
246 /* use CFI flash driver */
247 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
248 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
249 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
250 #define CONFIG_SYS_FLASH_EMPTY_INFO
251 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
252 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
253 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
255 #define CONFIG_ENV_IS_IN_FLASH 1
256 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
257 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
258 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
260 /* Address and size of Redundant Environment Sector */
261 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
262 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
264 /*-----------------------------------------------------------------------
265 * Hardware Information Block
267 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
268 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
269 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
271 /*-----------------------------------------------------------------------
272 * Cache Configuration
274 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
275 #if defined(CONFIG_CMD_KGDB)
276 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
279 /*-----------------------------------------------------------------------
280 * SYPCR - System Protection Control 11-9
281 * SYPCR can only be written once after reset!
282 *-----------------------------------------------------------------------
283 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
285 #if defined(CONFIG_WATCHDOG)
286 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
287 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
289 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
292 /*-----------------------------------------------------------------------
293 * SIUMCR - SIU Module Configuration 11-6
294 *-----------------------------------------------------------------------
295 * PCMCIA config., multi-function pin tri-state
297 #ifndef CONFIG_CAN_DRIVER
298 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
299 #else /* we must activate GPL5 in the SIUMCR for CAN */
300 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
301 #endif /* CONFIG_CAN_DRIVER */
303 /*-----------------------------------------------------------------------
304 * TBSCR - Time Base Status and Control 11-26
305 *-----------------------------------------------------------------------
306 * Clear Reference Interrupt Status, Timebase freezing enabled
308 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
310 /*-----------------------------------------------------------------------
311 * PISCR - Periodic Interrupt Status and Control 11-31
312 *-----------------------------------------------------------------------
313 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
315 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
317 /*-----------------------------------------------------------------------
318 * SCCR - System Clock and reset Control Register 15-27
319 *-----------------------------------------------------------------------
320 * Set clock output, timebase and RTC source and divider,
321 * power management and some other internal clocks
323 #define SCCR_MASK SCCR_EBDF11
324 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
325 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
328 /*-----------------------------------------------------------------------
330 *-----------------------------------------------------------------------
333 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
334 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
335 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
336 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
337 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
338 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
339 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
340 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
342 /*-----------------------------------------------------------------------
343 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
344 *-----------------------------------------------------------------------
347 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
349 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
350 #undef CONFIG_IDE_LED /* LED for ide not supported */
351 #undef CONFIG_IDE_RESET /* reset for ide not supported */
353 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
354 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
356 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
358 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
360 /* Offset for data I/O */
361 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
363 /* Offset for normal register accesses */
364 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
366 /* Offset for alternate registers */
367 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
369 /*-----------------------------------------------------------------------
371 *-----------------------------------------------------------------------
374 #define CONFIG_SYS_DER 0
377 * Init Memory Controller:
379 * BR0/1 and OR0/1 (FLASH)
382 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
383 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
385 /* used to re-map FLASH both when starting from SRAM or FLASH:
386 * restrict access enough to keep SRAM working (if any)
387 * but not too much to meddle with FLASH accesses
389 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
390 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
393 * FLASH timing: Default value of OR0 after reset
395 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
396 OR_SCY_6_CLK | OR_TRLX)
398 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
399 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
400 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
402 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
403 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
404 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
407 * BR2/3 and OR2/3 (SDRAM)
410 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
411 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
412 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
414 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
415 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
417 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
418 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
420 #ifndef CONFIG_CAN_DRIVER
421 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
422 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
423 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
424 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
425 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
426 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
427 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
428 BR_PS_8 | BR_MS_UPMB | BR_V )
429 #endif /* CONFIG_CAN_DRIVER */
432 * 4096 Rows from SDRAM example configuration
433 * 1000 factor s -> ms
434 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
435 * 4 Number of refresh cycles per period
436 * 64 Refresh cycle in ms per number of rows
438 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
441 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
443 * CPUclock(MHz) * 31.2
444 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
445 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
447 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
448 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
449 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
450 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
452 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
453 * be met also in the default configuration, i.e. if environment variable
454 * 'cpuclk' is not set.
456 #define CONFIG_SYS_MAMR_PTA 128
459 * Memory Periodic Timer Prescaler Register (MPTPR) values.
461 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
462 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
463 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
464 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
467 * MAMR settings for SDRAM
471 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
472 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
475 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
476 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
477 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
478 /* 10 column SDRAM */
479 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
480 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
481 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
484 * Internal Definitions
488 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
489 #define BOOTFLAG_WARM 0x02 /* Software reboot */
492 * Network configuration
494 #define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
495 #define CONFIG_FEC_ENET /* enable ethernet on FEC */
496 #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
497 #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
499 #if defined(CONFIG_CMD_MII)
500 #define CONFIG_SYS_DISCOVER_PHY
501 #define CONFIG_MII_INIT 1
504 #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
505 switching to another netwok (if the
506 tried network is unreachable) */
508 #define CONFIG_ETHPRIME "SCC ETHERNET"
510 #endif /* __CONFIG_H */