2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37 #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
39 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
40 #define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
41 #define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
42 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
43 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */
46 #undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */
47 /* (function measure_gclk() */
49 #ifdef CFG_MEASURE_CPUCLK
50 #define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
53 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
55 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
57 #define CONFIG_BOOTCOUNT_LIMIT
59 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61 #define CONFIG_BOARD_TYPES 1 /* support board types */
63 #define CONFIG_PREBOOT "echo;" \
64 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
67 #undef CONFIG_BOOTARGS
69 #define CONFIG_EXTRA_ENV_SETTINGS \
71 "nfsargs=setenv bootargs root=/dev/nfs rw " \
72 "nfsroot=${serverip}:${rootpath}\0" \
73 "ramargs=setenv bootargs root=/dev/ram rw\0" \
74 "addip=setenv bootargs ${bootargs} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
76 ":${hostname}:${netdev}:off panic=1\0" \
77 "flash_nfs=run nfsargs addip;" \
78 "bootm ${kernel_addr}\0" \
79 "flash_self=run ramargs addip;" \
80 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
82 "rootpath=/opt/eldk/ppc_8xx\0" \
83 "bootfile=/tftpboot/TQM866M/uImage\0" \
84 "fdt_addr=40080000\0" \
85 "kernel_addr=400A0000\0" \
86 "ramdisk_addr=40280000\0" \
88 #define CONFIG_BOOTCOMMAND "run flash_self"
90 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
91 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
93 #undef CONFIG_WATCHDOG /* watchdog disabled */
95 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
97 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
99 /* enable I2C and select the hardware/software driver */
100 #undef CONFIG_HARD_I2C /* I2C with hardware support */
101 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
103 #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
104 #define CFG_I2C_SLAVE 0xFE
106 #ifdef CONFIG_SOFT_I2C
108 * Software (bit-bang) I2C driver configuration
110 #define PB_SCL 0x00000020 /* PB 26 */
111 #define PB_SDA 0x00000010 /* PB 27 */
113 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
114 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
115 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
116 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
117 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
118 else immr->im_cpm.cp_pbdat &= ~PB_SDA
119 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
120 else immr->im_cpm.cp_pbdat &= ~PB_SCL
121 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
122 #endif /* CONFIG_SOFT_I2C */
124 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
125 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
126 #define CFG_EEPROM_PAGE_WRITE_BITS 4
127 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
132 #define CONFIG_BOOTP_SUBNETMASK
133 #define CONFIG_BOOTP_GATEWAY
134 #define CONFIG_BOOTP_HOSTNAME
135 #define CONFIG_BOOTP_BOOTPATH
136 #define CONFIG_BOOTP_BOOTFILESIZE
139 #define CONFIG_MAC_PARTITION
140 #define CONFIG_DOS_PARTITION
142 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
144 #define CONFIG_TIMESTAMP /* but print image timestmps */
148 * Command line configuration.
150 #include <config_cmd_default.h>
152 #define CONFIG_CMD_ASKENV
153 #define CONFIG_CMD_DHCP
154 #define CONFIG_CMD_EEPROM
155 #define CONFIG_CMD_I2C
156 #define CONFIG_CMD_IDE
157 #define CONFIG_CMD_NFS
161 * Miscellaneous configurable options
163 #define CFG_LONGHELP /* undef to save memory */
164 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
166 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
167 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
168 #ifdef CFG_HUSH_PARSER
169 #define CFG_PROMPT_HUSH_PS2 "> "
172 #if defined(CONFIG_CMD_KGDB)
173 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
175 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
177 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
178 #define CFG_MAXARGS 16 /* max number of command args */
179 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
181 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
182 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
184 #define CFG_LOAD_ADDR 0x100000 /* default load address */
186 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
188 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
191 * Low Level Configuration Settings
192 * (address mappings, register initial values, etc.)
193 * You should know what you are doing if you make changes here.
195 /*-----------------------------------------------------------------------
196 * Internal Memory Mapped Register
198 #define CFG_IMMR 0xFFF00000
200 /*-----------------------------------------------------------------------
201 * Definitions for initial stack pointer and data area (in DPRAM)
203 #define CFG_INIT_RAM_ADDR CFG_IMMR
204 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
205 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
206 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
207 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
209 /*-----------------------------------------------------------------------
210 * Start addresses for the final memory configuration
211 * (Set up by the startup code)
212 * Please note that CFG_SDRAM_BASE _must_ start at 0
214 #define CFG_SDRAM_BASE 0x00000000
215 #define CFG_FLASH_BASE 0x40000000
216 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
217 #define CFG_MONITOR_BASE CFG_FLASH_BASE
218 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
221 * For booting Linux, the board info and command line data
222 * have to be in the first 8 MB of memory, since this is
223 * the maximum mapped by the Linux kernel during initialization.
225 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
227 /*-----------------------------------------------------------------------
230 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
231 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
233 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
234 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
236 #define CFG_ENV_IS_IN_FLASH 1
237 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
238 #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
239 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
241 /* Address and size of Redundant Environment Sector */
242 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
243 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
245 #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
247 /*-----------------------------------------------------------------------
248 * Hardware Information Block
250 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
251 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
252 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
254 /*-----------------------------------------------------------------------
255 * Cache Configuration
257 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
258 #if defined(CONFIG_CMD_KGDB)
259 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
262 /*-----------------------------------------------------------------------
263 * SYPCR - System Protection Control 11-9
264 * SYPCR can only be written once after reset!
265 *-----------------------------------------------------------------------
266 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
268 #if defined(CONFIG_WATCHDOG)
269 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
270 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
272 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
275 /*-----------------------------------------------------------------------
276 * SIUMCR - SIU Module Configuration 11-6
277 *-----------------------------------------------------------------------
278 * PCMCIA config., multi-function pin tri-state
280 #ifndef CONFIG_CAN_DRIVER
281 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
282 #else /* we must activate GPL5 in the SIUMCR for CAN */
283 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
284 #endif /* CONFIG_CAN_DRIVER */
286 /*-----------------------------------------------------------------------
287 * TBSCR - Time Base Status and Control 11-26
288 *-----------------------------------------------------------------------
289 * Clear Reference Interrupt Status, Timebase freezing enabled
291 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
293 /*-----------------------------------------------------------------------
294 * PISCR - Periodic Interrupt Status and Control 11-31
295 *-----------------------------------------------------------------------
296 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
298 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
300 /*-----------------------------------------------------------------------
301 * SCCR - System Clock and reset Control Register 15-27
302 *-----------------------------------------------------------------------
303 * Set clock output, timebase and RTC source and divider,
304 * power management and some other internal clocks
306 #define SCCR_MASK SCCR_EBDF11
307 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
308 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
311 /*-----------------------------------------------------------------------
313 *-----------------------------------------------------------------------
316 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
317 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
318 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
319 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
320 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
321 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
322 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
323 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
325 /*-----------------------------------------------------------------------
326 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
327 *-----------------------------------------------------------------------
330 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
332 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
333 #undef CONFIG_IDE_LED /* LED for ide not supported */
334 #undef CONFIG_IDE_RESET /* reset for ide not supported */
336 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
337 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
339 #define CFG_ATA_IDE0_OFFSET 0x0000
341 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
343 /* Offset for data I/O */
344 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
346 /* Offset for normal register accesses */
347 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
349 /* Offset for alternate registers */
350 #define CFG_ATA_ALT_OFFSET 0x0100
352 /*-----------------------------------------------------------------------
354 *-----------------------------------------------------------------------
360 * Init Memory Controller:
362 * BR0/1 and OR0/1 (FLASH)
365 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
366 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
368 /* used to re-map FLASH both when starting from SRAM or FLASH:
369 * restrict access enough to keep SRAM working (if any)
370 * but not too much to meddle with FLASH accesses
372 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
373 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
376 * FLASH timing: Default value of OR0 after reset
378 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
379 OR_SCY_15_CLK | OR_TRLX)
381 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
382 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
383 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
385 #define CFG_OR1_REMAP CFG_OR0_REMAP
386 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
387 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
390 * BR2/3 and OR2/3 (SDRAM)
393 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
394 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
395 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
397 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
398 #define CFG_OR_TIMING_SDRAM 0x00000A00
400 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
401 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
403 #ifndef CONFIG_CAN_DRIVER
404 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
405 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
406 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
407 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
408 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
409 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
410 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
411 BR_PS_8 | BR_MS_UPMB | BR_V )
412 #endif /* CONFIG_CAN_DRIVER */
415 * 4096 Rows from SDRAM example configuration
416 * 1000 factor s -> ms
417 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
418 * 4 Number of refresh cycles per period
419 * 64 Refresh cycle in ms per number of rows
421 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
424 * Memory Periodic Timer Prescaler
425 * Periodic timer for refresh, start with refresh rate for 40 MHz clock
426 * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
428 #define CFG_MAMR_PTA 39
431 * For 16 MBit, refresh rates could be 31.3 us
432 * (= 64 ms / 2K = 125 / quad bursts).
433 * For a simpler initialization, 15.6 us is used instead.
435 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
436 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
438 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
439 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
441 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
442 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
443 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
446 * MAMR settings for SDRAM
450 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
451 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
452 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
454 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
455 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
456 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
457 /* 10 column SDRAM */
458 #define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
459 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
460 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
463 * Internal Definitions
467 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
468 #define BOOTFLAG_WARM 0x02 /* Software reboot */
470 #define CONFIG_SCC1_ENET
471 #define CONFIG_FEC_ENET
472 #define CONFIG_ETHPRIME "SCC ETHERNET"
474 #endif /* __CONFIG_H */