3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * TQM85xx (8560/40/55/41) board configuration file
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE 1 /* BOOKE */
38 #define CONFIG_E500 1 /* BOOKE e500 family */
39 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
42 #define CONFIG_TSEC_ENET /* tsec ethernet support */
44 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
47 * Only MPC8540 doesn't have CPM module
49 #ifndef CONFIG_MPC8540
50 #define CONFIG_CPM2 1 /* has CPM2 */
53 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
55 #undef CONFIG_CAN_DRIVER /* CAN Driver support */
60 * Two valid values are:
64 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
65 * is likely the desired value here, so that is now the default.
66 * The board, however, can run at 66MHz. In any event, this value
67 * must match the settings of some switches. Details can be found
68 * in the README.mpc85xxads.
71 #ifndef CONFIG_SYS_CLK_FREQ
72 #define CONFIG_SYS_CLK_FREQ 33333333
76 * These can be toggled for performance analysis, otherwise use default.
78 #define CONFIG_L2_CACHE /* toggle L2 cache */
79 #define CONFIG_BTB /* toggle branch predition */
80 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
82 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
84 #undef CFG_DRAM_TEST /* memory test, takes time */
85 #define CFG_MEMTEST_START 0x00000000
86 #define CFG_MEMTEST_END 0x10000000
89 * Base addresses -- Note these are effective addresses where the
90 * actual resources get mapped (not physical addresses)
92 #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
93 #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
94 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
95 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
100 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
101 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
103 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
104 /* TQM8540 & 8560 need DLL-override */
105 #define CONFIG_DDR_DLL /* DLL fix needed */
106 #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
107 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
109 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
110 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
111 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */
114 * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
115 * series while new boards have 'N' type Flashes from the S29GLxxxN
116 * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
118 #undef CONFIG_TQM_FLASH_N_TYPE
121 * Flash on the Local Bus
123 #define CFG_FLASH0 0xFC000000
124 #define CFG_FLASH1 0xF8000000
125 #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
127 #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
128 #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
130 #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
131 #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
132 #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
133 #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
135 #define CFG_FLASH_CFI /* flash is CFI compat. */
136 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
137 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
138 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
140 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
141 #define CFG_MAX_FLASH_SECT 512 /* sectors per device */
142 #undef CFG_FLASH_CHECKSUM
143 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
144 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
146 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
148 #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
149 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
150 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
151 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
153 #define CONFIG_L1_INIT_RAM
154 #define CFG_INIT_RAM_LOCK 1
155 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
156 #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
158 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
159 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
160 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
162 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */
163 #define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
166 #if defined(CONFIG_TQM8560)
168 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
169 #undef CONFIG_CONS_NONE /* define if console on something else */
170 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
172 #else /* !CONFIG_TQM8560 */
174 #define CONFIG_CONS_INDEX 1
175 #undef CONFIG_SERIAL_SOFTWARE_FIFO
177 #define CFG_NS16550_SERIAL
178 #define CFG_NS16550_REG_SIZE 1
179 #define CFG_NS16550_CLK get_bus_freq(0)
181 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
182 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
185 #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
186 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
187 #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
188 #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
189 #define CONFIG_BOARD_EARLY_INIT_R 1
191 #endif /* CONFIG_TQM8560 */
193 #define CONFIG_BAUDRATE 115200
195 #define CFG_BAUDRATE_TABLE \
196 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
198 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
199 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
200 #ifdef CFG_HUSH_PARSER
201 #define CFG_PROMPT_HUSH_PS2 "> "
204 /* pass open firmware flat tree */
205 #define CONFIG_OF_LIBFDT 1
206 #define CONFIG_OF_BOARD_SETUP 1
207 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
210 #ifdef CONFIG_CAN_DRIVER
211 #define CFG_CAN_BASE 0xE3000000 /* CAN base address */
212 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
213 #define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI)
214 #define CFG_BR2_CAN ((CFG_CAN_BASE & BR_BA) | \
215 BR_PS_8 | BR_MS_UPMC | BR_V)
216 #endif /* CONFIG_CAN_DRIVER */
221 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
222 #define CONFIG_HARD_I2C /* I2C with hardware support */
223 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
224 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
225 #define CFG_I2C_SLAVE 0x7F
226 #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
227 #define CFG_I2C_OFFSET 0x3000
230 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
231 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
235 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
237 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
238 #define CFG_I2C_EEPROM_ADDR_LEN 2
239 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
240 #define CFG_EEPROM_PAGE_WRITE_ENABLE
241 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
242 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
244 /* I2C SYSMON (LM75) */
245 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
246 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
247 #define CFG_DTT_MAX_TEMP 70
248 #define CFG_DTT_LOW_TEMP -30
249 #define CFG_DTT_HYSTERESIS 3
252 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
253 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
254 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
258 * Addresses are mapped 1-1.
260 #define CFG_PCI1_MEM_BASE 0x80000000
261 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
262 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
263 #define CFG_PCI1_IO_BASE 0xe2000000
264 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
265 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
267 #if defined(CONFIG_PCI)
269 #define CONFIG_PCI_PNP /* do pci plug-and-play */
271 #define CONFIG_EEPRO100
274 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
275 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
277 #endif /* CONFIG_PCI */
279 #define CONFIG_NET_MULTI 1
281 #define CONFIG_MII 1 /* MII PHY management */
282 #define CONFIG_TSEC1 1
283 #define CONFIG_TSEC1_NAME "TSEC0"
284 #define CONFIG_TSEC2 1
285 #define CONFIG_TSEC2_NAME "TSEC1"
286 #define TSEC1_PHY_ADDR 2
287 #define TSEC2_PHY_ADDR 1
288 #define TSEC1_PHYIDX 0
289 #define TSEC2_PHYIDX 0
290 #define TSEC1_FLAGS TSEC_GIGABIT
291 #define TSEC2_FLAGS TSEC_GIGABIT
292 #define FEC_PHY_ADDR 3
295 #define CONFIG_HAS_ETH0
296 #define CONFIG_HAS_ETH1
297 #define CONFIG_HAS_ETH2
299 /* Options are TSEC[0-1], FEC */
300 #define CONFIG_ETHPRIME "TSEC0"
302 #if defined(CONFIG_TQM8540)
304 * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
305 * The FEC port is connected on the same signals as the FCC3 port
306 * of the TQM8560 to the baseboard (STK85xx Starterkit).
308 * On the STK85xx Starterkit the X47/X50 jumper has to be set to
309 * a - d (X50.2 - 3) to enable the FEC port.
311 #define CONFIG_MPC85XX_FEC 1
312 #define CONFIG_MPC85XX_FEC_NAME "FEC"
315 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
317 * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
318 * can be used at once, since only one FCC port is available on the STK85xx
321 * To use this port you have to configure U-Boot to use the FCC port 1...2
322 * and set the X47/X50 jumper to:
323 * FCC1: a - b (X47.2 - X50.2)
324 * FCC2: a - c (X50.2 - 1)
326 #define CONFIG_ETHER_ON_FCC
327 #define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
330 #if defined(CONFIG_TQM8560)
332 * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
333 * can be used at once, since only one FCC port is available on the STK85xx
336 * To use this port you have to configure U-Boot to use the FCC port 1...3
337 * and set the X47/X50 jumper to:
338 * FCC1: a - b (X47.2 - X50.2)
339 * FCC2: a - c (X50.2 - 1)
340 * FCC3: a - d (X50.2 - 3)
342 #define CONFIG_ETHER_ON_FCC
343 #define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
346 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
347 #define CONFIG_ETHER_ON_FCC1
348 #define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
350 #define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
351 #define CFG_CPMFCR_RAMTYPE 0
352 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
355 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
356 #define CONFIG_ETHER_ON_FCC2
357 #define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
359 #define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
360 #define CFG_CPMFCR_RAMTYPE 0
361 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
364 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
365 #define CONFIG_ETHER_ON_FCC3
366 #define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
368 #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
369 #define CFG_CPMFCR_RAMTYPE 0
370 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
376 #define CFG_ENV_IS_IN_FLASH 1
378 #ifdef CONFIG_TQM_FLASH_N_TYPE
379 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
380 #else /* !CONFIG_TQM_FLASH_N_TYPE */
381 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
382 #endif /* CONFIG_TQM_FLASH_N_TYPE */
383 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
384 #define CFG_ENV_SIZE 0x2000
385 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
386 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
388 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
389 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
391 #define CONFIG_TIMESTAMP /* Print image info with ts */
396 #define CONFIG_BOOTP_BOOTFILESIZE
397 #define CONFIG_BOOTP_BOOTPATH
398 #define CONFIG_BOOTP_GATEWAY
399 #define CONFIG_BOOTP_HOSTNAME
402 * Command line configuration.
404 #include <config_cmd_default.h>
406 #define CONFIG_CMD_PING
407 #define CONFIG_CMD_I2C
408 #define CONFIG_CMD_DHCP
409 #define CONFIG_CMD_NFS
410 #define CONFIG_CMD_SNTP
411 #define CONFIG_CMD_DATE
412 #define CONFIG_CMD_EEPROM
413 #define CONFIG_CMD_DTT
414 #define CONFIG_CMD_MII
416 #if defined(CONFIG_PCI)
417 #define CONFIG_CMD_PCI
420 #undef CONFIG_WATCHDOG /* watchdog disabled */
423 * Miscellaneous configurable options
425 #define CFG_LONGHELP /* undef to save memory */
426 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
427 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
429 #if defined(CONFIG_CMD_KGDB)
430 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
432 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
435 #define CFG_PBSIZE (CFG_CBSIZE + \
436 sizeof(CFG_PROMPT) + 16) /* Print Buf Size */
437 #define CFG_MAXARGS 16 /* max number of command args */
438 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
439 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
442 * For booting Linux, the board info and command line data
443 * have to be in the first 8 MB of memory, since this is
444 * the maximum mapped by the Linux kernel during initialization.
446 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
449 * Internal Definitions
453 #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
454 #define BOOTFLAG_WARM 0x02 /* Software reboot */
456 #if defined(CONFIG_CMD_KGDB)
457 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
458 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
461 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
463 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
465 #define CONFIG_PREBOOT "echo;" \
466 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
469 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
473 * Setup some board specific values for the default environment variables
476 #define CFG_ENV_CONSDEV "consdev=ttyCPM0\0"
478 #define CFG_ENV_CONSDEV "consdev=ttyS0\0"
480 #define CFG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
481 MK_STR(CONFIG_HOSTNAME)".dtb\0"
482 #define CFG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
483 #define CFG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
484 "uboot_addr="MK_STR(TEXT_BASE)"\0"
486 #define CONFIG_EXTRA_ENV_SETTINGS \
491 "nfsargs=setenv bootargs root=/dev/nfs rw " \
492 "nfsroot=$serverip:$rootpath\0" \
493 "ramargs=setenv bootargs root=/dev/ram rw\0" \
494 "addip=setenv bootargs $bootargs " \
495 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
496 ":$hostname:$netdev:off panic=1\0" \
497 "addcons=setenv bootargs $bootargs " \
498 "console=$consdev,$baudrate\0" \
499 "flash_nfs=run nfsargs addip addcons;" \
500 "bootm $kernel_addr - $fdt_addr\0" \
501 "flash_self=run ramargs addip addcons;" \
502 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
503 "net_nfs=tftp $kernel_addr_r $bootfile;" \
504 "tftp $fdt_addr_r $fdt_file;" \
505 "run nfsargs addip addcons;" \
506 "bootm $kernel_addr_r - $fdt_addr_r\0" \
507 "rootpath=/opt/eldk/ppc_85xx\0" \
508 "fdt_addr_r=900000\0" \
509 "kernel_addr_r=1000000\0" \
510 "fdt_addr=ffec0000\0" \
511 "kernel_addr=ffd00000\0" \
512 "ramdisk_addr=ff800000\0" \
514 "load=tftp 100000 $uboot\0" \
515 "update=protect off $uboot_addr +$filesize;" \
516 "erase $uboot_addr +$filesize;" \
517 "cp.b 100000 $uboot_addr $filesize;" \
518 "setenv filesize;saveenv\0" \
519 "upd=run load update\0" \
521 #define CONFIG_BOOTCOMMAND "run flash_self"
523 #endif /* __CONFIG_H */