3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * TQM85xx (8560/40/55/41) board configuration file
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE 1 /* BOOKE */
38 #define CONFIG_E500 1 /* BOOKE e500 family */
39 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
42 #define CONFIG_TSEC_ENET /* tsec ethernet support */
44 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
47 * Only MPC8540 doesn't have CPM module
49 #ifndef CONFIG_MPC8540
50 #define CONFIG_CPM2 1 /* has CPM2 */
53 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
58 * Two valid values are:
62 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
63 * is likely the desired value here, so that is now the default.
64 * The board, however, can run at 66MHz. In any event, this value
65 * must match the settings of some switches. Details can be found
66 * in the README.mpc85xxads.
69 #ifndef CONFIG_SYS_CLK_FREQ
70 #define CONFIG_SYS_CLK_FREQ 33333333
74 * These can be toggled for performance analysis, otherwise use default.
76 #define CONFIG_L2_CACHE /* toggle L2 cache */
77 #define CONFIG_BTB /* toggle branch predition */
78 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
80 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
82 #undef CFG_DRAM_TEST /* memory test, takes time */
83 #define CFG_MEMTEST_START 0x00000000
84 #define CFG_MEMTEST_END 0x10000000
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
90 #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
91 #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
92 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
93 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
98 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
99 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
101 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
102 /* TQM8540 & 8560 need DLL-override */
103 #define CONFIG_DDR_DLL /* DLL fix needed */
104 #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
105 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
107 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
108 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
109 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */
112 * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
113 * series while new boards have 'N' type Flashes from the S29GLxxxN
114 * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
116 #undef CONFIG_TQM_FLASH_N_TYPE
119 * Flash on the Local Bus
121 #define CFG_FLASH0 0xFC000000
122 #define CFG_FLASH1 0xF8000000
123 #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
125 #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
126 #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
128 #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
129 #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
130 #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
131 #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
133 #define CFG_FLASH_CFI /* flash is CFI compat. */
134 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
135 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
136 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
138 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
139 #define CFG_MAX_FLASH_SECT 512 /* sectors per device */
140 #undef CFG_FLASH_CHECKSUM
141 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
142 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
146 #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
147 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
148 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
149 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
151 #define CONFIG_L1_INIT_RAM
152 #define CFG_INIT_RAM_LOCK 1
153 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
154 #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
156 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
157 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
158 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
160 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */
161 #define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
164 #if defined(CONFIG_TQM8560)
166 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
167 #undef CONFIG_CONS_NONE /* define if console on something else */
168 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
170 #else /* !CONFIG_TQM8560 */
172 #define CONFIG_CONS_INDEX 1
173 #undef CONFIG_SERIAL_SOFTWARE_FIFO
175 #define CFG_NS16550_SERIAL
176 #define CFG_NS16550_REG_SIZE 1
177 #define CFG_NS16550_CLK get_bus_freq(0)
179 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
180 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
183 #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
184 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
185 #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
186 #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
187 #define CONFIG_BOARD_EARLY_INIT_R 1
189 #endif /* CONFIG_TQM8560 */
191 #define CONFIG_BAUDRATE 115200
193 #define CFG_BAUDRATE_TABLE \
194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
196 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
197 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
198 #ifdef CFG_HUSH_PARSER
199 #define CFG_PROMPT_HUSH_PS2 "> "
205 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
206 #define CONFIG_HARD_I2C /* I2C with hardware support */
207 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
208 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
209 #define CFG_I2C_SLAVE 0x7F
210 #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
211 #define CFG_I2C_OFFSET 0x3000
214 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
215 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
219 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
221 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
222 #define CFG_I2C_EEPROM_ADDR_LEN 2
223 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
224 #define CFG_EEPROM_PAGE_WRITE_ENABLE
225 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
226 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
228 /* I2C SYSMON (LM75) */
229 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
230 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
231 #define CFG_DTT_MAX_TEMP 70
232 #define CFG_DTT_LOW_TEMP -30
233 #define CFG_DTT_HYSTERESIS 3
236 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
237 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
238 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
242 * Addresses are mapped 1-1.
244 #define CFG_PCI1_MEM_BASE 0x80000000
245 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
246 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
247 #define CFG_PCI1_IO_BASE 0xe2000000
248 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
249 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
251 #if defined(CONFIG_PCI)
253 #define CONFIG_PCI_PNP /* do pci plug-and-play */
255 #define CONFIG_EEPRO100
258 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
259 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
261 #endif /* CONFIG_PCI */
263 #define CONFIG_NET_MULTI 1
265 #define CONFIG_MII 1 /* MII PHY management */
266 #define CONFIG_TSEC1 1
267 #define CONFIG_TSEC1_NAME "TSEC0"
268 #define CONFIG_TSEC2 1
269 #define CONFIG_TSEC2_NAME "TSEC1"
270 #define TSEC1_PHY_ADDR 2
271 #define TSEC2_PHY_ADDR 1
272 #define TSEC1_PHYIDX 0
273 #define TSEC2_PHYIDX 0
274 #define TSEC1_FLAGS TSEC_GIGABIT
275 #define TSEC2_FLAGS TSEC_GIGABIT
276 #define FEC_PHY_ADDR 3
279 #define CONFIG_HAS_ETH0
280 #define CONFIG_HAS_ETH1
281 #define CONFIG_HAS_ETH2
283 /* Options are TSEC[0-1], FEC */
284 #define CONFIG_ETHPRIME "TSEC0"
286 #if defined(CONFIG_TQM8540)
288 * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
289 * The FEC port is connected on the same signals as the FCC3 port
290 * of the TQM8560 to the baseboard (STK85xx Starterkit).
292 * On the STK85xx Starterkit the X47/X50 jumper has to be set to
293 * a - d (X50.2 - 3) to enable the FEC port.
295 #define CONFIG_MPC85XX_FEC 1
296 #define CONFIG_MPC85XX_FEC_NAME "FEC"
299 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
301 * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
302 * can be used at once, since only one FCC port is available on the STK85xx
305 * To use this port you have to configure U-Boot to use the FCC port 1...2
306 * and set the X47/X50 jumper to:
307 * FCC1: a - b (X47.2 - X50.2)
308 * FCC2: a - c (X50.2 - 1)
310 #define CONFIG_ETHER_ON_FCC
311 #define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
314 #if defined(CONFIG_TQM8560)
316 * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
317 * can be used at once, since only one FCC port is available on the STK85xx
320 * To use this port you have to configure U-Boot to use the FCC port 1...3
321 * and set the X47/X50 jumper to:
322 * FCC1: a - b (X47.2 - X50.2)
323 * FCC2: a - c (X50.2 - 1)
324 * FCC3: a - d (X50.2 - 3)
326 #define CONFIG_ETHER_ON_FCC
327 #define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
330 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
331 #define CONFIG_ETHER_ON_FCC1
332 #define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
334 #define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
335 #define CFG_CPMFCR_RAMTYPE 0
336 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
339 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
340 #define CONFIG_ETHER_ON_FCC2
341 #define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
343 #define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
344 #define CFG_CPMFCR_RAMTYPE 0
345 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
348 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
349 #define CONFIG_ETHER_ON_FCC3
350 #define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
352 #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
353 #define CFG_CPMFCR_RAMTYPE 0
354 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
360 #define CFG_ENV_IS_IN_FLASH 1
362 #ifdef CONFIG_TQM_FLASH_N_TYPE
363 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
364 #else /* !CONFIG_TQM_FLASH_N_TYPE */
365 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
366 #endif /* CONFIG_TQM_FLASH_N_TYPE */
367 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
368 #define CFG_ENV_SIZE 0x2000
369 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
370 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
372 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
373 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
375 #define CONFIG_TIMESTAMP /* Print image info with ts */
380 #define CONFIG_BOOTP_BOOTFILESIZE
381 #define CONFIG_BOOTP_BOOTPATH
382 #define CONFIG_BOOTP_GATEWAY
383 #define CONFIG_BOOTP_HOSTNAME
386 * Command line configuration.
388 #include <config_cmd_default.h>
390 #define CONFIG_CMD_PING
391 #define CONFIG_CMD_I2C
392 #define CONFIG_CMD_DHCP
393 #define CONFIG_CMD_NFS
394 #define CONFIG_CMD_SNTP
395 #define CONFIG_CMD_DATE
396 #define CONFIG_CMD_EEPROM
397 #define CONFIG_CMD_DTT
398 #define CONFIG_CMD_MII
400 #if defined(CONFIG_PCI)
401 #define CONFIG_CMD_PCI
404 #undef CONFIG_WATCHDOG /* watchdog disabled */
407 * Miscellaneous configurable options
409 #define CFG_LONGHELP /* undef to save memory */
410 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
411 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
413 #if defined(CONFIG_CMD_KGDB)
414 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
416 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
419 #define CFG_PBSIZE (CFG_CBSIZE + \
420 sizeof(CFG_PROMPT) + 16) /* Print Buf Size */
421 #define CFG_MAXARGS 16 /* max number of command args */
422 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
423 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
426 * For booting Linux, the board info and command line data
427 * have to be in the first 8 MB of memory, since this is
428 * the maximum mapped by the Linux kernel during initialization.
430 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
433 * Internal Definitions
437 #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
438 #define BOOTFLAG_WARM 0x02 /* Software reboot */
440 #if defined(CONFIG_CMD_KGDB)
441 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
442 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
445 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
447 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
449 #define CONFIG_PREBOOT "echo;" \
450 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
453 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
455 #define CONFIG_EXTRA_ENV_SETTINGS \
456 "bootfile="CFG_BOOTFILE_PATH"\0" \
459 "nfsargs=setenv bootargs root=/dev/nfs rw " \
460 "nfsroot=$serverip:$rootpath\0" \
461 "ramargs=setenv bootargs root=/dev/ram rw\0" \
462 "addip=setenv bootargs $bootargs " \
463 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
464 ":$hostname:$netdev:off panic=1\0" \
465 "addcons=setenv bootargs $bootargs " \
466 "console=$consdev,$baudrate\0" \
467 "flash_nfs=run nfsargs addip addcons;" \
468 "bootm $kernel_addr\0" \
469 "flash_self=run ramargs addip addcons;" \
470 "bootm $kernel_addr $ramdisk_addr\0" \
471 "net_nfs=tftp $loadaddr $bootfile;" \
472 "run nfsargs addip addcons;bootm\0" \
473 "rootpath=/opt/eldk/ppc_85xx\0" \
474 "kernel_addr=FE000000\0" \
475 "ramdisk_addr=FE180000\0" \
476 "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
477 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
478 "cp.b 100000 fffc0000 40000;" \
479 "setenv filesize;saveenv\0" \
480 "upd=run load update\0" \
482 #define CONFIG_BOOTCOMMAND "run flash_self"
484 #endif /* __CONFIG_H */