Merge branch 'master' of git://git.denx.de/u-boot-spi
[oweals/u-boot.git] / include / configs / TQM834x.h
1 /*
2  * (C) Copyright 2005
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 /*
25  * TQM8349 board configuration file
26  */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 /*
32  * High Level Configuration Options
33  */
34 #define CONFIG_E300             1       /* E300 Family */
35 #define CONFIG_MPC83xx          1       /* MPC83xx family */
36 #define CONFIG_MPC834x          1       /* MPC834x specific */
37 #define CONFIG_MPC8349          1       /* MPC8349 specific */
38 #define CONFIG_TQM834X          1       /* TQM834X board specific */
39
40 #define CONFIG_SYS_TEXT_BASE    0x80000000
41
42 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
43 #define CONFIG_SYS_IMMR         0xff400000
44
45 /* System clock. Primary input clock when in PCI host mode */
46 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
47
48 /*
49  * Local Bus LCRR
50  *    LCRR:  DLL bypass, Clock divider is 8
51  *
52  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
53  *
54  * External Local Bus rate is
55  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
56  */
57 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
58 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
59
60 /* board pre init: do not call, nothing to do */
61 #undef CONFIG_BOARD_EARLY_INIT_F
62
63 /* detect the number of flash banks */
64 #define CONFIG_BOARD_EARLY_INIT_R
65
66 /*
67  * DDR Setup
68  */
69                                 /* DDR is system memory*/
70 #define CONFIG_SYS_DDR_BASE     0x00000000
71 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
72 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
73 #define DDR_CASLAT_25           /* CASLAT set to 2.5 */
74 #undef CONFIG_DDR_ECC           /* only for ECC DDR module */
75 #undef CONFIG_SPD_EEPROM        /* do not use SPD EEPROM for DDR setup */
76
77 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
78 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
79 #define CONFIG_SYS_MEMTEST_END          0x00100000
80
81 /*
82  * FLASH on the Local Bus
83  */
84 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
85 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
86 #undef CONFIG_SYS_FLASH_CHECKSUM
87 #define CONFIG_SYS_FLASH_BASE           0x80000000      /* start of FLASH   */
88 #define CONFIG_SYS_FLASH_SIZE           8               /* FLASH size in MB */
89 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sectors */
90 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
91
92 /*
93  * FLASH bank number detection
94  */
95
96 /*
97  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
98  * Flash banks has to be determined at runtime and stored in a gloabl variable
99  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
100  * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
101  * flash_info, and should be made sufficiently large to accomodate the number
102  * of banks that might actually be detected.  Since most (all?) Flash related
103  * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
104  * the board, it is defined as tqm834x_num_flash_banks.
105  */
106 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       2
107
108 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
109
110 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
111 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA) \
112                                 | BR_MS_GPCM \
113                                 | BR_PS_32 \
114                                 | BR_V)
115
116 /* FLASH timing (0x0000_0c54) */
117 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_GPCM_CSNT \
118                                         | OR_GPCM_ACS_DIV4 \
119                                         | OR_GPCM_SCY_5 \
120                                         | OR_GPCM_TRLX)
121
122 #define CONFIG_SYS_PRELIM_OR_AM         OR_AM_1GB /* OR addr mask: 1 GiB */
123
124 #define CONFIG_SYS_OR0_PRELIM           (CONFIG_SYS_PRELIM_OR_AM  \
125                                         | CONFIG_SYS_OR_TIMING_FLASH)
126
127 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_1GB)
128
129                                         /* Window base at flash base */
130 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
131
132 /* disable remaining mappings */
133 #define CONFIG_SYS_BR1_PRELIM           0x00000000
134 #define CONFIG_SYS_OR1_PRELIM           0x00000000
135 #define CONFIG_SYS_LBLAWBAR1_PRELIM     0x00000000
136 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x00000000
137
138 #define CONFIG_SYS_BR2_PRELIM           0x00000000
139 #define CONFIG_SYS_OR2_PRELIM           0x00000000
140 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0x00000000
141 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x00000000
142
143 #define CONFIG_SYS_BR3_PRELIM           0x00000000
144 #define CONFIG_SYS_OR3_PRELIM           0x00000000
145 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0x00000000
146 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x00000000
147
148 /*
149  * Monitor config
150  */
151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
152
153 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
154 # define CONFIG_SYS_RAMBOOT
155 #else
156 # undef  CONFIG_SYS_RAMBOOT
157 #endif
158
159 #define CONFIG_SYS_INIT_RAM_LOCK        1
160 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000 /* Initial RAM address */
161 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
162
163 #define CONFIG_SYS_GBL_DATA_OFFSET      \
164                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
165 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
166
167                                 /* Reserve 384 kB = 3 sect. for Mon */
168 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)
169                                 /* Reserve 512 kB for malloc */
170 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)
171
172 /*
173  * Serial Port
174  */
175 #define CONFIG_CONS_INDEX       1
176 #define CONFIG_SYS_NS16550
177 #define CONFIG_SYS_NS16550_SERIAL
178 #define CONFIG_SYS_NS16550_REG_SIZE     1
179 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
180
181 #define CONFIG_SYS_BAUDRATE_TABLE  \
182                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
183
184 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
185 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
186
187 /*
188  * I2C
189  */
190 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
191 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
192 #define CONFIG_FSL_I2C
193 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed: 400KHz */
194 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* slave address */
195 #define CONFIG_SYS_I2C_OFFSET           0x3000
196
197 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
198 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
199 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16 bit */
200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32 bytes/write */
201 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12      /* 10ms +/- 20% */
202 #define CONFIG_SYS_I2C_MULTI_EEPROMS            /* more than one eeprom */
203
204 /* I2C RTC */
205 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c */
206 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68 */
207
208 /* I2C SYSMON (LM75) */
209 #define CONFIG_DTT_LM75                 1       /* ON Semi's LM75 */
210 #define CONFIG_DTT_SENSORS              {0}     /* Sensor addresses */
211 #define CONFIG_SYS_DTT_MAX_TEMP         70
212 #define CONFIG_SYS_DTT_LOW_TEMP         -30
213 #define CONFIG_SYS_DTT_HYSTERESIS       3
214
215 /*
216  * TSEC
217  */
218 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
219 #define CONFIG_MII
220
221 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
222 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
223 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
224 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
225
226 #if defined(CONFIG_TSEC_ENET)
227
228 #define CONFIG_TSEC1            1
229 #define CONFIG_TSEC1_NAME       "TSEC0"
230 #define CONFIG_TSEC2            1
231 #define CONFIG_TSEC2_NAME       "TSEC1"
232 #define TSEC1_PHY_ADDR          2
233 #define TSEC2_PHY_ADDR          1
234 #define TSEC1_PHYIDX            0
235 #define TSEC2_PHYIDX            0
236 #define TSEC1_FLAGS             TSEC_GIGABIT
237 #define TSEC2_FLAGS             TSEC_GIGABIT
238
239 /* Options are: TSEC[0-1] */
240 #define CONFIG_ETHPRIME         "TSEC0"
241
242 #endif  /* CONFIG_TSEC_ENET */
243
244 /*
245  * General PCI
246  * Addresses are mapped 1-1.
247  */
248 #define CONFIG_PCI
249
250 #if defined(CONFIG_PCI)
251
252 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
253 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
254
255 /* PCI1 host bridge */
256 #define CONFIG_SYS_PCI1_MEM_BASE        0x90000000
257 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
258 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
259 #define CONFIG_SYS_PCI1_MMIO_BASE       \
260                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
261 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
262 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
263 #define CONFIG_SYS_PCI1_IO_BASE         0xe2000000
264 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
265 #define CONFIG_SYS_PCI1_IO_SIZE         0x1000000       /* 16M */
266
267 #undef CONFIG_EEPRO100
268 #define CONFIG_EEPRO100
269 #undef CONFIG_TULIP
270
271 #if !defined(CONFIG_PCI_PNP)
272         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
273         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_MEM_BASE
274         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
275 #endif
276
277 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          0x1957  /* Freescale */
278
279 #endif  /* CONFIG_PCI */
280
281 /*
282  * Environment
283  */
284 #define CONFIG_ENV_IS_IN_FLASH  1
285 #define CONFIG_ENV_ADDR         \
286                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
287 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env */
288 #define CONFIG_ENV_SIZE         0x8000  /*  32K max size */
289 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
290 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
291
292 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
293 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
294
295 /*
296  * BOOTP options
297  */
298 #define CONFIG_BOOTP_BOOTFILESIZE
299 #define CONFIG_BOOTP_BOOTPATH
300 #define CONFIG_BOOTP_GATEWAY
301 #define CONFIG_BOOTP_HOSTNAME
302
303
304 /*
305  * Command line configuration.
306  */
307 #include <config_cmd_default.h>
308
309 #define CONFIG_CMD_ASKENV
310 #define CONFIG_CMD_DATE
311 #define CONFIG_CMD_DHCP
312 #define CONFIG_CMD_DTT
313 #define CONFIG_CMD_EEPROM
314 #define CONFIG_CMD_I2C
315 #define CONFIG_CMD_NFS
316 #define CONFIG_CMD_JFFS2
317 #define CONFIG_CMD_MII
318 #define CONFIG_CMD_PING
319 #define CONFIG_CMD_REGINFO
320 #define CONFIG_CMD_SNTP
321
322 #if defined(CONFIG_PCI)
323     #define CONFIG_CMD_PCI
324 #endif
325
326 #if defined(CONFIG_SYS_RAMBOOT)
327     #undef CONFIG_CMD_SAVEENV
328     #undef CONFIG_CMD_LOADS
329 #endif
330
331 /*
332  * Miscellaneous configurable options
333  */
334 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
335 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
336 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
337
338 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
339 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
340
341 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser */
342
343 #if defined(CONFIG_CMD_KGDB)
344         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
345 #else
346         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
347 #endif
348
349                                 /* Print Buffer Size */
350 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
351 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
352                                 /* Boot Argument Buffer Size */
353 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
354 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
355
356 #undef CONFIG_WATCHDOG          /* watchdog disabled */
357
358 /* pass open firmware flat tree */
359 #define CONFIG_OF_LIBFDT        1
360 #define CONFIG_OF_BOARD_SETUP   1
361 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
362
363 /*
364  * For booting Linux, the board info and command line data
365  * have to be in the first 256 MB of memory, since this is
366  * the maximum mapped by the Linux kernel during initialization.
367  */
368                                 /* Initial Memory map for Linux */
369 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
370
371 #define CONFIG_SYS_HRCW_LOW (\
372         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
373         HRCWL_DDR_TO_SCB_CLK_1X1 |\
374         HRCWL_CSB_TO_CLKIN_4X1 |\
375         HRCWL_VCO_1X2 |\
376         HRCWL_CORE_TO_CSB_2X1)
377
378 #if defined(PCI_64BIT)
379 #define CONFIG_SYS_HRCW_HIGH (\
380         HRCWH_PCI_HOST |\
381         HRCWH_64_BIT_PCI |\
382         HRCWH_PCI1_ARBITER_ENABLE |\
383         HRCWH_PCI2_ARBITER_DISABLE |\
384         HRCWH_CORE_ENABLE |\
385         HRCWH_FROM_0X00000100 |\
386         HRCWH_BOOTSEQ_DISABLE |\
387         HRCWH_SW_WATCHDOG_DISABLE |\
388         HRCWH_ROM_LOC_LOCAL_16BIT |\
389         HRCWH_TSEC1M_IN_GMII |\
390         HRCWH_TSEC2M_IN_GMII)
391 #else
392 #define CONFIG_SYS_HRCW_HIGH (\
393         HRCWH_PCI_HOST |\
394         HRCWH_32_BIT_PCI |\
395         HRCWH_PCI1_ARBITER_ENABLE |\
396         HRCWH_PCI2_ARBITER_DISABLE |\
397         HRCWH_CORE_ENABLE |\
398         HRCWH_FROM_0X00000100 |\
399         HRCWH_BOOTSEQ_DISABLE |\
400         HRCWH_SW_WATCHDOG_DISABLE |\
401         HRCWH_ROM_LOC_LOCAL_16BIT |\
402         HRCWH_TSEC1M_IN_GMII |\
403         HRCWH_TSEC2M_IN_GMII)
404 #endif
405
406 /* System IO Config */
407 #define CONFIG_SYS_SICRH        0
408 #define CONFIG_SYS_SICRL        SICRL_LDP_A
409
410 /* i-cache and d-cache disabled */
411 #define CONFIG_SYS_HID0_INIT    0x000000000
412 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
413                                  HID0_ENABLE_INSTRUCTION_CACHE)
414 #define CONFIG_SYS_HID2 HID2_HBE
415
416 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
417
418 /* DDR 0 - 512M */
419 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
420                                 | BATL_PP_RW \
421                                 | BATL_MEMCOHERENCE)
422 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
423                                 | BATU_BL_256M \
424                                 | BATU_VS \
425                                 | BATU_VP)
426 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
427                                 | BATL_PP_RW \
428                                 | BATL_MEMCOHERENCE)
429 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
430                                 | BATU_BL_256M \
431                                 | BATU_VS \
432                                 | BATU_VP)
433
434 /* stack in DCACHE @ 512M (no backing mem) */
435 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_INIT_RAM_ADDR \
436                                 | BATL_PP_RW \
437                                 | BATL_MEMCOHERENCE)
438 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_INIT_RAM_ADDR \
439                                 | BATU_BL_128K \
440                                 | BATU_VS \
441                                 | BATU_VP)
442
443 /* PCI */
444 #ifdef CONFIG_PCI
445 #define CONFIG_PCI_INDIRECT_BRIDGE
446 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MEM_BASE \
447                                 | BATL_PP_RW \
448                                 | BATL_MEMCOHERENCE)
449 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MEM_BASE \
450                                 | BATU_BL_256M \
451                                 | BATU_VS \
452                                 | BATU_VP)
453 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_MMIO_BASE \
454                                 | BATL_PP_RW \
455                                 | BATL_MEMCOHERENCE \
456                                 | BATL_GUARDEDSTORAGE)
457 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI1_MMIO_BASE \
458                                 | BATU_BL_256M \
459                                 | BATU_VS \
460                                 | BATU_VP)
461 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_IO_BASE \
462                                 | BATL_PP_RW \
463                                 | BATL_CACHEINHIBIT \
464                                 | BATL_GUARDEDSTORAGE)
465 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_IO_BASE \
466                                 | BATU_BL_16M \
467                                 | BATU_VS \
468                                 | BATU_VP)
469 #else
470 #define CONFIG_SYS_IBAT3L       (0)
471 #define CONFIG_SYS_IBAT3U       (0)
472 #define CONFIG_SYS_IBAT4L       (0)
473 #define CONFIG_SYS_IBAT4U       (0)
474 #define CONFIG_SYS_IBAT5L       (0)
475 #define CONFIG_SYS_IBAT5U       (0)
476 #endif
477
478 /* IMMRBAR */
479 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_IMMR \
480                                 | BATL_PP_RW \
481                                 | BATL_CACHEINHIBIT \
482                                 | BATL_GUARDEDSTORAGE)
483 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_IMMR \
484                                 | BATU_BL_1M \
485                                 | BATU_VS \
486                                 | BATU_VP)
487
488 /* FLASH */
489 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_FLASH_BASE \
490                                 | BATL_PP_RW \
491                                 | BATL_CACHEINHIBIT \
492                                 | BATL_GUARDEDSTORAGE)
493 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_FLASH_BASE \
494                                 | BATU_BL_256M \
495                                 | BATU_VS \
496                                 | BATU_VP)
497
498 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
499 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
500 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
501 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
502 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
503 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
504 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
505 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
506 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
507 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
508 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
509 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
510 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
511 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
512 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
513 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
514
515 #if defined(CONFIG_CMD_KGDB)
516 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
517 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
518 #endif
519
520 /*
521  * Environment Configuration
522  */
523
524                                 /* default location for tftp and bootm */
525 #define CONFIG_LOADADDR         400000
526
527 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
528 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
529
530 #define CONFIG_BAUDRATE         115200
531
532 #define CONFIG_PREBOOT  "echo;" \
533         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
534         "echo"
535
536 #undef  CONFIG_BOOTARGS
537
538 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
539         "netdev=eth0\0"                                                 \
540         "hostname=tqm834x\0"                                            \
541         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
542                 "nfsroot=${serverip}:${rootpath}\0"                     \
543         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
544         "addip=setenv bootargs ${bootargs} "                            \
545                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
546                 ":${hostname}:${netdev}:off panic=1\0"                  \
547         "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
548         "flash_nfs_old=run nfsargs addip addcons;"                      \
549                 "bootm ${kernel_addr}\0"                                \
550         "flash_nfs=run nfsargs addip addcons;"                          \
551                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
552         "flash_self_old=run ramargs addip addcons;"                     \
553                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
554         "flash_self=run ramargs addip addcons;"                         \
555                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
556         "net_nfs_old=tftp 400000 ${bootfile};"                          \
557                 "run nfsargs addip addcons;bootm\0"                     \
558         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
559                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
560                 "run nfsargs addip addcons; "                           \
561                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
562         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
563         "bootfile=tqm834x/uImage\0"                                     \
564         "fdtfile=tqm834x/tqm834x.dtb\0"                                 \
565         "kernel_addr_r=400000\0"                                        \
566         "fdt_addr_r=600000\0"                                           \
567         "ramdisk_addr_r=800000\0"                                       \
568         "kernel_addr=800C0000\0"                                        \
569         "fdt_addr=800A0000\0"                                           \
570         "ramdisk_addr=80300000\0"                                       \
571         "u-boot=tqm834x/u-boot.bin\0"                                   \
572         "load=tftp 200000 ${u-boot}\0"                                  \
573         "update=protect off 80000000 +${filesize};"                     \
574                 "era 80000000 +${filesize};"                            \
575                 "cp.b 200000 80000000 ${filesize}\0"                    \
576         "upd=run load update\0"                                         \
577         ""
578
579 #define CONFIG_BOOTCOMMAND      "run flash_self"
580
581 /*
582  * JFFS2 partitions
583  */
584 /* mtdparts command line support */
585 #define CONFIG_CMD_MTDPARTS
586 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
587 #define CONFIG_FLASH_CFI_MTD
588 #define MTDIDS_DEFAULT          "nor0=TQM834x-0"
589
590 /* default mtd partition table */
591 #define MTDPARTS_DEFAULT        "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
592                                                 "1m(kernel),2m(initrd)," \
593                                                 "-(user);" \
594
595 #endif  /* __CONFIG_H */