Add GPL-2.0+ SPDX-License-Identifier to source files
[oweals/u-boot.git] / include / configs / TQM834x.h
1 /*
2  * (C) Copyright 2005
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+ 
6  */
7
8 /*
9  * TQM8349 board configuration file
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*
16  * High Level Configuration Options
17  */
18 #define CONFIG_E300             1       /* E300 Family */
19 #define CONFIG_MPC83xx          1       /* MPC83xx family */
20 #define CONFIG_MPC834x          1       /* MPC834x specific */
21 #define CONFIG_MPC8349          1       /* MPC8349 specific */
22 #define CONFIG_TQM834X          1       /* TQM834X board specific */
23
24 #define CONFIG_SYS_TEXT_BASE    0x80000000
25
26 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
27 #define CONFIG_SYS_IMMR         0xff400000
28
29 /* System clock. Primary input clock when in PCI host mode */
30 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
31
32 /*
33  * Local Bus LCRR
34  *    LCRR:  DLL bypass, Clock divider is 8
35  *
36  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
37  *
38  * External Local Bus rate is
39  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
40  */
41 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
42 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
43
44 /* board pre init: do not call, nothing to do */
45 #undef CONFIG_BOARD_EARLY_INIT_F
46
47 /* detect the number of flash banks */
48 #define CONFIG_BOARD_EARLY_INIT_R
49
50 /*
51  * DDR Setup
52  */
53                                 /* DDR is system memory*/
54 #define CONFIG_SYS_DDR_BASE     0x00000000
55 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
56 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
57 #define DDR_CASLAT_25           /* CASLAT set to 2.5 */
58 #undef CONFIG_DDR_ECC           /* only for ECC DDR module */
59 #undef CONFIG_SPD_EEPROM        /* do not use SPD EEPROM for DDR setup */
60
61 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
62 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
63 #define CONFIG_SYS_MEMTEST_END          0x00100000
64
65 /*
66  * FLASH on the Local Bus
67  */
68 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
69 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
70 #undef CONFIG_SYS_FLASH_CHECKSUM
71 #define CONFIG_SYS_FLASH_BASE           0x80000000      /* start of FLASH   */
72 #define CONFIG_SYS_FLASH_SIZE           8               /* FLASH size in MB */
73 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sectors */
74 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
75
76 /*
77  * FLASH bank number detection
78  */
79
80 /*
81  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
82  * Flash banks has to be determined at runtime and stored in a gloabl variable
83  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
84  * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
85  * flash_info, and should be made sufficiently large to accomodate the number
86  * of banks that might actually be detected.  Since most (all?) Flash related
87  * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
88  * the board, it is defined as tqm834x_num_flash_banks.
89  */
90 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       2
91
92 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
93
94 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
95 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA) \
96                                 | BR_MS_GPCM \
97                                 | BR_PS_32 \
98                                 | BR_V)
99
100 /* FLASH timing (0x0000_0c54) */
101 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_GPCM_CSNT \
102                                         | OR_GPCM_ACS_DIV4 \
103                                         | OR_GPCM_SCY_5 \
104                                         | OR_GPCM_TRLX)
105
106 #define CONFIG_SYS_PRELIM_OR_AM         OR_AM_1GB /* OR addr mask: 1 GiB */
107
108 #define CONFIG_SYS_OR0_PRELIM           (CONFIG_SYS_PRELIM_OR_AM  \
109                                         | CONFIG_SYS_OR_TIMING_FLASH)
110
111 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_1GB)
112
113                                         /* Window base at flash base */
114 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
115
116 /* disable remaining mappings */
117 #define CONFIG_SYS_BR1_PRELIM           0x00000000
118 #define CONFIG_SYS_OR1_PRELIM           0x00000000
119 #define CONFIG_SYS_LBLAWBAR1_PRELIM     0x00000000
120 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x00000000
121
122 #define CONFIG_SYS_BR2_PRELIM           0x00000000
123 #define CONFIG_SYS_OR2_PRELIM           0x00000000
124 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0x00000000
125 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x00000000
126
127 #define CONFIG_SYS_BR3_PRELIM           0x00000000
128 #define CONFIG_SYS_OR3_PRELIM           0x00000000
129 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0x00000000
130 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x00000000
131
132 /*
133  * Monitor config
134  */
135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
136
137 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
138 # define CONFIG_SYS_RAMBOOT
139 #else
140 # undef  CONFIG_SYS_RAMBOOT
141 #endif
142
143 #define CONFIG_SYS_INIT_RAM_LOCK        1
144 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000 /* Initial RAM address */
145 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
146
147 #define CONFIG_SYS_GBL_DATA_OFFSET      \
148                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
149 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
150
151                                 /* Reserve 384 kB = 3 sect. for Mon */
152 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)
153                                 /* Reserve 512 kB for malloc */
154 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)
155
156 /*
157  * Serial Port
158  */
159 #define CONFIG_CONS_INDEX       1
160 #define CONFIG_SYS_NS16550
161 #define CONFIG_SYS_NS16550_SERIAL
162 #define CONFIG_SYS_NS16550_REG_SIZE     1
163 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
164
165 #define CONFIG_SYS_BAUDRATE_TABLE  \
166                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
167
168 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
169 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
170
171 /*
172  * I2C
173  */
174 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
175 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
176 #define CONFIG_FSL_I2C
177 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed: 400KHz */
178 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* slave address */
179 #define CONFIG_SYS_I2C_OFFSET           0x3000
180
181 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
182 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16 bit */
184 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32 bytes/write */
185 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12      /* 10ms +/- 20% */
186 #define CONFIG_SYS_I2C_MULTI_EEPROMS            /* more than one eeprom */
187
188 /* I2C RTC */
189 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c */
190 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68 */
191
192 /* I2C SYSMON (LM75) */
193 #define CONFIG_DTT_LM75                 1       /* ON Semi's LM75 */
194 #define CONFIG_DTT_SENSORS              {0}     /* Sensor addresses */
195 #define CONFIG_SYS_DTT_MAX_TEMP         70
196 #define CONFIG_SYS_DTT_LOW_TEMP         -30
197 #define CONFIG_SYS_DTT_HYSTERESIS       3
198
199 /*
200  * TSEC
201  */
202 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
203 #define CONFIG_MII
204
205 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
206 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
207 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
208 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
209
210 #if defined(CONFIG_TSEC_ENET)
211
212 #define CONFIG_TSEC1            1
213 #define CONFIG_TSEC1_NAME       "TSEC0"
214 #define CONFIG_TSEC2            1
215 #define CONFIG_TSEC2_NAME       "TSEC1"
216 #define TSEC1_PHY_ADDR          2
217 #define TSEC2_PHY_ADDR          1
218 #define TSEC1_PHYIDX            0
219 #define TSEC2_PHYIDX            0
220 #define TSEC1_FLAGS             TSEC_GIGABIT
221 #define TSEC2_FLAGS             TSEC_GIGABIT
222
223 /* Options are: TSEC[0-1] */
224 #define CONFIG_ETHPRIME         "TSEC0"
225
226 #endif  /* CONFIG_TSEC_ENET */
227
228 /*
229  * General PCI
230  * Addresses are mapped 1-1.
231  */
232 #define CONFIG_PCI
233
234 #if defined(CONFIG_PCI)
235
236 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
237 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
238
239 /* PCI1 host bridge */
240 #define CONFIG_SYS_PCI1_MEM_BASE        0x90000000
241 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
242 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
243 #define CONFIG_SYS_PCI1_MMIO_BASE       \
244                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
245 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
246 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
247 #define CONFIG_SYS_PCI1_IO_BASE         0xe2000000
248 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
249 #define CONFIG_SYS_PCI1_IO_SIZE         0x1000000       /* 16M */
250
251 #undef CONFIG_EEPRO100
252 #define CONFIG_EEPRO100
253 #undef CONFIG_TULIP
254
255 #if !defined(CONFIG_PCI_PNP)
256         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
257         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_MEM_BASE
258         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
259 #endif
260
261 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          0x1957  /* Freescale */
262
263 #endif  /* CONFIG_PCI */
264
265 /*
266  * Environment
267  */
268 #define CONFIG_ENV_IS_IN_FLASH  1
269 #define CONFIG_ENV_ADDR         \
270                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
271 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env */
272 #define CONFIG_ENV_SIZE         0x8000  /*  32K max size */
273 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
274 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
275
276 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
277 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
278
279 /*
280  * BOOTP options
281  */
282 #define CONFIG_BOOTP_BOOTFILESIZE
283 #define CONFIG_BOOTP_BOOTPATH
284 #define CONFIG_BOOTP_GATEWAY
285 #define CONFIG_BOOTP_HOSTNAME
286
287
288 /*
289  * Command line configuration.
290  */
291 #include <config_cmd_default.h>
292
293 #define CONFIG_CMD_ASKENV
294 #define CONFIG_CMD_DATE
295 #define CONFIG_CMD_DHCP
296 #define CONFIG_CMD_DTT
297 #define CONFIG_CMD_EEPROM
298 #define CONFIG_CMD_I2C
299 #define CONFIG_CMD_NFS
300 #define CONFIG_CMD_JFFS2
301 #define CONFIG_CMD_MII
302 #define CONFIG_CMD_PING
303 #define CONFIG_CMD_REGINFO
304 #define CONFIG_CMD_SNTP
305
306 #if defined(CONFIG_PCI)
307     #define CONFIG_CMD_PCI
308 #endif
309
310 #if defined(CONFIG_SYS_RAMBOOT)
311     #undef CONFIG_CMD_SAVEENV
312     #undef CONFIG_CMD_LOADS
313 #endif
314
315 /*
316  * Miscellaneous configurable options
317  */
318 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
319 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
320 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
321
322 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
323 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
324
325 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser */
326
327 #if defined(CONFIG_CMD_KGDB)
328         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
329 #else
330         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
331 #endif
332
333                                 /* Print Buffer Size */
334 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
335 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
336                                 /* Boot Argument Buffer Size */
337 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
338 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
339
340 #undef CONFIG_WATCHDOG          /* watchdog disabled */
341
342 /* pass open firmware flat tree */
343 #define CONFIG_OF_LIBFDT        1
344 #define CONFIG_OF_BOARD_SETUP   1
345 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
346
347 /*
348  * For booting Linux, the board info and command line data
349  * have to be in the first 256 MB of memory, since this is
350  * the maximum mapped by the Linux kernel during initialization.
351  */
352                                 /* Initial Memory map for Linux */
353 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
354
355 #define CONFIG_SYS_HRCW_LOW (\
356         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
357         HRCWL_DDR_TO_SCB_CLK_1X1 |\
358         HRCWL_CSB_TO_CLKIN_4X1 |\
359         HRCWL_VCO_1X2 |\
360         HRCWL_CORE_TO_CSB_2X1)
361
362 #if defined(PCI_64BIT)
363 #define CONFIG_SYS_HRCW_HIGH (\
364         HRCWH_PCI_HOST |\
365         HRCWH_64_BIT_PCI |\
366         HRCWH_PCI1_ARBITER_ENABLE |\
367         HRCWH_PCI2_ARBITER_DISABLE |\
368         HRCWH_CORE_ENABLE |\
369         HRCWH_FROM_0X00000100 |\
370         HRCWH_BOOTSEQ_DISABLE |\
371         HRCWH_SW_WATCHDOG_DISABLE |\
372         HRCWH_ROM_LOC_LOCAL_16BIT |\
373         HRCWH_TSEC1M_IN_GMII |\
374         HRCWH_TSEC2M_IN_GMII)
375 #else
376 #define CONFIG_SYS_HRCW_HIGH (\
377         HRCWH_PCI_HOST |\
378         HRCWH_32_BIT_PCI |\
379         HRCWH_PCI1_ARBITER_ENABLE |\
380         HRCWH_PCI2_ARBITER_DISABLE |\
381         HRCWH_CORE_ENABLE |\
382         HRCWH_FROM_0X00000100 |\
383         HRCWH_BOOTSEQ_DISABLE |\
384         HRCWH_SW_WATCHDOG_DISABLE |\
385         HRCWH_ROM_LOC_LOCAL_16BIT |\
386         HRCWH_TSEC1M_IN_GMII |\
387         HRCWH_TSEC2M_IN_GMII)
388 #endif
389
390 /* System IO Config */
391 #define CONFIG_SYS_SICRH        0
392 #define CONFIG_SYS_SICRL        SICRL_LDP_A
393
394 /* i-cache and d-cache disabled */
395 #define CONFIG_SYS_HID0_INIT    0x000000000
396 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
397                                  HID0_ENABLE_INSTRUCTION_CACHE)
398 #define CONFIG_SYS_HID2 HID2_HBE
399
400 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
401
402 /* DDR 0 - 512M */
403 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
404                                 | BATL_PP_RW \
405                                 | BATL_MEMCOHERENCE)
406 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
407                                 | BATU_BL_256M \
408                                 | BATU_VS \
409                                 | BATU_VP)
410 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
411                                 | BATL_PP_RW \
412                                 | BATL_MEMCOHERENCE)
413 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
414                                 | BATU_BL_256M \
415                                 | BATU_VS \
416                                 | BATU_VP)
417
418 /* stack in DCACHE @ 512M (no backing mem) */
419 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_INIT_RAM_ADDR \
420                                 | BATL_PP_RW \
421                                 | BATL_MEMCOHERENCE)
422 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_INIT_RAM_ADDR \
423                                 | BATU_BL_128K \
424                                 | BATU_VS \
425                                 | BATU_VP)
426
427 /* PCI */
428 #ifdef CONFIG_PCI
429 #define CONFIG_PCI_INDIRECT_BRIDGE
430 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MEM_BASE \
431                                 | BATL_PP_RW \
432                                 | BATL_MEMCOHERENCE)
433 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MEM_BASE \
434                                 | BATU_BL_256M \
435                                 | BATU_VS \
436                                 | BATU_VP)
437 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_MMIO_BASE \
438                                 | BATL_PP_RW \
439                                 | BATL_MEMCOHERENCE \
440                                 | BATL_GUARDEDSTORAGE)
441 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI1_MMIO_BASE \
442                                 | BATU_BL_256M \
443                                 | BATU_VS \
444                                 | BATU_VP)
445 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_IO_BASE \
446                                 | BATL_PP_RW \
447                                 | BATL_CACHEINHIBIT \
448                                 | BATL_GUARDEDSTORAGE)
449 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_IO_BASE \
450                                 | BATU_BL_16M \
451                                 | BATU_VS \
452                                 | BATU_VP)
453 #else
454 #define CONFIG_SYS_IBAT3L       (0)
455 #define CONFIG_SYS_IBAT3U       (0)
456 #define CONFIG_SYS_IBAT4L       (0)
457 #define CONFIG_SYS_IBAT4U       (0)
458 #define CONFIG_SYS_IBAT5L       (0)
459 #define CONFIG_SYS_IBAT5U       (0)
460 #endif
461
462 /* IMMRBAR */
463 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_IMMR \
464                                 | BATL_PP_RW \
465                                 | BATL_CACHEINHIBIT \
466                                 | BATL_GUARDEDSTORAGE)
467 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_IMMR \
468                                 | BATU_BL_1M \
469                                 | BATU_VS \
470                                 | BATU_VP)
471
472 /* FLASH */
473 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_FLASH_BASE \
474                                 | BATL_PP_RW \
475                                 | BATL_CACHEINHIBIT \
476                                 | BATL_GUARDEDSTORAGE)
477 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_FLASH_BASE \
478                                 | BATU_BL_256M \
479                                 | BATU_VS \
480                                 | BATU_VP)
481
482 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
483 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
484 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
485 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
486 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
487 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
488 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
489 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
490 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
491 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
492 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
493 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
494 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
495 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
496 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
497 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
498
499 #if defined(CONFIG_CMD_KGDB)
500 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
501 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
502 #endif
503
504 /*
505  * Environment Configuration
506  */
507
508                                 /* default location for tftp and bootm */
509 #define CONFIG_LOADADDR         400000
510
511 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
512 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
513
514 #define CONFIG_BAUDRATE         115200
515
516 #define CONFIG_PREBOOT  "echo;" \
517         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
518         "echo"
519
520 #undef  CONFIG_BOOTARGS
521
522 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
523         "netdev=eth0\0"                                                 \
524         "hostname=tqm834x\0"                                            \
525         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
526                 "nfsroot=${serverip}:${rootpath}\0"                     \
527         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
528         "addip=setenv bootargs ${bootargs} "                            \
529                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
530                 ":${hostname}:${netdev}:off panic=1\0"                  \
531         "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
532         "flash_nfs_old=run nfsargs addip addcons;"                      \
533                 "bootm ${kernel_addr}\0"                                \
534         "flash_nfs=run nfsargs addip addcons;"                          \
535                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
536         "flash_self_old=run ramargs addip addcons;"                     \
537                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
538         "flash_self=run ramargs addip addcons;"                         \
539                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
540         "net_nfs_old=tftp 400000 ${bootfile};"                          \
541                 "run nfsargs addip addcons;bootm\0"                     \
542         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
543                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
544                 "run nfsargs addip addcons; "                           \
545                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
546         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
547         "bootfile=tqm834x/uImage\0"                                     \
548         "fdtfile=tqm834x/tqm834x.dtb\0"                                 \
549         "kernel_addr_r=400000\0"                                        \
550         "fdt_addr_r=600000\0"                                           \
551         "ramdisk_addr_r=800000\0"                                       \
552         "kernel_addr=800C0000\0"                                        \
553         "fdt_addr=800A0000\0"                                           \
554         "ramdisk_addr=80300000\0"                                       \
555         "u-boot=tqm834x/u-boot.bin\0"                                   \
556         "load=tftp 200000 ${u-boot}\0"                                  \
557         "update=protect off 80000000 +${filesize};"                     \
558                 "era 80000000 +${filesize};"                            \
559                 "cp.b 200000 80000000 ${filesize}\0"                    \
560         "upd=run load update\0"                                         \
561         ""
562
563 #define CONFIG_BOOTCOMMAND      "run flash_self"
564
565 /*
566  * JFFS2 partitions
567  */
568 /* mtdparts command line support */
569 #define CONFIG_CMD_MTDPARTS
570 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
571 #define CONFIG_FLASH_CFI_MTD
572 #define MTDIDS_DEFAULT          "nor0=TQM834x-0"
573
574 /* default mtd partition table */
575 #define MTDPARTS_DEFAULT        "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
576                                                 "1m(kernel),2m(initrd)," \
577                                                 "-(user);" \
578
579 #endif  /* __CONFIG_H */