include/configs/TQM834x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2005
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 /*
   8  * TQM8349 board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_E300             1       /* E300 Family */
  18 #define CONFIG_MPC834x          1       /* MPC834x specific */
  19 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  20
  21 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
  22 #define CONFIG_SYS_IMMR         0xff400000
  23
  24 /* System clock. Primary input clock when in PCI host mode */
  25 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
  26
  27 /*
  28  * Local Bus LCRR
  29  *    LCRR:  DLL bypass, Clock divider is 8
  30  *
  31  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  32  *
  33  * External Local Bus rate is
  34  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  35  */
  36 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
  37 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
  38
  39 /* board pre init: do not call, nothing to do */
  40
  41 /* detect the number of flash banks */
  42
  43 /*
  44  * DDR Setup
  45  */
  46                                 /* DDR is system memory*/
  47 #define CONFIG_SYS_DDR_BASE     0x00000000
  48 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  49 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  50 #define DDR_CASLAT_25           /* CASLAT set to 2.5 */
  51 #undef CONFIG_DDR_ECC           /* only for ECC DDR module */
  52 #undef CONFIG_SPD_EEPROM        /* do not use SPD EEPROM for DDR setup */
  53
  54 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  55 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  56 #define CONFIG_SYS_MEMTEST_END          0x00100000
  57
  58 /*
  59  * FLASH on the Local Bus
  60  */
  61 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
  62 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
  63 #undef CONFIG_SYS_FLASH_CHECKSUM
  64 #define CONFIG_SYS_FLASH_BASE           0x80000000      /* start of FLASH   */
  65 #define CONFIG_SYS_FLASH_SIZE           8               /* FLASH size in MB */
  66 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sectors */
  67 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  68
  69 /*
  70  * FLASH bank number detection
  71  */
  72
  73 /*
  74  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
  75  * Flash banks has to be determined at runtime and stored in a gloabl variable
  76  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
  77  * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
  78  * flash_info, and should be made sufficiently large to accomodate the number
  79  * of banks that might actually be detected.  Since most (all?) Flash related
  80  * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
  81  * the board, it is defined as tqm834x_num_flash_banks.
  82  */
  83 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       2
  84
  85 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
  86
  87 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
  88 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA) \
  89                                 | BR_MS_GPCM \
  90                                 | BR_PS_32 \
  91                                 | BR_V)
  92
  93 /* FLASH timing (0x0000_0c54) */
  94 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_GPCM_CSNT \
  95                                         | OR_GPCM_ACS_DIV4 \
  96                                         | OR_GPCM_SCY_5 \
  97                                         | OR_GPCM_TRLX)
  98
  99 #define CONFIG_SYS_PRELIM_OR_AM         OR_AM_1GB /* OR addr mask: 1 GiB */
 100
 101 #define CONFIG_SYS_OR0_PRELIM           (CONFIG_SYS_PRELIM_OR_AM  \
 102                                         | CONFIG_SYS_OR_TIMING_FLASH)
 103
 104 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_1GB)
 105
 106                                         /* Window base at flash base */
 107 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 108
 109 /* disable remaining mappings */
 110 #define CONFIG_SYS_BR1_PRELIM           0x00000000
 111 #define CONFIG_SYS_OR1_PRELIM           0x00000000
 112 #define CONFIG_SYS_LBLAWBAR1_PRELIM     0x00000000
 113 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x00000000
 114
 115 #define CONFIG_SYS_BR2_PRELIM           0x00000000
 116 #define CONFIG_SYS_OR2_PRELIM           0x00000000
 117 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0x00000000
 118 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x00000000
 119
 120 #define CONFIG_SYS_BR3_PRELIM           0x00000000
 121 #define CONFIG_SYS_OR3_PRELIM           0x00000000
 122 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0x00000000
 123 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x00000000
 124
 125 /*
 126  * Monitor config
 127  */
 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 129
 130 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 131 # define CONFIG_SYS_RAMBOOT
 132 #else
 133 # undef  CONFIG_SYS_RAMBOOT
 134 #endif
 135
 136 #define CONFIG_SYS_INIT_RAM_LOCK        1
 137 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000 /* Initial RAM address */
 138 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
 139
 140 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 141                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 142 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 143
 144                                 /* Reserve 384 kB = 3 sect. for Mon */
 145 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)
 146                                 /* Reserve 512 kB for malloc */
 147 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)
 148
 149 /*
 150  * Serial Port
 151  */
 152 #define CONFIG_SYS_NS16550_SERIAL
 153 #define CONFIG_SYS_NS16550_REG_SIZE     1
 154 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 155
 156 #define CONFIG_SYS_BAUDRATE_TABLE  \
 157                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 158
 159 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 160 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 161
 162 /*
 163  * I2C
 164  */
 165 #define CONFIG_SYS_I2C
 166 #define CONFIG_SYS_I2C_FSL
 167 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 168 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 169 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 170
 171 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
 172 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16 bit */
 174 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32 bytes/write */
 175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12      /* 10ms +/- 20% */
 176
 177 /* I2C RTC */
 178 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c */
 179 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68 */
 180
 181 /*
 182  * TSEC
 183  */
 184
 185 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 186 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 187 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 188 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 189
 190 #if defined(CONFIG_TSEC_ENET)
 191
 192 #define CONFIG_TSEC1            1
 193 #define CONFIG_TSEC1_NAME       "TSEC0"
 194 #define CONFIG_TSEC2            1
 195 #define CONFIG_TSEC2_NAME       "TSEC1"
 196 #define TSEC1_PHY_ADDR          2
 197 #define TSEC2_PHY_ADDR          1
 198 #define TSEC1_PHYIDX            0
 199 #define TSEC2_PHYIDX            0
 200 #define TSEC1_FLAGS             TSEC_GIGABIT
 201 #define TSEC2_FLAGS             TSEC_GIGABIT
 202
 203 /* Options are: TSEC[0-1] */
 204 #define CONFIG_ETHPRIME         "TSEC0"
 205
 206 #endif  /* CONFIG_TSEC_ENET */
 207
 208 #if defined(CONFIG_PCI)
 209
 210 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 211
 212 /* PCI1 host bridge */
 213 #define CONFIG_SYS_PCI1_MEM_BASE        0x90000000
 214 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 215 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 216 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 217                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 218 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 219 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 220 #define CONFIG_SYS_PCI1_IO_BASE         0xe2000000
 221 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 222 #define CONFIG_SYS_PCI1_IO_SIZE         0x1000000       /* 16M */
 223
 224 #undef CONFIG_EEPRO100
 225 #define CONFIG_EEPRO100
 226 #undef CONFIG_TULIP
 227
 228 #if !defined(CONFIG_PCI_PNP)
 229         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
 230         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_MEM_BASE
 231         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
 232 #endif
 233
 234 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          0x1957  /* Freescale */
 235
 236 #endif  /* CONFIG_PCI */
 237
 238 /*
 239  * Environment
 240  */
 241 #define CONFIG_ENV_ADDR         \
 242                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 243 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env */
 244 #define CONFIG_ENV_SIZE         0x8000  /*  32K max size */
 245 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 246 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 247
 248 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
 249 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
 250
 251 /*
 252  * BOOTP options
 253  */
 254 #define CONFIG_BOOTP_BOOTFILESIZE
 255
 256 /*
 257  * Miscellaneous configurable options
 258  */
 259 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 260
 261 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 262
 263 /*
 264  * For booting Linux, the board info and command line data
 265  * have to be in the first 256 MB of memory, since this is
 266  * the maximum mapped by the Linux kernel during initialization.
 267  */
 268                                 /* Initial Memory map for Linux */
 269 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 270
 271 #define CONFIG_SYS_HRCW_LOW (\
 272         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 273         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 274         HRCWL_CSB_TO_CLKIN_4X1 |\
 275         HRCWL_VCO_1X2 |\
 276         HRCWL_CORE_TO_CSB_2X1)
 277
 278 #if defined(PCI_64BIT)
 279 #define CONFIG_SYS_HRCW_HIGH (\
 280         HRCWH_PCI_HOST |\
 281         HRCWH_64_BIT_PCI |\
 282         HRCWH_PCI1_ARBITER_ENABLE |\
 283         HRCWH_PCI2_ARBITER_DISABLE |\
 284         HRCWH_CORE_ENABLE |\
 285         HRCWH_FROM_0X00000100 |\
 286         HRCWH_BOOTSEQ_DISABLE |\
 287         HRCWH_SW_WATCHDOG_DISABLE |\
 288         HRCWH_ROM_LOC_LOCAL_16BIT |\
 289         HRCWH_TSEC1M_IN_GMII |\
 290         HRCWH_TSEC2M_IN_GMII)
 291 #else
 292 #define CONFIG_SYS_HRCW_HIGH (\
 293         HRCWH_PCI_HOST |\
 294         HRCWH_32_BIT_PCI |\
 295         HRCWH_PCI1_ARBITER_ENABLE |\
 296         HRCWH_PCI2_ARBITER_DISABLE |\
 297         HRCWH_CORE_ENABLE |\
 298         HRCWH_FROM_0X00000100 |\
 299         HRCWH_BOOTSEQ_DISABLE |\
 300         HRCWH_SW_WATCHDOG_DISABLE |\
 301         HRCWH_ROM_LOC_LOCAL_16BIT |\
 302         HRCWH_TSEC1M_IN_GMII |\
 303         HRCWH_TSEC2M_IN_GMII)
 304 #endif
 305
 306 /* System IO Config */
 307 #define CONFIG_SYS_SICRH        0
 308 #define CONFIG_SYS_SICRL        SICRL_LDP_A
 309
 310 /* i-cache and d-cache disabled */
 311 #define CONFIG_SYS_HID0_INIT    0x000000000
 312 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
 313                                  HID0_ENABLE_INSTRUCTION_CACHE)
 314 #define CONFIG_SYS_HID2 HID2_HBE
 315
 316 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 317
 318 /* DDR 0 - 512M */
 319 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 320                                 | BATL_PP_RW \
 321                                 | BATL_MEMCOHERENCE)
 322 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 323                                 | BATU_BL_256M \
 324                                 | BATU_VS \
 325                                 | BATU_VP)
 326 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
 327                                 | BATL_PP_RW \
 328                                 | BATL_MEMCOHERENCE)
 329 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
 330                                 | BATU_BL_256M \
 331                                 | BATU_VS \
 332                                 | BATU_VP)
 333
 334 /* stack in DCACHE @ 512M (no backing mem) */
 335 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_INIT_RAM_ADDR \
 336                                 | BATL_PP_RW \
 337                                 | BATL_MEMCOHERENCE)
 338 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_INIT_RAM_ADDR \
 339                                 | BATU_BL_128K \
 340                                 | BATU_VS \
 341                                 | BATU_VP)
 342
 343 /* PCI */
 344 #ifdef CONFIG_PCI
 345 #define CONFIG_PCI_INDIRECT_BRIDGE
 346 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MEM_BASE \
 347                                 | BATL_PP_RW \
 348                                 | BATL_MEMCOHERENCE)
 349 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MEM_BASE \
 350                                 | BATU_BL_256M \
 351                                 | BATU_VS \
 352                                 | BATU_VP)
 353 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_MMIO_BASE \
 354                                 | BATL_PP_RW \
 355                                 | BATL_MEMCOHERENCE \
 356                                 | BATL_GUARDEDSTORAGE)
 357 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI1_MMIO_BASE \
 358                                 | BATU_BL_256M \
 359                                 | BATU_VS \
 360                                 | BATU_VP)
 361 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_IO_BASE \
 362                                 | BATL_PP_RW \
 363                                 | BATL_CACHEINHIBIT \
 364                                 | BATL_GUARDEDSTORAGE)
 365 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_IO_BASE \
 366                                 | BATU_BL_16M \
 367                                 | BATU_VS \
 368                                 | BATU_VP)
 369 #else
 370 #define CONFIG_SYS_IBAT3L       (0)
 371 #define CONFIG_SYS_IBAT3U       (0)
 372 #define CONFIG_SYS_IBAT4L       (0)
 373 #define CONFIG_SYS_IBAT4U       (0)
 374 #define CONFIG_SYS_IBAT5L       (0)
 375 #define CONFIG_SYS_IBAT5U       (0)
 376 #endif
 377
 378 /* IMMRBAR */
 379 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_IMMR \
 380                                 | BATL_PP_RW \
 381                                 | BATL_CACHEINHIBIT \
 382                                 | BATL_GUARDEDSTORAGE)
 383 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_IMMR \
 384                                 | BATU_BL_1M \
 385                                 | BATU_VS \
 386                                 | BATU_VP)
 387
 388 /* FLASH */
 389 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_FLASH_BASE \
 390                                 | BATL_PP_RW \
 391                                 | BATL_CACHEINHIBIT \
 392                                 | BATL_GUARDEDSTORAGE)
 393 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_FLASH_BASE \
 394                                 | BATU_BL_256M \
 395                                 | BATU_VS \
 396                                 | BATU_VP)
 397
 398 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 399 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 400 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 401 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 402 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 403 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 404 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 405 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 406 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 407 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 408 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 409 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 410 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 411 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 412 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 413 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 414
 415 #if defined(CONFIG_CMD_KGDB)
 416 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 417 #endif
 418
 419 /*
 420  * Environment Configuration
 421  */
 422
 423                                 /* default location for tftp and bootm */
 424 #define CONFIG_LOADADDR         400000
 425
 426 #define CONFIG_PREBOOT  "echo;" \
 427         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 428         "echo"
 429
 430 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 431         "netdev=eth0\0"                                                 \
 432         "hostname=tqm834x\0"                                            \
 433         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 434                 "nfsroot=${serverip}:${rootpath}\0"                     \
 435         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 436         "addip=setenv bootargs ${bootargs} "                            \
 437                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 438                 ":${hostname}:${netdev}:off panic=1\0"                  \
 439         "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 440         "flash_nfs_old=run nfsargs addip addcons;"                      \
 441                 "bootm ${kernel_addr}\0"                                \
 442         "flash_nfs=run nfsargs addip addcons;"                          \
 443                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 444         "flash_self_old=run ramargs addip addcons;"                     \
 445                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 446         "flash_self=run ramargs addip addcons;"                         \
 447                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 448         "net_nfs_old=tftp 400000 ${bootfile};"                          \
 449                 "run nfsargs addip addcons;bootm\0"                     \
 450         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 451                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 452                 "run nfsargs addip addcons; "                           \
 453                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 454         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 455         "bootfile=tqm834x/uImage\0"                                     \
 456         "fdtfile=tqm834x/tqm834x.dtb\0"                                 \
 457         "kernel_addr_r=400000\0"                                        \
 458         "fdt_addr_r=600000\0"                                           \
 459         "ramdisk_addr_r=800000\0"                                       \
 460         "kernel_addr=800C0000\0"                                        \
 461         "fdt_addr=800A0000\0"                                           \
 462         "ramdisk_addr=80300000\0"                                       \
 463         "u-boot=tqm834x/u-boot.bin\0"                                   \
 464         "load=tftp 200000 ${u-boot}\0"                                  \
 465         "update=protect off 80000000 +${filesize};"                     \
 466                 "era 80000000 +${filesize};"                            \
 467                 "cp.b 200000 80000000 ${filesize}\0"                    \
 468         "upd=run load update\0"                                         \
 469         ""
 470
 471 #define CONFIG_BOOTCOMMAND      "run flash_self"
 472
 473 /*
 474  * JFFS2 partitions
 475  */
 476 /* mtdparts command line support */
 477 #define CONFIG_FLASH_CFI_MTD
 478
 479 /* default mtd partition table */
 480 #endif  /* __CONFIG_H */