2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38 #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
40 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
42 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
43 #define BOOTFLAG_WARM 0x02 /* Software reboot */
45 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
46 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
47 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
51 * Serial console configuration
53 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
54 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
55 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
58 #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
59 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
60 #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
61 #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
62 #define CONFIG_BOARD_EARLY_INIT_R
63 #endif /* CONFIG_STK52XX */
65 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
68 * 0x40000000 - 0x4fffffff - PCI Memory
69 * 0x50000000 - 0x50ffffff - PCI IO Space
76 #define CONFIG_PCI_PNP 1
77 /* #define CONFIG_PCI_SCAN_SHOW 1 */
79 #define CONFIG_PCI_MEM_BUS 0x40000000
80 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
81 #define CONFIG_PCI_MEM_SIZE 0x10000000
83 #define CONFIG_PCI_IO_BUS 0x50000000
84 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
85 #define CONFIG_PCI_IO_SIZE 0x01000000
87 #define CONFIG_NET_MULTI 1
88 #define CONFIG_EEPRO100 1
89 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
90 #define CONFIG_NS8382X 1
93 #define ADD_PCI_CMD CFG_CMD_PCI
100 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
105 #undef CONFIG_MAC_PARTITION
106 #if defined (CONFIG_MINIFAP)
107 #define CONFIG_DOS_PARTITION
111 #ifdef CONFIG_STK52XX
112 #define CONFIG_USB_OHCI
113 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
114 #define CONFIG_DOS_PARTITION
115 #define CONFIG_USB_STORAGE
117 #define ADD_USB_CMD 0
121 #define CONFIG_POST (CFG_POST_MEMORY | \
126 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
127 /* preserve space for the post_word at end of on-chip SRAM */
128 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
130 #define CFG_CMD_POST_DIAG 0
134 #if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
135 #define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
137 #define ADD_IDE_CMD 0
143 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
148 CFG_CMD_POST_DIAG | \
155 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
156 #include <cmd_confdefs.h>
158 #if (TEXT_BASE == 0xFC000000) /* Boot low */
159 # define CFG_LOWBOOT 1
165 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
167 #define CONFIG_PREBOOT "echo;" \
168 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
171 #undef CONFIG_BOOTARGS
173 #if defined (CONFIG_TQM5200_AA)
174 #define CONFIG_EXTRA_ENV_SETTINGS \
176 "nfsargs=setenv bootargs root=/dev/nfs rw " \
177 "nfsroot=$(serverip):$(rootpath)\0" \
178 "ramargs=setenv bootargs root=/dev/ram rw\0" \
179 "addip=setenv bootargs $(bootargs) " \
180 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
181 ":$(hostname):$(netdev):off panic=1\0" \
182 "flash_nfs=run nfsargs addip;" \
183 "bootm $(kernel_addr)\0" \
184 "flash_self=run ramargs addip;" \
185 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
186 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
187 "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
188 "bootfile=uImage_tqm5200_mkr\0" \
189 "load=tftp 200000 $(loadfile)\0" \
190 "load133=tftp 200000 $(loadfile133)\0" \
191 "loadfile=u-boot_tqm5200_aa_mkr.bin\0" \
192 "loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0" \
193 "update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
194 "serverip=172.20.5.13\0" \
197 #if defined (CONFIG_TQM5200_AB)
198 #define CONFIG_EXTRA_ENV_SETTINGS \
200 "nfsargs=setenv bootargs root=/dev/nfs rw " \
201 "nfsroot=$(serverip):$(rootpath)\0" \
202 "ramargs=setenv bootargs root=/dev/ram rw\0" \
203 "addip=setenv bootargs $(bootargs) " \
204 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
205 ":$(hostname):$(netdev):off panic=1\0" \
206 "flash_nfs=run nfsargs addip;" \
207 "bootm $(kernel_addr)\0" \
208 "flash_self=run ramargs addip;" \
209 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
210 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
211 "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
212 "bootfile=uImage_tqm5200_mkr\0" \
213 "load=tftp 200000 $(loadfile)\0" \
214 "load133=tftp 200000 $(loadfile133)\0" \
215 "loadfile=u-boot_tqm5200_ab_mkr.bin\0" \
216 "loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0" \
217 "update=protect off 1:0-1; erase 1:0-1; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-1\0" \
218 "serverip=172.20.5.13\0" \
221 #if defined (CONFIG_TQM5200_AC)
222 #define CONFIG_EXTRA_ENV_SETTINGS \
224 "nfsargs=setenv bootargs root=/dev/nfs rw " \
225 "nfsroot=$(serverip):$(rootpath)\0" \
226 "ramargs=setenv bootargs root=/dev/ram rw\0" \
227 "addip=setenv bootargs $(bootargs) " \
228 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
229 ":$(hostname):$(netdev):off panic=1\0" \
230 "flash_nfs=run nfsargs addip;" \
231 "bootm $(kernel_addr)\0" \
232 "flash_self=run ramargs addip;" \
233 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
234 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
235 "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
236 "bootfile=uImage_tqm5200_mkr\0" \
237 "load=tftp 200000 $(loadfile)\0" \
238 "load133=tftp 200000 $(loadfile133)\0" \
239 "loadfile=u-boot_tqm5200_ac_mkr.bin\0" \
240 "loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0" \
241 "update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
242 "serverip=172.20.5.13\0" \
245 #define CONFIG_EXTRA_ENV_SETTINGS \
247 "nfsargs=setenv bootargs root=/dev/nfs rw " \
248 "nfsroot=$(serverip):$(rootpath)\0" \
249 "ramargs=setenv bootargs root=/dev/ram rw\0" \
250 "addip=setenv bootargs $(bootargs) " \
251 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
252 ":$(hostname):$(netdev):off panic=1\0" \
253 "flash_nfs=run nfsargs addip;" \
254 "bootm $(kernel_addr)\0" \
255 "flash_self=run ramargs addip;" \
256 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
257 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
258 "rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
259 "bootfile=uImage_tqm5200_mkr\0" \
260 "load=tftp 200000 $(loadfile)\0" \
261 "load133=tftp 200000 $(loadfile133)\0" \
262 "loadfile=u-boot_tqm5200_mkr.bin\0" \
263 "loadfile133=u-boot_tqm5200_133_mkr.bin\0" \
264 "update=protect off fc000000 fc03ffff; erase fc000000 fc03ffff; cp.b 200000 0xfc000000 $(filesize); protect on fc000000 fc03ffff\0" \
265 "serverip=172.20.5.13\0" \
271 #define CONFIG_BOOTCOMMAND "run net_nfs"
274 * IPB Bus clocking configuration.
276 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
278 #if defined(CFG_IPBSPEED_133)
280 * PCI Bus clocking configuration
282 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
283 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
284 * been tested with a IPB Bus Clock of 66 MHz.
286 #define CFG_PCISPEED_66 /* define for 66MHz speed */
292 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
293 #if defined (CONFIG_MINIFAP)
294 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
296 #define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
300 * I2C clock frequency
302 * Please notice, that the resulting clock frequency could differ from the
303 * configured value. This is because the I2C clock is derived from system
304 * clock over a frequency divider with only a few divider values. U-boot
305 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
306 * approximation allways lies below the configured value, never above.
308 #define CFG_I2C_SPEED 100000 /* 100 kHz */
309 #define CFG_I2C_SLAVE 0x7F
312 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
313 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
314 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
315 * same configuration could be used.
317 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
318 #define CFG_I2C_EEPROM_ADDR_LEN 2
319 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
320 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
323 * HW-Monitor configuration on Mini-FAP
325 #if defined (CONFIG_MINIFAP)
326 #define CFG_I2C_HWMON_ADDR 0x2C
329 /* List of I2C addresses to be verified by POST */
330 #if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
331 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
333 #elif defined (CONFIG_TQM5200_AC)
334 #define I2C_ADDR_LIST { CFG_I2C_SLAVE }
337 #if defined (CONFIG_MINIFAP)
339 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
340 CFG_I2C_HWMON_ADDR, \
345 * Flash configuration
347 #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
349 /* use CFI flash driver if no module variant is spezified */
350 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
351 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
352 #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
353 #define CFG_FLASH_EMPTY_INFO
354 #define CFG_FLASH_SIZE 0x02000000 /* 32 MByte */
355 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
357 #if !defined(CFG_LOWBOOT)
358 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
359 #else /* CFG_LOWBOOT */
360 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
361 #endif /* CFG_LOWBOOT */
362 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
364 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
365 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
369 * Environment settings
371 #define CFG_ENV_IS_IN_FLASH 1
372 #define CFG_ENV_SIZE 0x10000
373 #define CFG_ENV_SECT_SIZE 0x20000
374 #define CONFIG_ENV_OVERWRITE 1
379 #define CFG_MBAR 0xF0000000
380 #define CFG_SDRAM_BASE 0x00000000
381 #define CFG_DEFAULT_MBAR 0x80000000
383 /* Use ON-Chip SRAM until RAM will be available */
384 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
386 /* preserve space for the post_word at end of on-chip SRAM */
387 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
389 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
393 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
394 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
395 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
397 #define CFG_MONITOR_BASE TEXT_BASE
398 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
399 # define CFG_RAMBOOT 1
402 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
403 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
404 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
407 * Ethernet configuration
409 #define CONFIG_MPC5xxx_FEC 1
411 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
413 /* #define CONFIG_FEC_10MBIT 1 */
414 #define CONFIG_PHY_ADDR 0x00
419 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
420 * Bit 0 (mask: 0x80000000): 1
421 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
422 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
423 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
425 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
428 * use as UART. Pins PSC6_0 to PSC6_3 are used.
429 Bits 9:11 (mask: 0x00700000):
430 * 101 -> PSC6 : Extended POST test is not available
431 * on MINI-FAP and TQM5200_IB:
432 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
433 * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
434 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
437 #if defined (CONFIG_MINIFAP)
438 #define CFG_GPS_PORT_CONFIG 0x91300004
439 #elif defined (CONFIG_STK52XX)
440 #define CFG_GPS_PORT_CONFIG 0x81500004
442 #define CFG_GPS_PORT_CONFIG 0x81300004
448 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
451 * Miscellaneous configurable options
453 #define CFG_LONGHELP /* undef to save memory */
454 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
455 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
456 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
458 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
460 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
461 #define CFG_MAXARGS 16 /* max number of command args */
462 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
464 /* Enable an alternate, more extensive memory test */
465 #define CFG_ALT_MEMTEST
467 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
468 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
470 #define CFG_LOAD_ADDR 0x100000 /* default load address */
472 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
475 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
476 * which is normally part of the default commands (CFV_CMD_DFL)
481 * Various low-level settings
483 #if defined(CONFIG_MPC5200)
484 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
485 #define CFG_HID0_FINAL HID0_ICE
487 #define CFG_HID0_INIT 0
488 #define CFG_HID0_FINAL 0
491 #define CFG_BOOTCS_START CFG_FLASH_BASE
492 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
493 #ifdef CFG_PCISPEED_66
494 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
496 #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
498 #define CFG_CS0_START CFG_FLASH_BASE
499 #define CFG_CS0_SIZE CFG_FLASH_SIZE
501 /* automatic configuration of chip selects */
502 #ifdef CONFIG_CS_AUTOCONF
503 #define CONFIG_LAST_STAGE_INIT
507 * SRAM - Do not map below 2 GB in address space, because this area is used
508 * for SDRAM autosizing.
510 #if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
511 #define CFG_CS2_START 0xE5000000
512 #ifdef CONFIG_TQM5200_AB
513 #define CFG_CS2_SIZE 0x80000 /* 512 kByte */
514 #else /* CONFIG_CS_AUTOCONF */
515 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */
517 #define CFG_CS2_CFG 0x0004D930
521 * Grafic controller - Do not map below 2 GB in address space, because this
522 * area is used for SDRAM autosizing.
524 #if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
525 defined (CONFIG_CS_AUTOCONF)
526 #define CFG_CS1_START 0xE0000000
527 #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
528 #define CFG_CS1_CFG 0x8F48FF70
529 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
532 #define CFG_CS_BURST 0x00000000
533 #define CFG_CS_DEADCYCLE 0x33333333
535 #define CFG_RESET_ADDRESS 0xff000000
537 /*-----------------------------------------------------------------------
539 *-----------------------------------------------------------------------
541 #define CONFIG_USB_CLOCK 0x0001BBBB
542 #define CONFIG_USB_CONFIG 0x00001000
544 /*-----------------------------------------------------------------------
545 * IDE/ATA stuff Supports IDE harddisk
546 *-----------------------------------------------------------------------
549 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
551 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
552 #undef CONFIG_IDE_LED /* LED for ide not supported */
554 #define CONFIG_IDE_RESET /* reset for ide supported */
555 #define CONFIG_IDE_PREINIT
557 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
558 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
560 #define CFG_ATA_IDE0_OFFSET 0x0000
562 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
564 /* Offset for data I/O */
565 #define CFG_ATA_DATA_OFFSET (0x0060)
567 /* Offset for normal register accesses */
568 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
570 /* Offset for alternate registers */
571 #define CFG_ATA_ALT_OFFSET (0x005C)
573 /* Interval between registers */
574 #define CFG_ATA_STRIDE 4
576 #endif /* __CONFIG_H */