3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
7 * TOP5200 differences from IceCube:
8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
10 * 1 SDRAM/DDRAM Bank up to 256 MB
11 * local VPD I2C Bus is software driven and uses
12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
13 * FLASH is re-located at 0xff000000
14 * Internal regs are at 0xf0000000
15 * Reset jumps to 0x00000100
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * High Level Configuration Options
44 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
45 #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
46 #define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
49 * allowed and functional CONFIG_SYS_TEXT_BASE values:
50 * 0xff000000 low boot at 0x00000100 (default board setting)
51 * 0xfff00000 high boot at 0xfff00100 (board needs modification)
52 * 0x00100000 RAM load and test
54 #define CONFIG_SYS_TEXT_BASE 0xff000000
56 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
58 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
59 #define BOOTFLAG_WARM 0x02 /* Software reboot */
61 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
64 * Serial console configuration
66 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
67 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
68 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
71 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
74 * 0x40000000 - 0x4fffffff - PCI Memory
75 * 0x50000000 - 0x50ffffff - PCI IO Space
78 # define CONFIG_PCI_PNP 1
79 # define CONFIG_PCI_SCAN_SHOW 1
80 # define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
82 # define CONFIG_PCI_MEM_BUS 0x40000000
83 # define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
84 # define CONFIG_PCI_MEM_SIZE 0x10000000
86 # define CONFIG_PCI_IO_BUS 0x50000000
87 # define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
88 # define CONFIG_PCI_IO_SIZE 0x01000000
93 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
95 # define CONFIG_USB_OHCI
96 # define CONFIG_USB_CLOCK 0x0001bbbb
97 # if defined (CONFIG_EVAL5200)
98 # define CONFIG_USB_CONFIG 0x00005100
100 # define CONFIG_USB_CONFIG 0x00001000
102 # define CONFIG_DOS_PARTITION
103 # define CONFIG_USB_STORAGE
108 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
109 # define CONFIG_DOS_PARTITION
116 #define CONFIG_BOOTP_BOOTFILESIZE
117 #define CONFIG_BOOTP_BOOTPATH
118 #define CONFIG_BOOTP_GATEWAY
119 #define CONFIG_BOOTP_HOSTNAME
123 * Command line configuration.
125 #include <config_cmd_default.h>
127 #define CONFIG_CMD_ASKENV
128 #define CONFIG_CMD_BEDBUG
129 #define CONFIG_CMD_DATE
130 #define CONFIG_CMD_DHCP
131 #define CONFIG_CMD_EEPROM
132 #define CONFIG_CMD_ELF
133 #define CONFIG_CMD_I2C
134 #define CONFIG_CMD_IMMAP
135 #define CONFIG_CMD_MII
136 #define CONFIG_CMD_REGINFO
138 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
139 #define CONFIG_CMD_FAT
140 #define CONFIG_CMD_IDE
141 #define CONFIG_CMD_USB
142 #define CONFIG_CMD_PCI
147 * MUST be low boot - HIGHBOOT is not supported anymore
149 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
150 # define CONFIG_SYS_LOWBOOT 1
151 # define CONFIG_SYS_LOWBOOT16 1
153 # error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
159 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
161 #define CONFIG_PREBOOT "echo;" \
162 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
165 #undef CONFIG_BOOTARGS
167 #define CONFIG_EXTRA_ENV_SETTINGS \
169 "nfsargs=setenv bootargs root=/dev/nfs rw " \
170 "nfsroot=${serverip}:${rootpath}\0" \
171 "ramargs=setenv bootargs root=/dev/ram rw\0" \
172 "addip=setenv bootargs ${bootargs} " \
173 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
174 ":${hostname}:${netdev}:off panic=1\0" \
175 "flash_nfs=run nfsargs addip;" \
176 "bootm ${kernel_addr}\0" \
177 "flash_self=run ramargs addip;" \
178 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
179 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
180 "rootpath=/opt/eldk/ppc_82xx\0" \
181 "bootfile=/tftpboot/MPC5200/uImage\0" \
184 #define CONFIG_BOOTCOMMAND "run flash_self"
187 * IPB Bus clocking configuration.
189 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
195 * EEPROM configuration
197 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
198 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
200 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
201 #define CONFIG_SYS_EEPROM_SIZE 0x2000
203 #define CONFIG_ENV_OVERWRITE
204 #define CONFIG_MISC_INIT_R
206 #undef CONFIG_HARD_I2C /* I2C with hardware support */
207 #define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
209 #if defined (CONFIG_SOFT_I2C)
212 # define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
213 # define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
214 # define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
215 # define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
216 # define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
217 # define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
218 # define I2C_READ ((DVI0&SDA0)?1:0)
219 # define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
220 # define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
221 # define I2C_DELAY {udelay(5);}
222 # define I2C_ACTIVE {DDR0|=SDA0;}
223 # define I2C_TRISTATE {DDR0&=~SDA0;}
224 # define CONFIG_SYS_I2C_SPEED 100000
225 # define CONFIG_SYS_I2C_SLAVE 0x7F
226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
227 #define CONFIG_SYS_I2C_FACT_ADDR 0x57
230 #if defined (CONFIG_HARD_I2C)
231 # define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
232 # define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
233 # define CONFIG_SYS_I2C_SLAVE 0x7F
234 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
235 #define CONFIG_SYS_I2C_FACT_ADDR 0x54
239 * Flash configuration, expect one 16 Megabyte Bank at most
241 #define CONFIG_SYS_FLASH_BASE 0xff000000
242 #define CONFIG_SYS_FLASH_SIZE 0x01000000
243 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
244 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
246 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
248 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
249 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
251 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
254 * DRAM configuration - will be read from VPD later... TODO!
257 /* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
258 #define CONFIG_SYS_DRAM_DDR 0
259 #define CONFIG_SYS_DRAM_EMODE 0
260 #define CONFIG_SYS_DRAM_MODE 0x008D
261 #define CONFIG_SYS_DRAM_CONTROL 0x514F0000
262 #define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00
263 #define CONFIG_SYS_DRAM_CONFIG2 0x88B70004
264 #define CONFIG_SYS_DRAM_TAP_DEL 0x08
265 #define CONFIG_SYS_DRAM_RAM_SIZE 0x19
268 /* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
269 #define CONFIG_SYS_DRAM_DDR 0
270 #define CONFIG_SYS_DRAM_EMODE 0
271 #define CONFIG_SYS_DRAM_MODE 0x00CD
272 #define CONFIG_SYS_DRAM_CONTROL 0x514F0000
273 #define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00
274 #define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004
275 #define CONFIG_SYS_DRAM_TAP_DEL 0x08
276 #define CONFIG_SYS_DRAM_RAM_SIZE 0x19
280 * Environment settings
282 #define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
283 #define CONFIG_ENV_OFFSET 0x1000
284 #define CONFIG_ENV_SIZE 0x0700
289 #define CONFIG_SYS_FACT_OFFSET 0x1800
290 #define CONFIG_SYS_FACT_SIZE 0x0800
295 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
297 #define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
298 #define CONFIG_SYS_SDRAM_BASE 0x00000000
299 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
301 /* Use SRAM until RAM will be available */
302 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
303 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
306 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
307 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
308 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
310 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
311 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
312 # define CONFIG_SYS_RAMBOOT 1
315 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
316 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
317 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
320 * Ethernet configuration
322 #define CONFIG_MPC5xxx_FEC 1
323 #define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */
324 #define CONFIG_PHY_ADDR 0x1f
325 #define CONFIG_PHY_TYPE 0x79c874
327 * GPIO configuration:
328 * PSC1,2,3 predefined as UART
330 * Ethernet 100 with MD
332 #define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044
335 * Miscellaneous configurable options
337 #define CONFIG_SYS_LONGHELP /* undef to save memory */
338 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
339 #if defined(CONFIG_CMD_KGDB)
340 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
342 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
344 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
345 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
346 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
348 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
349 #define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
351 #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
353 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
355 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
356 #if defined(CONFIG_CMD_KGDB)
357 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
361 #ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
362 #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
363 #define RTC(reg) (0xf0010000+reg)
364 /* setup CS2 for M48T08. Must MAP 64kB */
365 #define CONFIG_SYS_CS2_START RTC(0)
366 #define CONFIG_SYS_CS2_SIZE 0x10000
367 /* setup CS2 configuration register: */
368 /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
369 /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
370 #define CONFIG_SYS_CS2_CFG 0x00047800
372 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
376 * Various low-level settings
378 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
379 #define CONFIG_SYS_HID0_FINAL HID0_ICE
381 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
382 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
383 #define CONFIG_SYS_BOOTCS_CFG 0x00047801
384 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
385 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
387 #define CONFIG_SYS_CS_BURST 0x00000000
388 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
390 #define CONFIG_SYS_RESET_ADDRESS 0x7f000000
392 /*-----------------------------------------------------------------------
393 * IDE/ATA stuff Supports IDE harddisk
394 *-----------------------------------------------------------------------
397 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
399 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
400 #undef CONFIG_IDE_LED /* LED for ide not supported */
402 #define CONFIG_IDE_RESET 1
403 #define CONFIG_IDE_PREINIT
405 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
406 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
408 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
410 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
412 /* Offset for data I/O */
413 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
415 /* Offset for normal register accesses */
416 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
418 /* Offset for alternate registers */
419 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005c)
421 /* Interval between registers */
422 #define CONFIG_SYS_ATA_STRIDE 4
424 #endif /* __CONFIG_H */