3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
7 * TOP5200 differences from IceCube:
8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
10 * 1 SDRAM/DDRAM Bank up to 256 MB
11 * local VPD I2C Bus is software driven and uses
12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
13 * FLASH is re-located at 0xff000000
14 * Internal regs are at 0xf0000000
15 * Reset jumps to 0x00000100
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * High Level Configuration Options
44 #define CONFIG_MPC5XXX 1 /* This is an MPC5xxx CPU */
45 #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
46 #define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
48 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
50 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51 #define BOOTFLAG_WARM 0x02 /* Software reboot */
53 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
54 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
55 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
59 * Serial console configuration
61 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
62 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
63 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
66 #ifdef CONFIG_EVAL5200 /* PCI is supported with Evaluation board only */
69 * 0x40000000 - 0x4fffffff - PCI Memory
70 * 0x50000000 - 0x50ffffff - PCI IO Space
73 # define CONFIG_PCI_PNP 1
74 # define CONFIG_PCI_SCAN_SHOW 1
76 # define CONFIG_PCI_MEM_BUS 0x40000000
77 # define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
78 # define CONFIG_PCI_MEM_SIZE 0x10000000
80 # define CONFIG_PCI_IO_BUS 0x50000000
81 # define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
82 # define CONFIG_PCI_IO_SIZE 0x01000000
84 # define ADD_PCI_CMD CFG_CMD_PCI
86 #else /* no Evaluation board */
88 # define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
95 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
109 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
110 #include <cmd_confdefs.h>
115 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
116 # define CFG_LOWBOOT 1
117 # define CFG_LOWBOOT16 1
123 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
125 #define CONFIG_PREBOOT "echo;" \
126 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
129 #undef CONFIG_BOOTARGS
131 #define CONFIG_EXTRA_ENV_SETTINGS \
133 "nfsargs=setenv bootargs root=/dev/nfs rw " \
134 "nfsroot=$(serverip):$(rootpath)\0" \
135 "ramargs=setenv bootargs root=/dev/ram rw\0" \
136 "addip=setenv bootargs $(bootargs) " \
137 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
138 ":$(hostname):$(netdev):off panic=1\0" \
139 "flash_nfs=run nfsargs addip;" \
140 "bootm $(kernel_addr)\0" \
141 "flash_self=run ramargs addip;" \
142 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
143 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
144 "rootpath=/opt/eldk/ppc_82xx\0" \
145 "bootfile=/tftpboot/MPC5200/uImage\0" \
148 #define CONFIG_BOOTCOMMAND "run flash_self"
151 * IPB Bus clocking configuration.
153 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
159 * EEPROM configuration
161 #define CFG_EEPROM_PAGE_WRITE_BITS 3
162 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
164 #define CFG_I2C_EEPROM_ADDR_LEN 2
165 #define CFG_EEPROM_SIZE 0x2000
167 #define CONFIG_ENV_OVERWRITE
168 #define CONFIG_MISC_INIT_R
170 #undef CONFIG_HARD_I2C /* I2C with hardware support */
171 #define CONFIG_SOFT_I2C 1
173 #if defined (CONFIG_SOFT_I2C)
176 # define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00))
177 # define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08))
178 # define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c))
179 # define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20))
180 # define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04))
181 # define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
182 # define I2C_READ ((DVI0&SDA0)?1:0)
183 # define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
184 # define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
185 # define I2C_DELAY {udelay(5);}
186 # define I2C_ACTIVE {DDR0|=SDA0;}
187 # define I2C_TRISTATE {DDR0&=~SDA0;}
188 # define CFG_I2C_SPEED 100000
189 # define CFG_I2C_SLAVE 0x7F
192 #if defined (CONFIG_HARD_I2C)
193 # define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
194 # define CFG_I2C_SPEED 100000 /* 100 kHz */
195 # define CFG_I2C_SLAVE 0x7F
199 * Flash configuration, expect one 16 Megabyte Bank at most
201 #define CFG_FLASH_BASE 0xff000000
202 #define CFG_FLASH_SIZE 0x01000000
203 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
204 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
206 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
208 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
209 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
211 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
214 * DRAM configuration - will be read from VPD later... TODO!
217 /* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
218 #define CFG_DRAM_DDR 0
219 #define CFG_DRAM_EMODE 0
220 #define CFG_DRAM_MODE 0x008D
221 #define CFG_DRAM_CONTROL 0x514F0000
222 #define CFG_DRAM_CONFIG1 0xC2233A00
223 #define CFG_DRAM_CONFIG2 0x88B70004
224 #define CFG_DRAM_TAP_DEL 0x08
225 #define CFG_DRAM_RAM_SIZE 0x19
228 /* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
229 #define CFG_DRAM_DDR 0
230 #define CFG_DRAM_EMODE 0
231 #define CFG_DRAM_MODE 0x00CD
232 #define CFG_DRAM_CONTROL 0x514F0000
233 #define CFG_DRAM_CONFIG1 0xD2333A00
234 #define CFG_DRAM_CONFIG2 0x8AD70004
235 #define CFG_DRAM_TAP_DEL 0x08
236 #define CFG_DRAM_RAM_SIZE 0x19
240 * Environment settings
242 #define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
243 #define CFG_ENV_OFFSET 0x1000
244 #define CFG_ENV_SIZE 0x0700
245 #define CFG_I2C_EEPROM_ADDR 0x57
250 #define CFG_FACT_OFFSET 0x1800
251 #define CFG_FACT_SIZE 0x0800
252 #define CFG_I2C_FACT_ADDR 0x57
257 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
259 #define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
260 #define CFG_SDRAM_BASE 0x00000000
261 #define CFG_DEFAULT_MBAR 0x80000000
263 /* Use SRAM until RAM will be available */
264 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
265 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
268 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
269 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
270 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
272 #define CFG_MONITOR_BASE TEXT_BASE
273 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
274 # define CFG_RAMBOOT 1
277 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
278 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
279 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
282 * Ethernet configuration
284 #define CONFIG_MPC5XXX_FEC 1
285 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
286 #define CONFIG_PHY_ADDR 0x1f
287 #define CONFIG_PHY_TYPE 0x79c874
289 * GPIO configuration:
290 * PSC1,2,3 predefined as UART
292 * Ethernet 100 with MD
294 #define CFG_GPS_PORT_CONFIG 0x00058444
297 * Miscellaneous configurable options
299 #define CFG_LONGHELP /* undef to save memory */
300 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
301 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
302 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
304 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
306 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
307 #define CFG_MAXARGS 16 /* max number of command args */
308 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
310 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
311 #define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
313 #define CFG_LOAD_ADDR 0x100000 /* default load address */
315 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
317 #define CONFIG_RTC_MPC5200 1 /* use 5200 RTC */
320 * Various low-level settings
322 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
323 #define CFG_HID0_FINAL HID0_ICE
325 #define CFG_BOOTCS_START CFG_FLASH_BASE
326 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
327 #define CFG_BOOTCS_CFG 0x00047801
328 #define CFG_CS0_START CFG_FLASH_BASE
329 #define CFG_CS0_SIZE CFG_FLASH_SIZE
331 #define CFG_CS_BURST 0x00000000
332 #define CFG_CS_DEADCYCLE 0x33333333
334 #define CFG_RESET_ADDRESS 0x7f000000
336 #endif /* __CONFIG_H */