ARM: configs: Add da850evm_nand to boot from NAND
[oweals/u-boot.git] / include / configs / T4240RDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * T4240 RDB board configuration file
8  */
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #define CONFIG_FSL_SATA_V2
13 #define CONFIG_PCIE4
14
15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
16
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
19 #ifndef CONFIG_SDCARD
20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
22 #else
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
25 #define CONFIG_SPL_PAD_TO               0x40000
26 #define CONFIG_SPL_MAX_SIZE             0x28000
27 #define RESET_VECTOR_OFFSET             0x27FFC
28 #define BOOT_PAGE_OFFSET                0x27000
29
30 #ifdef  CONFIG_SDCARD
31 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
32 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
33 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
34 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
35 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
36 #ifndef CONFIG_SPL_BUILD
37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
38 #endif
39 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
40 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
41 #define CONFIG_SPL_MMC_BOOT
42 #endif
43
44 #ifdef CONFIG_SPL_BUILD
45 #define CONFIG_SPL_SKIP_RELOCATE
46 #define CONFIG_SPL_COMMON_INIT_DDR
47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
48 #endif
49
50 #endif
51 #endif /* CONFIG_RAMBOOT_PBL */
52
53 #define CONFIG_DDR_ECC
54
55 /* High Level Configuration Options */
56 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
57
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
60 #endif
61
62 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
64 #define CONFIG_PCIE1                    /* PCIE controller 1 */
65 #define CONFIG_PCIE2                    /* PCIE controller 2 */
66 #define CONFIG_PCIE3                    /* PCIE controller 3 */
67 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
68 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
69
70 #define CONFIG_ENV_OVERWRITE
71
72 /*
73  * These can be toggled for performance analysis, otherwise use default.
74  */
75 #define CONFIG_SYS_CACHE_STASHING
76 #define CONFIG_BTB                      /* toggle branch predition */
77 #ifdef CONFIG_DDR_ECC
78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
79 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
80 #endif
81
82 #define CONFIG_ENABLE_36BIT_PHYS
83
84 #define CONFIG_ADDR_MAP
85 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
86
87 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
88 #define CONFIG_SYS_MEMTEST_END          0x00400000
89
90 /*
91  *  Config the L3 Cache as L3 SRAM
92  */
93 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
94 #define CONFIG_SYS_L3_SIZE              (512 << 10)
95 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
96 #ifdef CONFIG_RAMBOOT_PBL
97 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
98 #endif
99 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
100 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
101 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
102
103 #define CONFIG_SYS_DCSRBAR              0xf0000000
104 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
105
106 /*
107  * DDR Setup
108  */
109 #define CONFIG_VERY_BIG_RAM
110 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
111 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
112
113 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
114 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
115 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
116
117 #define CONFIG_DDR_SPD
118
119 /*
120  * IFC Definitions
121  */
122 #define CONFIG_SYS_FLASH_BASE   0xe0000000
123 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
124
125 #ifdef CONFIG_SPL_BUILD
126 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
127 #else
128 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
129 #endif
130
131 #define CONFIG_HWCONFIG
132
133 /* define to use L1 as initial stack */
134 #define CONFIG_L1_INIT_RAM
135 #define CONFIG_SYS_INIT_RAM_LOCK
136 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
137 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
138 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
139 /* The assembler doesn't like typecast */
140 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
141         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
142           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
143 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
144
145 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
146                                         GENERATED_GBL_DATA_SIZE)
147 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
148
149 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
150 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
151
152 /* Serial Port - controlled on board with jumper J8
153  * open - index 2
154  * shorted - index 1
155  */
156 #define CONFIG_SYS_NS16550_SERIAL
157 #define CONFIG_SYS_NS16550_REG_SIZE     1
158 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
159
160 #define CONFIG_SYS_BAUDRATE_TABLE       \
161         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
162
163 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
164 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
165 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
166 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
167
168 /* I2C */
169 #define CONFIG_SYS_I2C
170 #define CONFIG_SYS_I2C_FSL
171 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
172 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
173 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
174 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
175
176 /*
177  * General PCI
178  * Memory space is mapped 1-1, but I/O space must start from 0.
179  */
180
181 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
182 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
183 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
184 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
185 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
186 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
187 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
188 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
189 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
190
191 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
192 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
193 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
194 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
195 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
196 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
197 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
198 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
199 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
200
201 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
202 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
203 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
204 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
205 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
206 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
207 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
208 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
209 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
210
211 /* controller 4, Base address 203000 */
212 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
213 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
214 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
215 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
216 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
217 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
218
219 #ifdef CONFIG_PCI
220 #define CONFIG_PCI_INDIRECT_BRIDGE
221
222 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
223 #endif  /* CONFIG_PCI */
224
225 /* SATA */
226 #ifdef CONFIG_FSL_SATA_V2
227 #define CONFIG_SYS_SATA_MAX_DEVICE      2
228 #define CONFIG_SATA1
229 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
230 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
231 #define CONFIG_SATA2
232 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
233 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
234
235 #define CONFIG_LBA48
236 #endif
237
238 #ifdef CONFIG_FMAN_ENET
239 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
240 #endif
241
242 /*
243  * Environment
244  */
245 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
246 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
247
248 /*
249  * Command line configuration.
250  */
251
252 /*
253  * Miscellaneous configurable options
254  */
255 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
256
257 /*
258  * For booting Linux, the board info and command line data
259  * have to be in the first 64 MB of memory, since this is
260  * the maximum mapped by the Linux kernel during initialization.
261  */
262 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
263 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
264
265 #ifdef CONFIG_CMD_KGDB
266 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
267 #endif
268
269 /*
270  * Environment Configuration
271  */
272 #define CONFIG_ROOTPATH         "/opt/nfsroot"
273 #define CONFIG_BOOTFILE         "uImage"
274 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
275
276 /* default location for tftp and bootm */
277 #define CONFIG_LOADADDR         1000000
278
279 #define CONFIG_HVBOOT                                   \
280         "setenv bootargs config-addr=0x60000000; "      \
281         "bootm 0x01000000 - 0x00f00000"
282
283 #ifndef CONFIG_MTD_NOR_FLASH
284 #else
285 #define CONFIG_FLASH_CFI_DRIVER
286 #define CONFIG_SYS_FLASH_CFI
287 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
288 #endif
289
290 #if defined(CONFIG_SPIFLASH)
291 #define CONFIG_SYS_EXTRA_ENV_RELOC
292 #define CONFIG_ENV_SPI_BUS              0
293 #define CONFIG_ENV_SPI_CS               0
294 #define CONFIG_ENV_SPI_MAX_HZ           10000000
295 #define CONFIG_ENV_SPI_MODE             0
296 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
297 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
298 #define CONFIG_ENV_SECT_SIZE            0x10000
299 #elif defined(CONFIG_SDCARD)
300 #define CONFIG_SYS_EXTRA_ENV_RELOC
301 #define CONFIG_SYS_MMC_ENV_DEV          0
302 #define CONFIG_ENV_SIZE                 0x2000
303 #define CONFIG_ENV_OFFSET               (512 * 0x800)
304 #elif defined(CONFIG_NAND)
305 #define CONFIG_SYS_EXTRA_ENV_RELOC
306 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
307 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
308 #elif defined(CONFIG_ENV_IS_NOWHERE)
309 #define CONFIG_ENV_SIZE         0x2000
310 #else
311 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
312 #define CONFIG_ENV_SIZE         0x2000
313 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
314 #endif
315
316 #define CONFIG_SYS_CLK_FREQ     66666666
317 #define CONFIG_DDR_CLK_FREQ     133333333
318
319 #ifndef __ASSEMBLY__
320 unsigned long get_board_sys_clk(void);
321 unsigned long get_board_ddr_clk(void);
322 #endif
323
324 /*
325  * DDR Setup
326  */
327 #define CONFIG_SYS_SPD_BUS_NUM  0
328 #define SPD_EEPROM_ADDRESS1     0x52
329 #define SPD_EEPROM_ADDRESS2     0x54
330 #define SPD_EEPROM_ADDRESS3     0x56
331 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
332 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
333
334 /*
335  * IFC Definitions
336  */
337 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
338 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
339                                 + 0x8000000) | \
340                                 CSPR_PORT_SIZE_16 | \
341                                 CSPR_MSEL_NOR | \
342                                 CSPR_V)
343 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
344 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
345                                 CSPR_PORT_SIZE_16 | \
346                                 CSPR_MSEL_NOR | \
347                                 CSPR_V)
348 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
349 /* NOR Flash Timing Params */
350 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
351
352 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
353                                 FTIM0_NOR_TEADC(0x5) | \
354                                 FTIM0_NOR_TEAHC(0x5))
355 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
356                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
357                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
358 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
359                                 FTIM2_NOR_TCH(0x4) | \
360                                 FTIM2_NOR_TWPH(0x0E) | \
361                                 FTIM2_NOR_TWP(0x1c))
362 #define CONFIG_SYS_NOR_FTIM3    0x0
363
364 #define CONFIG_SYS_FLASH_QUIET_TEST
365 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
366
367 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
368 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
369 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
370 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
371
372 #define CONFIG_SYS_FLASH_EMPTY_INFO
373 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
374                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
375
376 /* NAND Flash on IFC */
377 #define CONFIG_NAND_FSL_IFC
378 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
379 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
380 #define CONFIG_SYS_NAND_BASE            0xff800000
381 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
382
383 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
384 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
385                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
386                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
387                                 | CSPR_V)
388 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
389
390 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
391                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
392                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
393                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
394                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
395                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
396                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
397
398 #define CONFIG_SYS_NAND_ONFI_DETECTION
399
400 /* ONFI NAND Flash mode0 Timing Params */
401 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
402                                         FTIM0_NAND_TWP(0x18)   | \
403                                         FTIM0_NAND_TWCHT(0x07) | \
404                                         FTIM0_NAND_TWH(0x0a))
405 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
406                                         FTIM1_NAND_TWBE(0x39)  | \
407                                         FTIM1_NAND_TRR(0x0e)   | \
408                                         FTIM1_NAND_TRP(0x18))
409 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
410                                         FTIM2_NAND_TREH(0x0a) | \
411                                         FTIM2_NAND_TWHRE(0x1e))
412 #define CONFIG_SYS_NAND_FTIM3           0x0
413
414 #define CONFIG_SYS_NAND_DDR_LAW         11
415 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
416 #define CONFIG_SYS_MAX_NAND_DEVICE      1
417
418 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
419
420 #if defined(CONFIG_NAND)
421 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
422 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
423 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
424 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
425 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
426 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
427 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
428 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
429 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
430 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
431 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
432 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
433 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
434 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
435 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
436 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
437 #else
438 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
439 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
440 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
441 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
442 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
443 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
444 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
445 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
446 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
447 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
448 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
449 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
450 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
451 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
452 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
453 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
454 #endif
455 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
456 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
457 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
458 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
459 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
460 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
461 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
462 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
463
464 /* CPLD on IFC */
465 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
466 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
467 #define CONFIG_SYS_CSPR3_EXT    (0xf)
468 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
469                                 | CSPR_PORT_SIZE_8 \
470                                 | CSPR_MSEL_GPCM \
471                                 | CSPR_V)
472
473 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
474 #define CONFIG_SYS_CSOR3        0x0
475
476 /* CPLD Timing parameters for IFC CS3 */
477 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
478                                         FTIM0_GPCM_TEADC(0x0e) | \
479                                         FTIM0_GPCM_TEAHC(0x0e))
480 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
481                                         FTIM1_GPCM_TRAD(0x1f))
482 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
483                                         FTIM2_GPCM_TCH(0x8) | \
484                                         FTIM2_GPCM_TWP(0x1f))
485 #define CONFIG_SYS_CS3_FTIM3            0x0
486
487 #if defined(CONFIG_RAMBOOT_PBL)
488 #define CONFIG_SYS_RAMBOOT
489 #endif
490
491 /* I2C */
492 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
493 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
494 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
495 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
496
497 #define I2C_MUX_CH_DEFAULT      0x8
498 #define I2C_MUX_CH_VOL_MONITOR  0xa
499 #define I2C_MUX_CH_VSC3316_FS   0xc
500 #define I2C_MUX_CH_VSC3316_BS   0xd
501
502 /* Voltage monitor on channel 2*/
503 #define I2C_VOL_MONITOR_ADDR            0x40
504 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
505 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
506 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
507
508 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
509 #ifndef CONFIG_SPL_BUILD
510 #define CONFIG_VID
511 #endif
512 #define CONFIG_VOL_MONITOR_IR36021_SET
513 #define CONFIG_VOL_MONITOR_IR36021_READ
514 /* The lowest and highest voltage allowed for T4240RDB */
515 #define VDD_MV_MIN                      819
516 #define VDD_MV_MAX                      1212
517
518 /*
519  * eSPI - Enhanced SPI
520  */
521 #define CONFIG_SF_DEFAULT_SPEED         10000000
522 #define CONFIG_SF_DEFAULT_MODE          0
523
524 /* Qman/Bman */
525 #ifndef CONFIG_NOBQFMAN
526 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
527 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
528 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
529 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
530 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
531 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
532 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
533 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
534 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
535                                         CONFIG_SYS_BMAN_CENA_SIZE)
536 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
537 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
538 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
539 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
540 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
541 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
542 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
543 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
544 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
545 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
546 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
547                                         CONFIG_SYS_QMAN_CENA_SIZE)
548 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
549 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
550
551 #define CONFIG_SYS_DPAA_FMAN
552 #define CONFIG_SYS_DPAA_PME
553 #define CONFIG_SYS_PMAN
554 #define CONFIG_SYS_DPAA_DCE
555 #define CONFIG_SYS_DPAA_RMAN
556 #define CONFIG_SYS_INTERLAKEN
557
558 /* Default address of microcode for the Linux Fman driver */
559 #if defined(CONFIG_SPIFLASH)
560 /*
561  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
562  * env, so we got 0x110000.
563  */
564 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
565 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
566 #elif defined(CONFIG_SDCARD)
567 /*
568  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
569  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
570  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
571  */
572 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
573 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
574 #elif defined(CONFIG_NAND)
575 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
576 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
577 #else
578 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
579 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
580 #endif
581 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
582 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
583 #endif /* CONFIG_NOBQFMAN */
584
585 #ifdef CONFIG_SYS_DPAA_FMAN
586 #define CONFIG_FMAN_ENET
587 #define CONFIG_PHYLIB_10G
588 #define CONFIG_PHY_VITESSE
589 #define CONFIG_PHY_CORTINA
590 #define CONFIG_SYS_CORTINA_FW_IN_NOR
591 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
592 #define CONFIG_CORTINA_FW_LENGTH        0x40000
593 #define CONFIG_PHY_TERANETICS
594 #define SGMII_PHY_ADDR1 0x0
595 #define SGMII_PHY_ADDR2 0x1
596 #define SGMII_PHY_ADDR3 0x2
597 #define SGMII_PHY_ADDR4 0x3
598 #define SGMII_PHY_ADDR5 0x4
599 #define SGMII_PHY_ADDR6 0x5
600 #define SGMII_PHY_ADDR7 0x6
601 #define SGMII_PHY_ADDR8 0x7
602 #define FM1_10GEC1_PHY_ADDR     0x10
603 #define FM1_10GEC2_PHY_ADDR     0x11
604 #define FM2_10GEC1_PHY_ADDR     0x12
605 #define FM2_10GEC2_PHY_ADDR     0x13
606 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
607 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
608 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
609 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
610 #endif
611
612 /* SATA */
613 #ifdef CONFIG_FSL_SATA_V2
614 #define CONFIG_SYS_SATA_MAX_DEVICE      2
615 #define CONFIG_SATA1
616 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
617 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
618 #define CONFIG_SATA2
619 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
620 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
621
622 #define CONFIG_LBA48
623 #endif
624
625 #ifdef CONFIG_FMAN_ENET
626 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
627 #endif
628
629 /*
630 * USB
631 */
632 #define CONFIG_USB_EHCI_FSL
633 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
634 #define CONFIG_HAS_FSL_DR_USB
635
636 #ifdef CONFIG_MMC
637 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
638 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
639 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
640 #endif
641
642
643 #define __USB_PHY_TYPE  utmi
644
645 /*
646  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
647  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
648  * interleaving. It can be cacheline, page, bank, superbank.
649  * See doc/README.fsl-ddr for details.
650  */
651 #ifdef CONFIG_ARCH_T4240
652 #define CTRL_INTLV_PREFERED 3way_4KB
653 #else
654 #define CTRL_INTLV_PREFERED cacheline
655 #endif
656
657 #define CONFIG_EXTRA_ENV_SETTINGS                               \
658         "hwconfig=fsl_ddr:"                                     \
659         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
660         "bank_intlv=auto;"                                      \
661         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
662         "netdev=eth0\0"                                         \
663         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
664         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
665         "tftpflash=tftpboot $loadaddr $uboot && "               \
666         "protect off $ubootaddr +$filesize && "                 \
667         "erase $ubootaddr +$filesize && "                       \
668         "cp.b $loadaddr $ubootaddr $filesize && "               \
669         "protect on $ubootaddr +$filesize && "                  \
670         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
671         "consoledev=ttyS0\0"                                    \
672         "ramdiskaddr=2000000\0"                                 \
673         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
674         "fdtaddr=1e00000\0"                                     \
675         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
676         "bdev=sda3\0"
677
678 #define CONFIG_HVBOOT                                   \
679         "setenv bootargs config-addr=0x60000000; "      \
680         "bootm 0x01000000 - 0x00f00000"
681
682 #define CONFIG_LINUX                                    \
683         "setenv bootargs root=/dev/ram rw "             \
684         "console=$consoledev,$baudrate $othbootargs;"   \
685         "setenv ramdiskaddr 0x02000000;"                \
686         "setenv fdtaddr 0x00c00000;"                    \
687         "setenv loadaddr 0x1000000;"                    \
688         "bootm $loadaddr $ramdiskaddr $fdtaddr"
689
690 #define CONFIG_HDBOOT                                   \
691         "setenv bootargs root=/dev/$bdev rw "           \
692         "console=$consoledev,$baudrate $othbootargs;"   \
693         "tftp $loadaddr $bootfile;"                     \
694         "tftp $fdtaddr $fdtfile;"                       \
695         "bootm $loadaddr - $fdtaddr"
696
697 #define CONFIG_NFSBOOTCOMMAND                   \
698         "setenv bootargs root=/dev/nfs rw "     \
699         "nfsroot=$serverip:$rootpath "          \
700         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
701         "console=$consoledev,$baudrate $othbootargs;"   \
702         "tftp $loadaddr $bootfile;"             \
703         "tftp $fdtaddr $fdtfile;"               \
704         "bootm $loadaddr - $fdtaddr"
705
706 #define CONFIG_RAMBOOTCOMMAND                           \
707         "setenv bootargs root=/dev/ram rw "             \
708         "console=$consoledev,$baudrate $othbootargs;"   \
709         "tftp $ramdiskaddr $ramdiskfile;"               \
710         "tftp $loadaddr $bootfile;"                     \
711         "tftp $fdtaddr $fdtfile;"                       \
712         "bootm $loadaddr $ramdiskaddr $fdtaddr"
713
714 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
715
716 #include <asm/fsl_secure_boot.h>
717
718 #endif  /* __CONFIG_H */