2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 RDB board configuration file
13 #define CONFIG_T4240RDB
14 #define CONFIG_PHYS_64BIT
15 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_FSL_SATA_V2
21 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
23 #ifdef CONFIG_RAMBOOT_PBL
24 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
27 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
30 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
31 #define CONFIG_SPL_ENV_SUPPORT
32 #define CONFIG_SPL_SERIAL_SUPPORT
33 #define CONFIG_SPL_FLUSH_IMAGE
34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35 #define CONFIG_SPL_LIBGENERIC_SUPPORT
36 #define CONFIG_SPL_LIBCOMMON_SUPPORT
37 #define CONFIG_SPL_I2C_SUPPORT
38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
39 #define CONFIG_FSL_LAW /* Use common FSL init code */
40 #define CONFIG_SYS_TEXT_BASE 0x00201000
41 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
42 #define CONFIG_SPL_PAD_TO 0x40000
43 #define CONFIG_SPL_MAX_SIZE 0x28000
44 #define RESET_VECTOR_OFFSET 0x27FFC
45 #define BOOT_PAGE_OFFSET 0x27000
48 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
49 #define CONFIG_SPL_MMC_SUPPORT
50 #define CONFIG_SPL_MMC_MINIMAL
51 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
52 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
53 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
54 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
55 #ifndef CONFIG_SPL_BUILD
56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
59 #define CONFIG_SPL_MMC_BOOT
62 #ifdef CONFIG_SPL_BUILD
63 #define CONFIG_SPL_SKIP_RELOCATE
64 #define CONFIG_SPL_COMMON_INIT_DDR
65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
66 #define CONFIG_SYS_NO_FLASH
70 #endif /* CONFIG_RAMBOOT_PBL */
72 #define CONFIG_DDR_ECC
74 #define CONFIG_CMD_REGINFO
76 /* High Level Configuration Options */
78 #define CONFIG_E500 /* BOOKE e500 family */
79 #define CONFIG_E500MC /* BOOKE e500mc family */
80 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
81 #define CONFIG_MP /* support multiple processors */
83 #ifndef CONFIG_SYS_TEXT_BASE
84 #define CONFIG_SYS_TEXT_BASE 0xeff40000
87 #ifndef CONFIG_RESET_VECTOR_ADDRESS
88 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
91 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
92 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
93 #define CONFIG_FSL_IFC /* Enable IFC Support */
94 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
95 #define CONFIG_PCI /* Enable PCI/PCIE */
96 #define CONFIG_PCIE1 /* PCIE controler 1 */
97 #define CONFIG_PCIE2 /* PCIE controler 2 */
98 #define CONFIG_PCIE3 /* PCIE controler 3 */
99 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
100 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
102 #define CONFIG_FSL_LAW /* Use common FSL init code */
104 #define CONFIG_ENV_OVERWRITE
107 * These can be toggled for performance analysis, otherwise use default.
109 #define CONFIG_SYS_CACHE_STASHING
110 #define CONFIG_BTB /* toggle branch predition */
111 #ifdef CONFIG_DDR_ECC
112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
116 #define CONFIG_ENABLE_36BIT_PHYS
118 #define CONFIG_ADDR_MAP
119 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
121 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
122 #define CONFIG_SYS_MEMTEST_END 0x00400000
123 #define CONFIG_SYS_ALT_MEMTEST
124 #define CONFIG_PANIC_HANG /* do not reset board on panic */
127 * Config the L3 Cache as L3 SRAM
129 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
130 #define CONFIG_SYS_L3_SIZE (512 << 10)
131 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
132 #ifdef CONFIG_RAMBOOT_PBL
133 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
135 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
136 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
137 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
138 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
140 #define CONFIG_SYS_DCSRBAR 0xf0000000
141 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
146 #define CONFIG_VERY_BIG_RAM
147 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
150 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
151 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
152 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
153 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
155 #define CONFIG_DDR_SPD
156 #define CONFIG_SYS_FSL_DDR3
162 #define CONFIG_SYS_FLASH_BASE 0xe0000000
163 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
166 #ifdef CONFIG_SPL_BUILD
167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
172 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
173 #define CONFIG_MISC_INIT_R
175 #define CONFIG_HWCONFIG
177 /* define to use L1 as initial stack */
178 #define CONFIG_L1_INIT_RAM
179 #define CONFIG_SYS_INIT_RAM_LOCK
180 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
183 /* The assembler doesn't like typecast */
184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
185 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
186 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
187 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
190 GENERATED_GBL_DATA_SIZE)
191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
193 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
194 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
196 /* Serial Port - controlled on board with jumper J8
200 #define CONFIG_CONS_INDEX 1
201 #define CONFIG_SYS_NS16550
202 #define CONFIG_SYS_NS16550_SERIAL
203 #define CONFIG_SYS_NS16550_REG_SIZE 1
204 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
206 #define CONFIG_SYS_BAUDRATE_TABLE \
207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
210 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
211 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
212 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
214 /* Use the HUSH parser */
215 #define CONFIG_SYS_HUSH_PARSER
216 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
218 /* pass open firmware flat tree */
219 #define CONFIG_OF_LIBFDT
220 #define CONFIG_OF_BOARD_SETUP
221 #define CONFIG_OF_STDOUT_VIA_ALIAS
223 /* new uImage format support */
225 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
228 #define CONFIG_SYS_I2C
229 #define CONFIG_SYS_I2C_FSL
230 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
232 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
233 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
237 * Memory space is mapped 1-1, but I/O space must start from 0.
240 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
241 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
242 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
244 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
245 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
246 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
247 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
248 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
250 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
251 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
252 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
253 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
254 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
255 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
256 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
257 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
258 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
260 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
261 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
262 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
263 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
264 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
265 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
266 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
267 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
268 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
270 /* controller 4, Base address 203000 */
271 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
272 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
273 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
274 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
275 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
276 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
279 #define CONFIG_PCI_INDIRECT_BRIDGE
280 #define CONFIG_PCI_PNP /* do pci plug-and-play */
283 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
284 #define CONFIG_DOS_PARTITION
285 #endif /* CONFIG_PCI */
288 #ifdef CONFIG_FSL_SATA_V2
289 #define CONFIG_LIBATA
290 #define CONFIG_FSL_SATA
292 #define CONFIG_SYS_SATA_MAX_DEVICE 2
294 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
295 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
297 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
298 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
301 #define CONFIG_CMD_SATA
302 #define CONFIG_DOS_PARTITION
303 #define CONFIG_CMD_EXT2
306 #ifdef CONFIG_FMAN_ENET
307 #define CONFIG_MII /* MII PHY management */
308 #define CONFIG_ETHPRIME "FM1@DTSEC1"
309 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
315 #define CONFIG_LOADS_ECHO /* echo on for serial download */
316 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
319 * Command line configuration.
321 #define CONFIG_CMD_DHCP
322 #define CONFIG_CMD_ELF
323 #define CONFIG_CMD_ERRATA
324 #define CONFIG_CMD_GREPENV
325 #define CONFIG_CMD_IRQ
326 #define CONFIG_CMD_I2C
327 #define CONFIG_CMD_MII
328 #define CONFIG_CMD_PING
331 #define CONFIG_CMD_PCI
335 * Miscellaneous configurable options
337 #define CONFIG_SYS_LONGHELP /* undef to save memory */
338 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
339 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
340 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
341 #ifdef CONFIG_CMD_KGDB
342 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
344 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
346 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
347 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
348 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
351 * For booting Linux, the board info and command line data
352 * have to be in the first 64 MB of memory, since this is
353 * the maximum mapped by the Linux kernel during initialization.
355 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
356 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
358 #ifdef CONFIG_CMD_KGDB
359 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
363 * Environment Configuration
365 #define CONFIG_ROOTPATH "/opt/nfsroot"
366 #define CONFIG_BOOTFILE "uImage"
367 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
369 /* default location for tftp and bootm */
370 #define CONFIG_LOADADDR 1000000
373 #define CONFIG_BAUDRATE 115200
375 #define CONFIG_HVBOOT \
376 "setenv bootargs config-addr=0x60000000; " \
377 "bootm 0x01000000 - 0x00f00000"
379 #ifdef CONFIG_SYS_NO_FLASH
380 #ifndef CONFIG_RAMBOOT_PBL
381 #define CONFIG_ENV_IS_NOWHERE
384 #define CONFIG_FLASH_CFI_DRIVER
385 #define CONFIG_SYS_FLASH_CFI
386 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
389 #if defined(CONFIG_SPIFLASH)
390 #define CONFIG_SYS_EXTRA_ENV_RELOC
391 #define CONFIG_ENV_IS_IN_SPI_FLASH
392 #define CONFIG_ENV_SPI_BUS 0
393 #define CONFIG_ENV_SPI_CS 0
394 #define CONFIG_ENV_SPI_MAX_HZ 10000000
395 #define CONFIG_ENV_SPI_MODE 0
396 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
397 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
398 #define CONFIG_ENV_SECT_SIZE 0x10000
399 #elif defined(CONFIG_SDCARD)
400 #define CONFIG_SYS_EXTRA_ENV_RELOC
401 #define CONFIG_ENV_IS_IN_MMC
402 #define CONFIG_SYS_MMC_ENV_DEV 0
403 #define CONFIG_ENV_SIZE 0x2000
404 #define CONFIG_ENV_OFFSET (512 * 0x800)
405 #elif defined(CONFIG_NAND)
406 #define CONFIG_SYS_EXTRA_ENV_RELOC
407 #define CONFIG_ENV_IS_IN_NAND
408 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
409 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
410 #elif defined(CONFIG_ENV_IS_NOWHERE)
411 #define CONFIG_ENV_SIZE 0x2000
413 #define CONFIG_ENV_IS_IN_FLASH
414 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
415 #define CONFIG_ENV_SIZE 0x2000
416 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
419 #define CONFIG_SYS_CLK_FREQ 66666666
420 #define CONFIG_DDR_CLK_FREQ 133333333
423 unsigned long get_board_sys_clk(void);
424 unsigned long get_board_ddr_clk(void);
430 #define CONFIG_SYS_SPD_BUS_NUM 0
431 #define SPD_EEPROM_ADDRESS1 0x52
432 #define SPD_EEPROM_ADDRESS2 0x54
433 #define SPD_EEPROM_ADDRESS3 0x56
434 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
435 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
440 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
441 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
443 CSPR_PORT_SIZE_16 | \
446 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
447 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
448 CSPR_PORT_SIZE_16 | \
451 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
452 /* NOR Flash Timing Params */
453 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
455 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
456 FTIM0_NOR_TEADC(0x5) | \
457 FTIM0_NOR_TEAHC(0x5))
458 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
459 FTIM1_NOR_TRAD_NOR(0x1A) |\
460 FTIM1_NOR_TSEQRAD_NOR(0x13))
461 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
462 FTIM2_NOR_TCH(0x4) | \
463 FTIM2_NOR_TWPH(0x0E) | \
465 #define CONFIG_SYS_NOR_FTIM3 0x0
467 #define CONFIG_SYS_FLASH_QUIET_TEST
468 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
470 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
471 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
472 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
473 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
475 #define CONFIG_SYS_FLASH_EMPTY_INFO
476 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
477 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
479 /* NAND Flash on IFC */
480 #define CONFIG_NAND_FSL_IFC
481 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
482 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
483 #define CONFIG_SYS_NAND_BASE 0xff800000
484 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
486 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
487 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
488 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
489 | CSPR_MSEL_NAND /* MSEL = NAND */ \
491 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
493 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
494 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
495 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
496 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
497 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
498 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
499 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
501 #define CONFIG_SYS_NAND_ONFI_DETECTION
503 /* ONFI NAND Flash mode0 Timing Params */
504 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
505 FTIM0_NAND_TWP(0x18) | \
506 FTIM0_NAND_TWCHT(0x07) | \
507 FTIM0_NAND_TWH(0x0a))
508 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
509 FTIM1_NAND_TWBE(0x39) | \
510 FTIM1_NAND_TRR(0x0e) | \
511 FTIM1_NAND_TRP(0x18))
512 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
513 FTIM2_NAND_TREH(0x0a) | \
514 FTIM2_NAND_TWHRE(0x1e))
515 #define CONFIG_SYS_NAND_FTIM3 0x0
517 #define CONFIG_SYS_NAND_DDR_LAW 11
518 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
519 #define CONFIG_SYS_MAX_NAND_DEVICE 1
520 #define CONFIG_CMD_NAND
522 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
524 #if defined(CONFIG_NAND)
525 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
526 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
527 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
528 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
529 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
530 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
531 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
532 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
533 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
534 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
535 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
536 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
537 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
538 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
539 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
540 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
542 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
543 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
544 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
545 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
546 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
547 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
548 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
549 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
550 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
551 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
552 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
553 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
554 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
555 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
556 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
557 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
559 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
560 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
561 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
562 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
563 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
564 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
565 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
566 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
569 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
570 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
571 #define CONFIG_SYS_CSPR3_EXT (0xf)
572 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
577 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
578 #define CONFIG_SYS_CSOR3 0x0
580 /* CPLD Timing parameters for IFC CS3 */
581 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
582 FTIM0_GPCM_TEADC(0x0e) | \
583 FTIM0_GPCM_TEAHC(0x0e))
584 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
585 FTIM1_GPCM_TRAD(0x1f))
586 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
587 FTIM2_GPCM_TCH(0x8) | \
588 FTIM2_GPCM_TWP(0x1f))
589 #define CONFIG_SYS_CS3_FTIM3 0x0
591 #if defined(CONFIG_RAMBOOT_PBL)
592 #define CONFIG_SYS_RAMBOOT
597 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
598 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
599 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
600 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
602 #define I2C_MUX_CH_DEFAULT 0x8
603 #define I2C_MUX_CH_VOL_MONITOR 0xa
604 #define I2C_MUX_CH_VSC3316_FS 0xc
605 #define I2C_MUX_CH_VSC3316_BS 0xd
607 /* Voltage monitor on channel 2*/
608 #define I2C_VOL_MONITOR_ADDR 0x40
609 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
610 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
611 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
614 * eSPI - Enhanced SPI
616 #define CONFIG_FSL_ESPI
617 #define CONFIG_SPI_FLASH_SST
618 #define CONFIG_CMD_SF
619 #define CONFIG_SF_DEFAULT_SPEED 10000000
620 #define CONFIG_SF_DEFAULT_MODE 0
624 #ifndef CONFIG_NOBQFMAN
625 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
626 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
627 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
628 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
629 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
630 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
631 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
632 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
633 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
634 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
635 CONFIG_SYS_BMAN_CENA_SIZE)
636 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
637 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
638 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
639 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
640 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
641 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
642 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
643 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
644 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
645 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
646 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
647 CONFIG_SYS_QMAN_CENA_SIZE)
648 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
649 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
651 #define CONFIG_SYS_DPAA_FMAN
652 #define CONFIG_SYS_DPAA_PME
653 #define CONFIG_SYS_PMAN
654 #define CONFIG_SYS_DPAA_DCE
655 #define CONFIG_SYS_DPAA_RMAN
656 #define CONFIG_SYS_INTERLAKEN
658 /* Default address of microcode for the Linux Fman driver */
659 #if defined(CONFIG_SPIFLASH)
661 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
662 * env, so we got 0x110000.
664 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
665 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
666 #elif defined(CONFIG_SDCARD)
668 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
669 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
670 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
672 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
673 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
674 #elif defined(CONFIG_NAND)
675 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
676 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
678 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
679 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
681 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
682 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
683 #endif /* CONFIG_NOBQFMAN */
685 #ifdef CONFIG_SYS_DPAA_FMAN
686 #define CONFIG_FMAN_ENET
687 #define CONFIG_PHYLIB_10G
688 #define CONFIG_PHY_VITESSE
689 #define CONFIG_PHY_CORTINA
690 #define CONFIG_SYS_CORTINA_FW_IN_NOR
691 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
692 #define CONFIG_CORTINA_FW_LENGTH 0x40000
693 #define CONFIG_PHY_TERANETICS
694 #define SGMII_PHY_ADDR1 0x0
695 #define SGMII_PHY_ADDR2 0x1
696 #define SGMII_PHY_ADDR3 0x2
697 #define SGMII_PHY_ADDR4 0x3
698 #define SGMII_PHY_ADDR5 0x4
699 #define SGMII_PHY_ADDR6 0x5
700 #define SGMII_PHY_ADDR7 0x6
701 #define SGMII_PHY_ADDR8 0x7
702 #define FM1_10GEC1_PHY_ADDR 0x10
703 #define FM1_10GEC2_PHY_ADDR 0x11
704 #define FM2_10GEC1_PHY_ADDR 0x12
705 #define FM2_10GEC2_PHY_ADDR 0x13
706 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
707 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
708 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
709 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
714 #ifdef CONFIG_FSL_SATA_V2
715 #define CONFIG_LIBATA
716 #define CONFIG_FSL_SATA
718 #define CONFIG_SYS_SATA_MAX_DEVICE 2
720 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
721 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
723 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
724 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
727 #define CONFIG_CMD_SATA
728 #define CONFIG_DOS_PARTITION
729 #define CONFIG_CMD_EXT2
732 #ifdef CONFIG_FMAN_ENET
733 #define CONFIG_MII /* MII PHY management */
734 #define CONFIG_ETHPRIME "FM1@DTSEC1"
735 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
741 #define CONFIG_CMD_USB
742 #define CONFIG_USB_STORAGE
743 #define CONFIG_USB_EHCI
744 #define CONFIG_USB_EHCI_FSL
745 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
746 #define CONFIG_CMD_EXT2
747 #define CONFIG_HAS_FSL_DR_USB
752 #define CONFIG_FSL_ESDHC
753 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
754 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
755 #define CONFIG_CMD_MMC
756 #define CONFIG_GENERIC_MMC
757 #define CONFIG_CMD_EXT2
758 #define CONFIG_CMD_FAT
759 #define CONFIG_DOS_PARTITION
760 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
763 /* Hash command with SHA acceleration supported in hardware */
764 #ifdef CONFIG_FSL_CAAM
765 #define CONFIG_CMD_HASH
766 #define CONFIG_SHA_HW_ACCEL
769 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
771 #define __USB_PHY_TYPE utmi
774 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
775 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
776 * interleaving. It can be cacheline, page, bank, superbank.
777 * See doc/README.fsl-ddr for details.
779 #ifdef CONFIG_PPC_T4240
780 #define CTRL_INTLV_PREFERED 3way_4KB
782 #define CTRL_INTLV_PREFERED cacheline
785 #define CONFIG_EXTRA_ENV_SETTINGS \
786 "hwconfig=fsl_ddr:" \
787 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
789 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
791 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
792 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
793 "tftpflash=tftpboot $loadaddr $uboot && " \
794 "protect off $ubootaddr +$filesize && " \
795 "erase $ubootaddr +$filesize && " \
796 "cp.b $loadaddr $ubootaddr $filesize && " \
797 "protect on $ubootaddr +$filesize && " \
798 "cmp.b $loadaddr $ubootaddr $filesize\0" \
799 "consoledev=ttyS0\0" \
800 "ramdiskaddr=2000000\0" \
801 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
803 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
806 #define CONFIG_HVBOOT \
807 "setenv bootargs config-addr=0x60000000; " \
808 "bootm 0x01000000 - 0x00f00000"
810 #define CONFIG_LINUX \
811 "setenv bootargs root=/dev/ram rw " \
812 "console=$consoledev,$baudrate $othbootargs;" \
813 "setenv ramdiskaddr 0x02000000;" \
814 "setenv fdtaddr 0x00c00000;" \
815 "setenv loadaddr 0x1000000;" \
816 "bootm $loadaddr $ramdiskaddr $fdtaddr"
818 #define CONFIG_HDBOOT \
819 "setenv bootargs root=/dev/$bdev rw " \
820 "console=$consoledev,$baudrate $othbootargs;" \
821 "tftp $loadaddr $bootfile;" \
822 "tftp $fdtaddr $fdtfile;" \
823 "bootm $loadaddr - $fdtaddr"
825 #define CONFIG_NFSBOOTCOMMAND \
826 "setenv bootargs root=/dev/nfs rw " \
827 "nfsroot=$serverip:$rootpath " \
828 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
829 "console=$consoledev,$baudrate $othbootargs;" \
830 "tftp $loadaddr $bootfile;" \
831 "tftp $fdtaddr $fdtfile;" \
832 "bootm $loadaddr - $fdtaddr"
834 #define CONFIG_RAMBOOTCOMMAND \
835 "setenv bootargs root=/dev/ram rw " \
836 "console=$consoledev,$baudrate $othbootargs;" \
837 "tftp $ramdiskaddr $ramdiskfile;" \
838 "tftp $loadaddr $bootfile;" \
839 "tftp $fdtaddr $fdtfile;" \
840 "bootm $loadaddr $ramdiskaddr $fdtaddr"
842 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
844 #include <asm/fsl_secure_boot.h>
846 #ifdef CONFIG_SECURE_BOOT
847 /* Secure Boot target was not getting build for T4240 because of
848 * increased binary size. So the size is being reduced by removing USB
849 * which is anyways not used in Secure Environment.
851 #undef CONFIG_CMD_USB
852 #define CONFIG_CMD_BLOB
855 #endif /* __CONFIG_H */