2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 RDB board configuration file
13 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26 #define CONFIG_SYS_TEXT_BASE 0x00201000
27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28 #define CONFIG_SPL_PAD_TO 0x40000
29 #define CONFIG_SPL_MAX_SIZE 0x28000
30 #define RESET_VECTOR_OFFSET 0x27FFC
31 #define BOOT_PAGE_OFFSET 0x27000
34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
35 #define CONFIG_SPL_MMC_MINIMAL
36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
40 #ifndef CONFIG_SPL_BUILD
41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
45 #define CONFIG_SPL_MMC_BOOT
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_SKIP_RELOCATE
50 #define CONFIG_SPL_COMMON_INIT_DDR
51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
52 #define CONFIG_SYS_NO_FLASH
56 #endif /* CONFIG_RAMBOOT_PBL */
58 #define CONFIG_DDR_ECC
60 #define CONFIG_CMD_REGINFO
62 /* High Level Configuration Options */
63 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
64 #define CONFIG_MP /* support multiple processors */
66 #ifndef CONFIG_SYS_TEXT_BASE
67 #define CONFIG_SYS_TEXT_BASE 0xeff40000
70 #ifndef CONFIG_RESET_VECTOR_ADDRESS
71 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
74 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
75 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
76 #define CONFIG_FSL_IFC /* Enable IFC Support */
77 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
78 #define CONFIG_PCIE1 /* PCIE controller 1 */
79 #define CONFIG_PCIE2 /* PCIE controller 2 */
80 #define CONFIG_PCIE3 /* PCIE controller 3 */
81 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
82 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
84 #define CONFIG_ENV_OVERWRITE
87 * These can be toggled for performance analysis, otherwise use default.
89 #define CONFIG_SYS_CACHE_STASHING
90 #define CONFIG_BTB /* toggle branch predition */
92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
93 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
96 #define CONFIG_ENABLE_36BIT_PHYS
98 #define CONFIG_ADDR_MAP
99 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
101 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
102 #define CONFIG_SYS_MEMTEST_END 0x00400000
103 #define CONFIG_SYS_ALT_MEMTEST
104 #define CONFIG_PANIC_HANG /* do not reset board on panic */
107 * Config the L3 Cache as L3 SRAM
109 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
110 #define CONFIG_SYS_L3_SIZE (512 << 10)
111 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
112 #ifdef CONFIG_RAMBOOT_PBL
113 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
115 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
116 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
117 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
118 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
120 #define CONFIG_SYS_DCSRBAR 0xf0000000
121 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
126 #define CONFIG_VERY_BIG_RAM
127 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
128 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
130 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
131 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
132 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
133 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
135 #define CONFIG_DDR_SPD
140 #define CONFIG_SYS_FLASH_BASE 0xe0000000
141 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
143 #ifdef CONFIG_SPL_BUILD
144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
149 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
150 #define CONFIG_MISC_INIT_R
152 #define CONFIG_HWCONFIG
154 /* define to use L1 as initial stack */
155 #define CONFIG_L1_INIT_RAM
156 #define CONFIG_SYS_INIT_RAM_LOCK
157 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
160 /* The assembler doesn't like typecast */
161 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
162 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
163 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
164 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
166 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
167 GENERATED_GBL_DATA_SIZE)
168 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
170 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
171 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
173 /* Serial Port - controlled on board with jumper J8
177 #define CONFIG_CONS_INDEX 1
178 #define CONFIG_SYS_NS16550_SERIAL
179 #define CONFIG_SYS_NS16550_REG_SIZE 1
180 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
182 #define CONFIG_SYS_BAUDRATE_TABLE \
183 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
185 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
186 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
187 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
188 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
191 #define CONFIG_SYS_I2C
192 #define CONFIG_SYS_I2C_FSL
193 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
194 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
195 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
196 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
200 * Memory space is mapped 1-1, but I/O space must start from 0.
203 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
204 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
205 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
206 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
207 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
208 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
209 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
210 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
211 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
213 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
214 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
215 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
216 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
217 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
218 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
219 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
220 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
221 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
223 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
224 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
225 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
226 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
227 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
228 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
229 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
230 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
231 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
233 /* controller 4, Base address 203000 */
234 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
235 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
236 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
237 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
238 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
239 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
242 #define CONFIG_PCI_INDIRECT_BRIDGE
244 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
245 #define CONFIG_DOS_PARTITION
246 #endif /* CONFIG_PCI */
249 #ifdef CONFIG_FSL_SATA_V2
250 #define CONFIG_LIBATA
251 #define CONFIG_FSL_SATA
253 #define CONFIG_SYS_SATA_MAX_DEVICE 2
255 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
256 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
258 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
259 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
262 #define CONFIG_CMD_SATA
263 #define CONFIG_DOS_PARTITION
266 #ifdef CONFIG_FMAN_ENET
267 #define CONFIG_MII /* MII PHY management */
268 #define CONFIG_ETHPRIME "FM1@DTSEC1"
269 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
275 #define CONFIG_LOADS_ECHO /* echo on for serial download */
276 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
279 * Command line configuration.
281 #define CONFIG_CMD_ERRATA
282 #define CONFIG_CMD_IRQ
285 #define CONFIG_CMD_PCI
289 * Miscellaneous configurable options
291 #define CONFIG_SYS_LONGHELP /* undef to save memory */
292 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
293 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
294 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
295 #ifdef CONFIG_CMD_KGDB
296 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
298 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
300 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
301 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
302 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
305 * For booting Linux, the board info and command line data
306 * have to be in the first 64 MB of memory, since this is
307 * the maximum mapped by the Linux kernel during initialization.
309 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
310 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
312 #ifdef CONFIG_CMD_KGDB
313 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
317 * Environment Configuration
319 #define CONFIG_ROOTPATH "/opt/nfsroot"
320 #define CONFIG_BOOTFILE "uImage"
321 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
323 /* default location for tftp and bootm */
324 #define CONFIG_LOADADDR 1000000
326 #define CONFIG_BAUDRATE 115200
328 #define CONFIG_HVBOOT \
329 "setenv bootargs config-addr=0x60000000; " \
330 "bootm 0x01000000 - 0x00f00000"
332 #ifdef CONFIG_SYS_NO_FLASH
333 #ifndef CONFIG_RAMBOOT_PBL
334 #define CONFIG_ENV_IS_NOWHERE
337 #define CONFIG_FLASH_CFI_DRIVER
338 #define CONFIG_SYS_FLASH_CFI
339 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
342 #if defined(CONFIG_SPIFLASH)
343 #define CONFIG_SYS_EXTRA_ENV_RELOC
344 #define CONFIG_ENV_IS_IN_SPI_FLASH
345 #define CONFIG_ENV_SPI_BUS 0
346 #define CONFIG_ENV_SPI_CS 0
347 #define CONFIG_ENV_SPI_MAX_HZ 10000000
348 #define CONFIG_ENV_SPI_MODE 0
349 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
350 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
351 #define CONFIG_ENV_SECT_SIZE 0x10000
352 #elif defined(CONFIG_SDCARD)
353 #define CONFIG_SYS_EXTRA_ENV_RELOC
354 #define CONFIG_ENV_IS_IN_MMC
355 #define CONFIG_SYS_MMC_ENV_DEV 0
356 #define CONFIG_ENV_SIZE 0x2000
357 #define CONFIG_ENV_OFFSET (512 * 0x800)
358 #elif defined(CONFIG_NAND)
359 #define CONFIG_SYS_EXTRA_ENV_RELOC
360 #define CONFIG_ENV_IS_IN_NAND
361 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
362 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
363 #elif defined(CONFIG_ENV_IS_NOWHERE)
364 #define CONFIG_ENV_SIZE 0x2000
366 #define CONFIG_ENV_IS_IN_FLASH
367 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
368 #define CONFIG_ENV_SIZE 0x2000
369 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
372 #define CONFIG_SYS_CLK_FREQ 66666666
373 #define CONFIG_DDR_CLK_FREQ 133333333
376 unsigned long get_board_sys_clk(void);
377 unsigned long get_board_ddr_clk(void);
383 #define CONFIG_SYS_SPD_BUS_NUM 0
384 #define SPD_EEPROM_ADDRESS1 0x52
385 #define SPD_EEPROM_ADDRESS2 0x54
386 #define SPD_EEPROM_ADDRESS3 0x56
387 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
388 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
393 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
394 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
396 CSPR_PORT_SIZE_16 | \
399 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
400 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
401 CSPR_PORT_SIZE_16 | \
404 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
405 /* NOR Flash Timing Params */
406 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
408 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
409 FTIM0_NOR_TEADC(0x5) | \
410 FTIM0_NOR_TEAHC(0x5))
411 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
412 FTIM1_NOR_TRAD_NOR(0x1A) |\
413 FTIM1_NOR_TSEQRAD_NOR(0x13))
414 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
415 FTIM2_NOR_TCH(0x4) | \
416 FTIM2_NOR_TWPH(0x0E) | \
418 #define CONFIG_SYS_NOR_FTIM3 0x0
420 #define CONFIG_SYS_FLASH_QUIET_TEST
421 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
423 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
424 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
425 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
426 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
428 #define CONFIG_SYS_FLASH_EMPTY_INFO
429 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
430 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
432 /* NAND Flash on IFC */
433 #define CONFIG_NAND_FSL_IFC
434 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
435 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
436 #define CONFIG_SYS_NAND_BASE 0xff800000
437 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
439 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
440 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
441 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
442 | CSPR_MSEL_NAND /* MSEL = NAND */ \
444 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
446 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
447 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
448 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
449 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
450 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
451 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
452 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
454 #define CONFIG_SYS_NAND_ONFI_DETECTION
456 /* ONFI NAND Flash mode0 Timing Params */
457 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
458 FTIM0_NAND_TWP(0x18) | \
459 FTIM0_NAND_TWCHT(0x07) | \
460 FTIM0_NAND_TWH(0x0a))
461 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
462 FTIM1_NAND_TWBE(0x39) | \
463 FTIM1_NAND_TRR(0x0e) | \
464 FTIM1_NAND_TRP(0x18))
465 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
466 FTIM2_NAND_TREH(0x0a) | \
467 FTIM2_NAND_TWHRE(0x1e))
468 #define CONFIG_SYS_NAND_FTIM3 0x0
470 #define CONFIG_SYS_NAND_DDR_LAW 11
471 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
472 #define CONFIG_SYS_MAX_NAND_DEVICE 1
473 #define CONFIG_CMD_NAND
475 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
477 #if defined(CONFIG_NAND)
478 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
479 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
480 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
481 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
482 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
483 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
484 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
485 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
486 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
487 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
488 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
489 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
490 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
491 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
492 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
493 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
495 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
496 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
497 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
498 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
499 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
500 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
501 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
502 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
503 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
504 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
505 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
506 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
507 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
508 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
509 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
510 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
512 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
513 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
514 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
515 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
516 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
517 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
518 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
519 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
522 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
523 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
524 #define CONFIG_SYS_CSPR3_EXT (0xf)
525 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
530 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
531 #define CONFIG_SYS_CSOR3 0x0
533 /* CPLD Timing parameters for IFC CS3 */
534 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
535 FTIM0_GPCM_TEADC(0x0e) | \
536 FTIM0_GPCM_TEAHC(0x0e))
537 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
538 FTIM1_GPCM_TRAD(0x1f))
539 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
540 FTIM2_GPCM_TCH(0x8) | \
541 FTIM2_GPCM_TWP(0x1f))
542 #define CONFIG_SYS_CS3_FTIM3 0x0
544 #if defined(CONFIG_RAMBOOT_PBL)
545 #define CONFIG_SYS_RAMBOOT
549 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
550 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
551 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
552 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
554 #define I2C_MUX_CH_DEFAULT 0x8
555 #define I2C_MUX_CH_VOL_MONITOR 0xa
556 #define I2C_MUX_CH_VSC3316_FS 0xc
557 #define I2C_MUX_CH_VSC3316_BS 0xd
559 /* Voltage monitor on channel 2*/
560 #define I2C_VOL_MONITOR_ADDR 0x40
561 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
562 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
563 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
565 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
566 #ifndef CONFIG_SPL_BUILD
569 #define CONFIG_VOL_MONITOR_IR36021_SET
570 #define CONFIG_VOL_MONITOR_IR36021_READ
571 /* The lowest and highest voltage allowed for T4240RDB */
572 #define VDD_MV_MIN 819
573 #define VDD_MV_MAX 1212
576 * eSPI - Enhanced SPI
578 #define CONFIG_SF_DEFAULT_SPEED 10000000
579 #define CONFIG_SF_DEFAULT_MODE 0
582 #ifndef CONFIG_NOBQFMAN
583 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
584 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
585 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
586 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
587 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
588 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
589 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
590 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
591 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
592 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
593 CONFIG_SYS_BMAN_CENA_SIZE)
594 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
595 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
596 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
597 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
598 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
599 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
600 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
601 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
602 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
603 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
604 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
605 CONFIG_SYS_QMAN_CENA_SIZE)
606 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
607 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
609 #define CONFIG_SYS_DPAA_FMAN
610 #define CONFIG_SYS_DPAA_PME
611 #define CONFIG_SYS_PMAN
612 #define CONFIG_SYS_DPAA_DCE
613 #define CONFIG_SYS_DPAA_RMAN
614 #define CONFIG_SYS_INTERLAKEN
616 /* Default address of microcode for the Linux Fman driver */
617 #if defined(CONFIG_SPIFLASH)
619 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
620 * env, so we got 0x110000.
622 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
623 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
624 #elif defined(CONFIG_SDCARD)
626 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
627 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
628 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
630 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
631 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
632 #elif defined(CONFIG_NAND)
633 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
634 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
636 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
637 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
639 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
640 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
641 #endif /* CONFIG_NOBQFMAN */
643 #ifdef CONFIG_SYS_DPAA_FMAN
644 #define CONFIG_FMAN_ENET
645 #define CONFIG_PHYLIB_10G
646 #define CONFIG_PHY_VITESSE
647 #define CONFIG_PHY_CORTINA
648 #define CONFIG_SYS_CORTINA_FW_IN_NOR
649 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
650 #define CONFIG_CORTINA_FW_LENGTH 0x40000
651 #define CONFIG_PHY_TERANETICS
652 #define SGMII_PHY_ADDR1 0x0
653 #define SGMII_PHY_ADDR2 0x1
654 #define SGMII_PHY_ADDR3 0x2
655 #define SGMII_PHY_ADDR4 0x3
656 #define SGMII_PHY_ADDR5 0x4
657 #define SGMII_PHY_ADDR6 0x5
658 #define SGMII_PHY_ADDR7 0x6
659 #define SGMII_PHY_ADDR8 0x7
660 #define FM1_10GEC1_PHY_ADDR 0x10
661 #define FM1_10GEC2_PHY_ADDR 0x11
662 #define FM2_10GEC1_PHY_ADDR 0x12
663 #define FM2_10GEC2_PHY_ADDR 0x13
664 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
665 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
666 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
667 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
671 #ifdef CONFIG_FSL_SATA_V2
672 #define CONFIG_LIBATA
673 #define CONFIG_FSL_SATA
675 #define CONFIG_SYS_SATA_MAX_DEVICE 2
677 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
678 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
680 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
681 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
684 #define CONFIG_CMD_SATA
685 #define CONFIG_DOS_PARTITION
688 #ifdef CONFIG_FMAN_ENET
689 #define CONFIG_MII /* MII PHY management */
690 #define CONFIG_ETHPRIME "FM1@DTSEC1"
691 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
697 #define CONFIG_USB_EHCI
698 #define CONFIG_USB_EHCI_FSL
699 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
700 #define CONFIG_HAS_FSL_DR_USB
703 #define CONFIG_FSL_ESDHC
704 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
705 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
706 #define CONFIG_GENERIC_MMC
707 #define CONFIG_DOS_PARTITION
708 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
711 /* Hash command with SHA acceleration supported in hardware */
712 #ifdef CONFIG_FSL_CAAM
713 #define CONFIG_CMD_HASH
714 #define CONFIG_SHA_HW_ACCEL
718 #define __USB_PHY_TYPE utmi
721 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
722 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
723 * interleaving. It can be cacheline, page, bank, superbank.
724 * See doc/README.fsl-ddr for details.
726 #ifdef CONFIG_ARCH_T4240
727 #define CTRL_INTLV_PREFERED 3way_4KB
729 #define CTRL_INTLV_PREFERED cacheline
732 #define CONFIG_EXTRA_ENV_SETTINGS \
733 "hwconfig=fsl_ddr:" \
734 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
736 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
738 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
739 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
740 "tftpflash=tftpboot $loadaddr $uboot && " \
741 "protect off $ubootaddr +$filesize && " \
742 "erase $ubootaddr +$filesize && " \
743 "cp.b $loadaddr $ubootaddr $filesize && " \
744 "protect on $ubootaddr +$filesize && " \
745 "cmp.b $loadaddr $ubootaddr $filesize\0" \
746 "consoledev=ttyS0\0" \
747 "ramdiskaddr=2000000\0" \
748 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
749 "fdtaddr=1e00000\0" \
750 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
753 #define CONFIG_HVBOOT \
754 "setenv bootargs config-addr=0x60000000; " \
755 "bootm 0x01000000 - 0x00f00000"
757 #define CONFIG_LINUX \
758 "setenv bootargs root=/dev/ram rw " \
759 "console=$consoledev,$baudrate $othbootargs;" \
760 "setenv ramdiskaddr 0x02000000;" \
761 "setenv fdtaddr 0x00c00000;" \
762 "setenv loadaddr 0x1000000;" \
763 "bootm $loadaddr $ramdiskaddr $fdtaddr"
765 #define CONFIG_HDBOOT \
766 "setenv bootargs root=/dev/$bdev rw " \
767 "console=$consoledev,$baudrate $othbootargs;" \
768 "tftp $loadaddr $bootfile;" \
769 "tftp $fdtaddr $fdtfile;" \
770 "bootm $loadaddr - $fdtaddr"
772 #define CONFIG_NFSBOOTCOMMAND \
773 "setenv bootargs root=/dev/nfs rw " \
774 "nfsroot=$serverip:$rootpath " \
775 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
776 "console=$consoledev,$baudrate $othbootargs;" \
777 "tftp $loadaddr $bootfile;" \
778 "tftp $fdtaddr $fdtfile;" \
779 "bootm $loadaddr - $fdtaddr"
781 #define CONFIG_RAMBOOTCOMMAND \
782 "setenv bootargs root=/dev/ram rw " \
783 "console=$consoledev,$baudrate $othbootargs;" \
784 "tftp $ramdiskaddr $ramdiskfile;" \
785 "tftp $loadaddr $bootfile;" \
786 "tftp $fdtaddr $fdtfile;" \
787 "bootm $loadaddr $ramdiskaddr $fdtaddr"
789 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
791 #include <asm/fsl_secure_boot.h>
793 #endif /* __CONFIG_H */