2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 RDB board configuration file
13 #define CONFIG_T4240RDB
14 #define CONFIG_PHYS_64BIT
15 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_FSL_SATA_V2
20 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
22 #ifdef CONFIG_RAMBOOT_PBL
23 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
30 #define CONFIG_SPL_ENV_SUPPORT
31 #define CONFIG_SPL_SERIAL_SUPPORT
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34 #define CONFIG_SPL_LIBGENERIC_SUPPORT
35 #define CONFIG_SPL_LIBCOMMON_SUPPORT
36 #define CONFIG_SPL_I2C_SUPPORT
37 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
38 #define CONFIG_FSL_LAW /* Use common FSL init code */
39 #define CONFIG_SYS_TEXT_BASE 0x00201000
40 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
41 #define CONFIG_SPL_PAD_TO 0x40000
42 #define CONFIG_SPL_MAX_SIZE 0x28000
43 #define RESET_VECTOR_OFFSET 0x27FFC
44 #define BOOT_PAGE_OFFSET 0x27000
47 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
48 #define CONFIG_SPL_MMC_SUPPORT
49 #define CONFIG_SPL_MMC_MINIMAL
50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
51 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
52 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
54 #ifndef CONFIG_SPL_BUILD
55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
58 #define CONFIG_SPL_MMC_BOOT
61 #ifdef CONFIG_SPL_BUILD
62 #define CONFIG_SPL_SKIP_RELOCATE
63 #define CONFIG_SPL_COMMON_INIT_DDR
64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
65 #define CONFIG_SYS_NO_FLASH
69 #endif /* CONFIG_RAMBOOT_PBL */
71 #define CONFIG_DDR_ECC
73 #define CONFIG_CMD_REGINFO
75 /* High Level Configuration Options */
77 #define CONFIG_E500 /* BOOKE e500 family */
78 #define CONFIG_E500MC /* BOOKE e500mc family */
79 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
80 #define CONFIG_MP /* support multiple processors */
82 #ifndef CONFIG_SYS_TEXT_BASE
83 #define CONFIG_SYS_TEXT_BASE 0xeff40000
86 #ifndef CONFIG_RESET_VECTOR_ADDRESS
87 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
90 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
91 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
92 #define CONFIG_FSL_IFC /* Enable IFC Support */
93 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
94 #define CONFIG_PCI /* Enable PCI/PCIE */
95 #define CONFIG_PCIE1 /* PCIE controler 1 */
96 #define CONFIG_PCIE2 /* PCIE controler 2 */
97 #define CONFIG_PCIE3 /* PCIE controler 3 */
98 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
99 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
101 #define CONFIG_FSL_LAW /* Use common FSL init code */
103 #define CONFIG_ENV_OVERWRITE
106 * These can be toggled for performance analysis, otherwise use default.
108 #define CONFIG_SYS_CACHE_STASHING
109 #define CONFIG_BTB /* toggle branch predition */
110 #ifdef CONFIG_DDR_ECC
111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
112 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
115 #define CONFIG_ENABLE_36BIT_PHYS
117 #define CONFIG_ADDR_MAP
118 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
120 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
121 #define CONFIG_SYS_MEMTEST_END 0x00400000
122 #define CONFIG_SYS_ALT_MEMTEST
123 #define CONFIG_PANIC_HANG /* do not reset board on panic */
126 * Config the L3 Cache as L3 SRAM
128 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
129 #define CONFIG_SYS_L3_SIZE (512 << 10)
130 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
131 #ifdef CONFIG_RAMBOOT_PBL
132 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
134 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
135 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
136 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
137 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
139 #define CONFIG_SYS_DCSRBAR 0xf0000000
140 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
145 #define CONFIG_VERY_BIG_RAM
146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
149 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
151 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
152 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
154 #define CONFIG_DDR_SPD
155 #define CONFIG_SYS_FSL_DDR3
161 #define CONFIG_SYS_FLASH_BASE 0xe0000000
162 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
165 #ifdef CONFIG_SPL_BUILD
166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
171 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
172 #define CONFIG_MISC_INIT_R
174 #define CONFIG_HWCONFIG
176 /* define to use L1 as initial stack */
177 #define CONFIG_L1_INIT_RAM
178 #define CONFIG_SYS_INIT_RAM_LOCK
179 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
182 /* The assembler doesn't like typecast */
183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
184 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
185 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
186 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
188 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
189 GENERATED_GBL_DATA_SIZE)
190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
192 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
193 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
195 /* Serial Port - controlled on board with jumper J8
199 #define CONFIG_CONS_INDEX 1
200 #define CONFIG_SYS_NS16550
201 #define CONFIG_SYS_NS16550_SERIAL
202 #define CONFIG_SYS_NS16550_REG_SIZE 1
203 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
205 #define CONFIG_SYS_BAUDRATE_TABLE \
206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
208 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
209 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
210 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
211 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
213 /* Use the HUSH parser */
214 #define CONFIG_SYS_HUSH_PARSER
215 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
217 /* pass open firmware flat tree */
218 #define CONFIG_OF_LIBFDT
219 #define CONFIG_OF_BOARD_SETUP
220 #define CONFIG_OF_STDOUT_VIA_ALIAS
222 /* new uImage format support */
224 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
227 #define CONFIG_SYS_I2C
228 #define CONFIG_SYS_I2C_FSL
229 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
230 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
231 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
232 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
236 * Memory space is mapped 1-1, but I/O space must start from 0.
239 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
240 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
241 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
242 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
243 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
244 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
245 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
246 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
247 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
249 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
250 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
251 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
252 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
253 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
254 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
255 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
256 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
257 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
259 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
260 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
261 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
262 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
263 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
264 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
265 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
266 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
267 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
269 /* controller 4, Base address 203000 */
270 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
271 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
272 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
273 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
274 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
275 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
278 #define CONFIG_PCI_INDIRECT_BRIDGE
279 #define CONFIG_PCI_PNP /* do pci plug-and-play */
281 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
282 #define CONFIG_DOS_PARTITION
283 #endif /* CONFIG_PCI */
286 #ifdef CONFIG_FSL_SATA_V2
287 #define CONFIG_LIBATA
288 #define CONFIG_FSL_SATA
290 #define CONFIG_SYS_SATA_MAX_DEVICE 2
292 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
293 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
295 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
296 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
299 #define CONFIG_CMD_SATA
300 #define CONFIG_DOS_PARTITION
301 #define CONFIG_CMD_EXT2
304 #ifdef CONFIG_FMAN_ENET
305 #define CONFIG_MII /* MII PHY management */
306 #define CONFIG_ETHPRIME "FM1@DTSEC1"
307 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
313 #define CONFIG_LOADS_ECHO /* echo on for serial download */
314 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
317 * Command line configuration.
319 #define CONFIG_CMD_DHCP
320 #define CONFIG_CMD_ERRATA
321 #define CONFIG_CMD_GREPENV
322 #define CONFIG_CMD_IRQ
323 #define CONFIG_CMD_I2C
324 #define CONFIG_CMD_MII
325 #define CONFIG_CMD_PING
328 #define CONFIG_CMD_PCI
332 * Miscellaneous configurable options
334 #define CONFIG_SYS_LONGHELP /* undef to save memory */
335 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
336 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
337 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
338 #ifdef CONFIG_CMD_KGDB
339 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
341 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
343 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
344 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
345 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
348 * For booting Linux, the board info and command line data
349 * have to be in the first 64 MB of memory, since this is
350 * the maximum mapped by the Linux kernel during initialization.
352 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
353 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
355 #ifdef CONFIG_CMD_KGDB
356 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
360 * Environment Configuration
362 #define CONFIG_ROOTPATH "/opt/nfsroot"
363 #define CONFIG_BOOTFILE "uImage"
364 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
366 /* default location for tftp and bootm */
367 #define CONFIG_LOADADDR 1000000
370 #define CONFIG_BAUDRATE 115200
372 #define CONFIG_HVBOOT \
373 "setenv bootargs config-addr=0x60000000; " \
374 "bootm 0x01000000 - 0x00f00000"
376 #ifdef CONFIG_SYS_NO_FLASH
377 #ifndef CONFIG_RAMBOOT_PBL
378 #define CONFIG_ENV_IS_NOWHERE
381 #define CONFIG_FLASH_CFI_DRIVER
382 #define CONFIG_SYS_FLASH_CFI
383 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
386 #if defined(CONFIG_SPIFLASH)
387 #define CONFIG_SYS_EXTRA_ENV_RELOC
388 #define CONFIG_ENV_IS_IN_SPI_FLASH
389 #define CONFIG_ENV_SPI_BUS 0
390 #define CONFIG_ENV_SPI_CS 0
391 #define CONFIG_ENV_SPI_MAX_HZ 10000000
392 #define CONFIG_ENV_SPI_MODE 0
393 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
394 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
395 #define CONFIG_ENV_SECT_SIZE 0x10000
396 #elif defined(CONFIG_SDCARD)
397 #define CONFIG_SYS_EXTRA_ENV_RELOC
398 #define CONFIG_ENV_IS_IN_MMC
399 #define CONFIG_SYS_MMC_ENV_DEV 0
400 #define CONFIG_ENV_SIZE 0x2000
401 #define CONFIG_ENV_OFFSET (512 * 0x800)
402 #elif defined(CONFIG_NAND)
403 #define CONFIG_SYS_EXTRA_ENV_RELOC
404 #define CONFIG_ENV_IS_IN_NAND
405 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
406 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
407 #elif defined(CONFIG_ENV_IS_NOWHERE)
408 #define CONFIG_ENV_SIZE 0x2000
410 #define CONFIG_ENV_IS_IN_FLASH
411 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
412 #define CONFIG_ENV_SIZE 0x2000
413 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
416 #define CONFIG_SYS_CLK_FREQ 66666666
417 #define CONFIG_DDR_CLK_FREQ 133333333
420 unsigned long get_board_sys_clk(void);
421 unsigned long get_board_ddr_clk(void);
427 #define CONFIG_SYS_SPD_BUS_NUM 0
428 #define SPD_EEPROM_ADDRESS1 0x52
429 #define SPD_EEPROM_ADDRESS2 0x54
430 #define SPD_EEPROM_ADDRESS3 0x56
431 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
432 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
437 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
438 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
440 CSPR_PORT_SIZE_16 | \
443 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
444 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
445 CSPR_PORT_SIZE_16 | \
448 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
449 /* NOR Flash Timing Params */
450 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
452 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
453 FTIM0_NOR_TEADC(0x5) | \
454 FTIM0_NOR_TEAHC(0x5))
455 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
456 FTIM1_NOR_TRAD_NOR(0x1A) |\
457 FTIM1_NOR_TSEQRAD_NOR(0x13))
458 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
459 FTIM2_NOR_TCH(0x4) | \
460 FTIM2_NOR_TWPH(0x0E) | \
462 #define CONFIG_SYS_NOR_FTIM3 0x0
464 #define CONFIG_SYS_FLASH_QUIET_TEST
465 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
467 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
468 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
469 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
470 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
472 #define CONFIG_SYS_FLASH_EMPTY_INFO
473 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
474 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
476 /* NAND Flash on IFC */
477 #define CONFIG_NAND_FSL_IFC
478 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
479 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
480 #define CONFIG_SYS_NAND_BASE 0xff800000
481 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
483 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
484 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
485 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
486 | CSPR_MSEL_NAND /* MSEL = NAND */ \
488 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
490 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
491 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
492 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
493 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
494 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
495 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
496 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
498 #define CONFIG_SYS_NAND_ONFI_DETECTION
500 /* ONFI NAND Flash mode0 Timing Params */
501 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
502 FTIM0_NAND_TWP(0x18) | \
503 FTIM0_NAND_TWCHT(0x07) | \
504 FTIM0_NAND_TWH(0x0a))
505 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
506 FTIM1_NAND_TWBE(0x39) | \
507 FTIM1_NAND_TRR(0x0e) | \
508 FTIM1_NAND_TRP(0x18))
509 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
510 FTIM2_NAND_TREH(0x0a) | \
511 FTIM2_NAND_TWHRE(0x1e))
512 #define CONFIG_SYS_NAND_FTIM3 0x0
514 #define CONFIG_SYS_NAND_DDR_LAW 11
515 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
516 #define CONFIG_SYS_MAX_NAND_DEVICE 1
517 #define CONFIG_CMD_NAND
519 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
521 #if defined(CONFIG_NAND)
522 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
523 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
524 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
525 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
526 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
527 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
528 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
529 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
530 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
531 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
532 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
533 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
534 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
535 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
536 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
537 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
539 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
540 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
541 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
542 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
543 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
544 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
545 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
546 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
547 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
548 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
549 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
550 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
551 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
552 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
553 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
554 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
556 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
557 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
558 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
559 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
560 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
561 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
562 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
563 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
566 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
567 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
568 #define CONFIG_SYS_CSPR3_EXT (0xf)
569 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
574 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
575 #define CONFIG_SYS_CSOR3 0x0
577 /* CPLD Timing parameters for IFC CS3 */
578 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
579 FTIM0_GPCM_TEADC(0x0e) | \
580 FTIM0_GPCM_TEAHC(0x0e))
581 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
582 FTIM1_GPCM_TRAD(0x1f))
583 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
584 FTIM2_GPCM_TCH(0x8) | \
585 FTIM2_GPCM_TWP(0x1f))
586 #define CONFIG_SYS_CS3_FTIM3 0x0
588 #if defined(CONFIG_RAMBOOT_PBL)
589 #define CONFIG_SYS_RAMBOOT
594 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
595 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
596 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
597 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
599 #define I2C_MUX_CH_DEFAULT 0x8
600 #define I2C_MUX_CH_VOL_MONITOR 0xa
601 #define I2C_MUX_CH_VSC3316_FS 0xc
602 #define I2C_MUX_CH_VSC3316_BS 0xd
604 /* Voltage monitor on channel 2*/
605 #define I2C_VOL_MONITOR_ADDR 0x40
606 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
607 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
608 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
611 * eSPI - Enhanced SPI
613 #define CONFIG_FSL_ESPI
614 #define CONFIG_SPI_FLASH_SST
615 #define CONFIG_CMD_SF
616 #define CONFIG_SF_DEFAULT_SPEED 10000000
617 #define CONFIG_SF_DEFAULT_MODE 0
621 #ifndef CONFIG_NOBQFMAN
622 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
623 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
624 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
625 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
626 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
627 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
628 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
629 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
630 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
631 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
632 CONFIG_SYS_BMAN_CENA_SIZE)
633 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
634 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
635 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
636 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
637 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
638 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
639 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
640 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
641 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
642 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
643 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
644 CONFIG_SYS_QMAN_CENA_SIZE)
645 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
646 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
648 #define CONFIG_SYS_DPAA_FMAN
649 #define CONFIG_SYS_DPAA_PME
650 #define CONFIG_SYS_PMAN
651 #define CONFIG_SYS_DPAA_DCE
652 #define CONFIG_SYS_DPAA_RMAN
653 #define CONFIG_SYS_INTERLAKEN
655 /* Default address of microcode for the Linux Fman driver */
656 #if defined(CONFIG_SPIFLASH)
658 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
659 * env, so we got 0x110000.
661 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
662 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
663 #elif defined(CONFIG_SDCARD)
665 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
666 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
667 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
669 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
670 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
671 #elif defined(CONFIG_NAND)
672 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
673 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
675 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
676 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
678 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
679 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
680 #endif /* CONFIG_NOBQFMAN */
682 #ifdef CONFIG_SYS_DPAA_FMAN
683 #define CONFIG_FMAN_ENET
684 #define CONFIG_PHYLIB_10G
685 #define CONFIG_PHY_VITESSE
686 #define CONFIG_PHY_CORTINA
687 #define CONFIG_SYS_CORTINA_FW_IN_NOR
688 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
689 #define CONFIG_CORTINA_FW_LENGTH 0x40000
690 #define CONFIG_PHY_TERANETICS
691 #define SGMII_PHY_ADDR1 0x0
692 #define SGMII_PHY_ADDR2 0x1
693 #define SGMII_PHY_ADDR3 0x2
694 #define SGMII_PHY_ADDR4 0x3
695 #define SGMII_PHY_ADDR5 0x4
696 #define SGMII_PHY_ADDR6 0x5
697 #define SGMII_PHY_ADDR7 0x6
698 #define SGMII_PHY_ADDR8 0x7
699 #define FM1_10GEC1_PHY_ADDR 0x10
700 #define FM1_10GEC2_PHY_ADDR 0x11
701 #define FM2_10GEC1_PHY_ADDR 0x12
702 #define FM2_10GEC2_PHY_ADDR 0x13
703 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
704 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
705 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
706 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
711 #ifdef CONFIG_FSL_SATA_V2
712 #define CONFIG_LIBATA
713 #define CONFIG_FSL_SATA
715 #define CONFIG_SYS_SATA_MAX_DEVICE 2
717 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
718 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
720 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
721 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
724 #define CONFIG_CMD_SATA
725 #define CONFIG_DOS_PARTITION
726 #define CONFIG_CMD_EXT2
729 #ifdef CONFIG_FMAN_ENET
730 #define CONFIG_MII /* MII PHY management */
731 #define CONFIG_ETHPRIME "FM1@DTSEC1"
732 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
738 #define CONFIG_CMD_USB
739 #define CONFIG_USB_STORAGE
740 #define CONFIG_USB_EHCI
741 #define CONFIG_USB_EHCI_FSL
742 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
743 #define CONFIG_CMD_EXT2
744 #define CONFIG_HAS_FSL_DR_USB
749 #define CONFIG_FSL_ESDHC
750 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
751 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
752 #define CONFIG_CMD_MMC
753 #define CONFIG_GENERIC_MMC
754 #define CONFIG_CMD_EXT2
755 #define CONFIG_CMD_FAT
756 #define CONFIG_DOS_PARTITION
757 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
760 /* Hash command with SHA acceleration supported in hardware */
761 #ifdef CONFIG_FSL_CAAM
762 #define CONFIG_CMD_HASH
763 #define CONFIG_SHA_HW_ACCEL
766 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
768 #define __USB_PHY_TYPE utmi
771 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
772 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
773 * interleaving. It can be cacheline, page, bank, superbank.
774 * See doc/README.fsl-ddr for details.
776 #ifdef CONFIG_PPC_T4240
777 #define CTRL_INTLV_PREFERED 3way_4KB
779 #define CTRL_INTLV_PREFERED cacheline
782 #define CONFIG_EXTRA_ENV_SETTINGS \
783 "hwconfig=fsl_ddr:" \
784 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
786 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
788 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
789 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
790 "tftpflash=tftpboot $loadaddr $uboot && " \
791 "protect off $ubootaddr +$filesize && " \
792 "erase $ubootaddr +$filesize && " \
793 "cp.b $loadaddr $ubootaddr $filesize && " \
794 "protect on $ubootaddr +$filesize && " \
795 "cmp.b $loadaddr $ubootaddr $filesize\0" \
796 "consoledev=ttyS0\0" \
797 "ramdiskaddr=2000000\0" \
798 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
800 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
803 #define CONFIG_HVBOOT \
804 "setenv bootargs config-addr=0x60000000; " \
805 "bootm 0x01000000 - 0x00f00000"
807 #define CONFIG_LINUX \
808 "setenv bootargs root=/dev/ram rw " \
809 "console=$consoledev,$baudrate $othbootargs;" \
810 "setenv ramdiskaddr 0x02000000;" \
811 "setenv fdtaddr 0x00c00000;" \
812 "setenv loadaddr 0x1000000;" \
813 "bootm $loadaddr $ramdiskaddr $fdtaddr"
815 #define CONFIG_HDBOOT \
816 "setenv bootargs root=/dev/$bdev rw " \
817 "console=$consoledev,$baudrate $othbootargs;" \
818 "tftp $loadaddr $bootfile;" \
819 "tftp $fdtaddr $fdtfile;" \
820 "bootm $loadaddr - $fdtaddr"
822 #define CONFIG_NFSBOOTCOMMAND \
823 "setenv bootargs root=/dev/nfs rw " \
824 "nfsroot=$serverip:$rootpath " \
825 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
826 "console=$consoledev,$baudrate $othbootargs;" \
827 "tftp $loadaddr $bootfile;" \
828 "tftp $fdtaddr $fdtfile;" \
829 "bootm $loadaddr - $fdtaddr"
831 #define CONFIG_RAMBOOTCOMMAND \
832 "setenv bootargs root=/dev/ram rw " \
833 "console=$consoledev,$baudrate $othbootargs;" \
834 "tftp $ramdiskaddr $ramdiskfile;" \
835 "tftp $loadaddr $bootfile;" \
836 "tftp $fdtaddr $fdtfile;" \
837 "bootm $loadaddr $ramdiskaddr $fdtaddr"
839 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
841 #include <asm/fsl_secure_boot.h>
843 #ifdef CONFIG_SECURE_BOOT
844 /* Secure Boot target was not getting build for T4240 because of
845 * increased binary size. So the size is being reduced by removing USB
846 * which is anyways not used in Secure Environment.
848 #undef CONFIG_CMD_USB
849 #define CONFIG_CMD_BLOB
852 #endif /* __CONFIG_H */