ARM: configs: Add da850evm_nand to boot from NAND
[oweals/u-boot.git] / include / configs / T4240QDS.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * T4240 QDS board configuration file
8  */
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #define CONFIG_FSL_SATA_V2
13 #define CONFIG_PCIE4
14
15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
16
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
19 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
22 #else
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
25 #define CONFIG_SPL_PAD_TO               0x40000
26 #define CONFIG_SPL_MAX_SIZE             0x28000
27 #define RESET_VECTOR_OFFSET             0x27FFC
28 #define BOOT_PAGE_OFFSET                0x27000
29
30 #ifdef  CONFIG_NAND
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
32 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
33 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
35 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
37 #define CONFIG_SPL_NAND_BOOT
38 #endif
39
40 #ifdef  CONFIG_SDCARD
41 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
42 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
43 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
44 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
45 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
46 #ifndef CONFIG_SPL_BUILD
47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
48 #endif
49 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
51 #define CONFIG_SPL_MMC_BOOT
52 #endif
53
54 #ifdef CONFIG_SPL_BUILD
55 #define CONFIG_SPL_SKIP_RELOCATE
56 #define CONFIG_SPL_COMMON_INIT_DDR
57 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
58 #endif
59
60 #endif
61 #endif /* CONFIG_RAMBOOT_PBL */
62
63 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
64 /* Set 1M boot space */
65 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
66 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
67                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
68 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
69 #endif
70
71 #define CONFIG_SRIO_PCIE_BOOT_MASTER
72 #define CONFIG_DDR_ECC
73
74 #include "t4qds.h"
75
76 #ifndef CONFIG_MTD_NOR_FLASH
77 #else
78 #define CONFIG_FLASH_CFI_DRIVER
79 #define CONFIG_SYS_FLASH_CFI
80 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
81 #endif
82
83 #if defined(CONFIG_SPIFLASH)
84 #define CONFIG_SYS_EXTRA_ENV_RELOC
85 #define CONFIG_ENV_SPI_BUS              0
86 #define CONFIG_ENV_SPI_CS               0
87 #define CONFIG_ENV_SPI_MAX_HZ           10000000
88 #define CONFIG_ENV_SPI_MODE             0
89 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
90 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
91 #define CONFIG_ENV_SECT_SIZE            0x10000
92 #elif defined(CONFIG_SDCARD)
93 #define CONFIG_SYS_EXTRA_ENV_RELOC
94 #define CONFIG_SYS_MMC_ENV_DEV          0
95 #define CONFIG_ENV_SIZE                 0x2000
96 #define CONFIG_ENV_OFFSET               (512 * 0x800)
97 #elif defined(CONFIG_NAND)
98 #define CONFIG_SYS_EXTRA_ENV_RELOC
99 #define CONFIG_ENV_SIZE                 0x2000
100 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
101 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
102 #define CONFIG_ENV_ADDR         0xffe20000
103 #define CONFIG_ENV_SIZE         0x2000
104 #elif defined(CONFIG_ENV_IS_NOWHERE)
105 #define CONFIG_ENV_SIZE         0x2000
106 #else
107 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
108 #define CONFIG_ENV_SIZE         0x2000
109 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
110 #endif
111
112 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
113 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
114
115 #ifndef __ASSEMBLY__
116 unsigned long get_board_sys_clk(void);
117 unsigned long get_board_ddr_clk(void);
118 #endif
119
120 /* EEPROM */
121 #define CONFIG_ID_EEPROM
122 #define CONFIG_SYS_I2C_EEPROM_NXID
123 #define CONFIG_SYS_EEPROM_BUS_NUM       0
124 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
126
127 /*
128  * DDR Setup
129  */
130 #define CONFIG_SYS_SPD_BUS_NUM  0
131 #define SPD_EEPROM_ADDRESS1     0x51
132 #define SPD_EEPROM_ADDRESS2     0x52
133 #define SPD_EEPROM_ADDRESS3     0x53
134 #define SPD_EEPROM_ADDRESS4     0x54
135 #define SPD_EEPROM_ADDRESS5     0x55
136 #define SPD_EEPROM_ADDRESS6     0x56
137 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
138 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
139
140 /*
141  * IFC Definitions
142  */
143 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
144 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
145                                 + 0x8000000) | \
146                                 CSPR_PORT_SIZE_16 | \
147                                 CSPR_MSEL_NOR | \
148                                 CSPR_V)
149 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
150 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
151                                 CSPR_PORT_SIZE_16 | \
152                                 CSPR_MSEL_NOR | \
153                                 CSPR_V)
154 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
155 /* NOR Flash Timing Params */
156 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
157
158 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
159                                 FTIM0_NOR_TEADC(0x5) | \
160                                 FTIM0_NOR_TEAHC(0x5))
161 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
162                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
163                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
164 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
165                                 FTIM2_NOR_TCH(0x4) | \
166                                 FTIM2_NOR_TWPH(0x0E) | \
167                                 FTIM2_NOR_TWP(0x1c))
168 #define CONFIG_SYS_NOR_FTIM3    0x0
169
170 #define CONFIG_SYS_FLASH_QUIET_TEST
171 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
172
173 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
174 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
177
178 #define CONFIG_SYS_FLASH_EMPTY_INFO
179 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
180                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
181
182 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
183 #define QIXIS_BASE                      0xffdf0000
184 #define QIXIS_LBMAP_SWITCH              6
185 #define QIXIS_LBMAP_MASK                0x0f
186 #define QIXIS_LBMAP_SHIFT               0
187 #define QIXIS_LBMAP_DFLTBANK            0x00
188 #define QIXIS_LBMAP_ALTBANK             0x04
189 #define QIXIS_RST_CTL_RESET             0x83
190 #define QIXIS_RST_FORCE_MEM             0x1
191 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
192 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
193 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
194 #define QIXIS_BRDCFG5                   0x55
195 #define QIXIS_MUX_SDHC                  2
196 #define QIXIS_MUX_SDHC_WIDTH8           1
197 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
198
199 #define CONFIG_SYS_CSPR3_EXT    (0xf)
200 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
201                                 | CSPR_PORT_SIZE_8 \
202                                 | CSPR_MSEL_GPCM \
203                                 | CSPR_V)
204 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
205 #define CONFIG_SYS_CSOR3        0x0
206 /* QIXIS Timing parameters for IFC CS3 */
207 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
208                                         FTIM0_GPCM_TEADC(0x0e) | \
209                                         FTIM0_GPCM_TEAHC(0x0e))
210 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
211                                         FTIM1_GPCM_TRAD(0x3f))
212 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
213                                         FTIM2_GPCM_TCH(0x8) | \
214                                         FTIM2_GPCM_TWP(0x1f))
215 #define CONFIG_SYS_CS3_FTIM3            0x0
216
217 /* NAND Flash on IFC */
218 #define CONFIG_NAND_FSL_IFC
219 #define CONFIG_SYS_NAND_BASE            0xff800000
220 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
221
222 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
223 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
224                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
225                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
226                                 | CSPR_V)
227 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
228
229 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
230                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
231                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
232                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
233                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
234                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
235                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
236
237 #define CONFIG_SYS_NAND_ONFI_DETECTION
238
239 /* ONFI NAND Flash mode0 Timing Params */
240 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
241                                         FTIM0_NAND_TWP(0x18)   | \
242                                         FTIM0_NAND_TWCHT(0x07) | \
243                                         FTIM0_NAND_TWH(0x0a))
244 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
245                                         FTIM1_NAND_TWBE(0x39)  | \
246                                         FTIM1_NAND_TRR(0x0e)   | \
247                                         FTIM1_NAND_TRP(0x18))
248 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
249                                         FTIM2_NAND_TREH(0x0a) | \
250                                         FTIM2_NAND_TWHRE(0x1e))
251 #define CONFIG_SYS_NAND_FTIM3           0x0
252
253 #define CONFIG_SYS_NAND_DDR_LAW         11
254
255 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
256 #define CONFIG_SYS_MAX_NAND_DEVICE      1
257
258 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
259 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
260 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
261
262 #if defined(CONFIG_NAND)
263 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
264 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
265 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
266 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
267 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
268 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
269 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
270 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
271 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
272 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
273 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
274 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
275 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
276 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
277 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
278 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
279 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
280 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
281 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
282 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
283 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
284 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
285 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
286 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
287 #else
288 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
289 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
290 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
291 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
292 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
293 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
294 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
295 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
296 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
297 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
298 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
299 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
300 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
301 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
302 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
303 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
304 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
305 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
306 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
307 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
308 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
309 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
310 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
311 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
312 #endif
313
314 #if defined(CONFIG_RAMBOOT_PBL)
315 #define CONFIG_SYS_RAMBOOT
316 #endif
317
318 /* I2C */
319 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
320 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
321 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
322 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
323
324 #define I2C_MUX_CH_DEFAULT      0x8
325 #define I2C_MUX_CH_VOL_MONITOR  0xa
326 #define I2C_MUX_CH_VSC3316_FS   0xc
327 #define I2C_MUX_CH_VSC3316_BS   0xd
328
329 /* Voltage monitor on channel 2*/
330 #define I2C_VOL_MONITOR_ADDR            0x40
331 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
332 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
333 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
334
335 /* VSC Crossbar switches */
336 #define CONFIG_VSC_CROSSBAR
337 #define VSC3316_FSM_TX_ADDR     0x70
338 #define VSC3316_FSM_RX_ADDR     0x71
339
340 /*
341  * RapidIO
342  */
343
344 /*
345  * for slave u-boot IMAGE instored in master memory space,
346  * PHYS must be aligned based on the SIZE
347  */
348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
352 /*
353  * for slave UCODE and ENV instored in master memory space,
354  * PHYS must be aligned based on the SIZE
355  */
356 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
359
360 /* slave core release by master*/
361 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
362 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
363
364 /*
365  * SRIO_PCIE_BOOT - SLAVE
366  */
367 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
368 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
369 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
370                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
371 #endif
372 /*
373  * eSPI - Enhanced SPI
374  */
375 #define CONFIG_SF_DEFAULT_SPEED         10000000
376 #define CONFIG_SF_DEFAULT_MODE          0
377
378 /* Qman/Bman */
379 #ifndef CONFIG_NOBQFMAN
380 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
381 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
382 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
383 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
384 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
385 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
386 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
387 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
388 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
389                                         CONFIG_SYS_BMAN_CENA_SIZE)
390 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
391 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
392 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
393 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
394 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
395 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
396 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
397 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
398 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
399 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
400 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
401                                         CONFIG_SYS_QMAN_CENA_SIZE)
402 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
403 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
404
405 #define CONFIG_SYS_DPAA_FMAN
406 #define CONFIG_SYS_DPAA_PME
407 #define CONFIG_SYS_PMAN
408 #define CONFIG_SYS_DPAA_DCE
409 #define CONFIG_SYS_DPAA_RMAN
410 #define CONFIG_SYS_INTERLAKEN
411
412 /* Default address of microcode for the Linux Fman driver */
413 #if defined(CONFIG_SPIFLASH)
414 /*
415  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
416  * env, so we got 0x110000.
417  */
418 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
419 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
420 #elif defined(CONFIG_SDCARD)
421 /*
422  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
423  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
424  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
425  */
426 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
427 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
428 #elif defined(CONFIG_NAND)
429 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
430 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
431 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
432 /*
433  * Slave has no ucode locally, it can fetch this from remote. When implementing
434  * in two corenet boards, slave's ucode could be stored in master's memory
435  * space, the address can be mapped from slave TLB->slave LAW->
436  * slave SRIO or PCIE outbound window->master inbound window->
437  * master LAW->the ucode address in master's memory space.
438  */
439 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
440 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
441 #else
442 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
443 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
444 #endif
445 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
446 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
447 #endif /* CONFIG_NOBQFMAN */
448
449 #ifdef CONFIG_SYS_DPAA_FMAN
450 #define CONFIG_FMAN_ENET
451 #define CONFIG_PHYLIB_10G
452 #define CONFIG_PHY_VITESSE
453 #define CONFIG_PHY_TERANETICS
454 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
455 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
456 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
457 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
458 #define FM1_10GEC1_PHY_ADDR     0x0
459 #define FM1_10GEC2_PHY_ADDR     0x1
460 #define FM2_10GEC1_PHY_ADDR     0x2
461 #define FM2_10GEC2_PHY_ADDR     0x3
462 #endif
463
464 /* SATA */
465 #ifdef CONFIG_FSL_SATA_V2
466 #define CONFIG_SYS_SATA_MAX_DEVICE      2
467 #define CONFIG_SATA1
468 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
469 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
470 #define CONFIG_SATA2
471 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
472 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
473
474 #define CONFIG_LBA48
475 #endif
476
477 #ifdef CONFIG_FMAN_ENET
478 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
479 #endif
480
481 /*
482 * USB
483 */
484 #define CONFIG_USB_EHCI_FSL
485 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
486 #define CONFIG_HAS_FSL_DR_USB
487
488 #ifdef CONFIG_MMC
489 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
490 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
491 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
492 #define CONFIG_ESDHC_DETECT_QUIRK \
493         (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
494         IS_SVR_REV(get_svr(), 1, 0))
495 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
496         (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
497 #endif
498
499
500 #define __USB_PHY_TYPE  utmi
501
502 /*
503  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
504  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
505  * interleaving. It can be cacheline, page, bank, superbank.
506  * See doc/README.fsl-ddr for details.
507  */
508 #ifdef CONFIG_ARCH_T4240
509 #define CTRL_INTLV_PREFERED 3way_4KB
510 #else
511 #define CTRL_INTLV_PREFERED cacheline
512 #endif
513
514 #define CONFIG_EXTRA_ENV_SETTINGS                               \
515         "hwconfig=fsl_ddr:"                                     \
516         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
517         "bank_intlv=auto;"                                      \
518         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
519         "netdev=eth0\0"                                         \
520         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
521         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
522         "tftpflash=tftpboot $loadaddr $uboot && "               \
523         "protect off $ubootaddr +$filesize && "                 \
524         "erase $ubootaddr +$filesize && "                       \
525         "cp.b $loadaddr $ubootaddr $filesize && "               \
526         "protect on $ubootaddr +$filesize && "                  \
527         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
528         "consoledev=ttyS0\0"                                    \
529         "ramdiskaddr=2000000\0"                                 \
530         "ramdiskfile=t4240qds/ramdisk.uboot\0"                  \
531         "fdtaddr=1e00000\0"                                     \
532         "fdtfile=t4240qds/t4240qds.dtb\0"                               \
533         "bdev=sda3\0"
534
535 #define CONFIG_HVBOOT                           \
536         "setenv bootargs config-addr=0x60000000; "      \
537         "bootm 0x01000000 - 0x00f00000"
538
539 #define CONFIG_ALU                              \
540         "setenv bootargs root=/dev/$bdev rw "           \
541         "console=$consoledev,$baudrate $othbootargs;"   \
542         "cpu 1 release 0x01000000 - - -;"               \
543         "cpu 2 release 0x01000000 - - -;"               \
544         "cpu 3 release 0x01000000 - - -;"               \
545         "cpu 4 release 0x01000000 - - -;"               \
546         "cpu 5 release 0x01000000 - - -;"               \
547         "cpu 6 release 0x01000000 - - -;"               \
548         "cpu 7 release 0x01000000 - - -;"               \
549         "go 0x01000000"
550
551 #define CONFIG_LINUX                            \
552         "setenv bootargs root=/dev/ram rw "             \
553         "console=$consoledev,$baudrate $othbootargs;"   \
554         "setenv ramdiskaddr 0x02000000;"                \
555         "setenv fdtaddr 0x00c00000;"                    \
556         "setenv loadaddr 0x1000000;"                    \
557         "bootm $loadaddr $ramdiskaddr $fdtaddr"
558
559 #define CONFIG_HDBOOT                                   \
560         "setenv bootargs root=/dev/$bdev rw "           \
561         "console=$consoledev,$baudrate $othbootargs;"   \
562         "tftp $loadaddr $bootfile;"                     \
563         "tftp $fdtaddr $fdtfile;"                       \
564         "bootm $loadaddr - $fdtaddr"
565
566 #define CONFIG_NFSBOOTCOMMAND                   \
567         "setenv bootargs root=/dev/nfs rw "     \
568         "nfsroot=$serverip:$rootpath "          \
569         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
570         "console=$consoledev,$baudrate $othbootargs;"   \
571         "tftp $loadaddr $bootfile;"             \
572         "tftp $fdtaddr $fdtfile;"               \
573         "bootm $loadaddr - $fdtaddr"
574
575 #define CONFIG_RAMBOOTCOMMAND                           \
576         "setenv bootargs root=/dev/ram rw "             \
577         "console=$consoledev,$baudrate $othbootargs;"   \
578         "tftp $ramdiskaddr $ramdiskfile;"               \
579         "tftp $loadaddr $bootfile;"                     \
580         "tftp $fdtaddr $fdtfile;"                       \
581         "bootm $loadaddr $ramdiskaddr $fdtaddr"
582
583 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
584
585 #include <asm/fsl_secure_boot.h>
586
587 #endif  /* __CONFIG_H */