1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
7 * T2080 RDB/PCIe board configuration file
13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
14 #define CONFIG_FSL_SATA_V2
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
18 #define CONFIG_ENABLE_36BIT_PHYS
20 #ifdef CONFIG_PHYS_64BIT
21 #define CONFIG_ADDR_MAP 1
22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
25 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
26 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
27 #define CONFIG_ENV_OVERWRITE
29 #ifdef CONFIG_RAMBOOT_PBL
30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_PAD_TO 0x40000
34 #define CONFIG_SPL_MAX_SIZE 0x28000
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SPL_SKIP_RELOCATE
39 #define CONFIG_SPL_COMMON_INIT_DDR
40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
47 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
51 #ifdef CONFIG_SPIFLASH
52 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
53 #define CONFIG_SPL_SPI_FLASH_MINIMAL
54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
58 #ifndef CONFIG_SPL_BUILD
59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
66 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
67 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
68 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
69 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
70 #ifndef CONFIG_SPL_BUILD
71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
76 #endif /* CONFIG_RAMBOOT_PBL */
78 #define CONFIG_SRIO_PCIE_BOOT_MASTER
79 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
80 /* Set 1M boot space */
81 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
82 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
83 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
84 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
87 #ifndef CONFIG_RESET_VECTOR_ADDRESS
88 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
92 * These can be toggled for performance analysis, otherwise use default.
94 #define CONFIG_SYS_CACHE_STASHING
95 #define CONFIG_BTB /* toggle branch predition */
96 #define CONFIG_DDR_ECC
98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
99 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
102 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
103 #define CONFIG_SYS_MEMTEST_END 0x00400000
105 #if defined(CONFIG_SPIFLASH)
106 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
107 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
108 #define CONFIG_ENV_SECT_SIZE 0x10000
109 #elif defined(CONFIG_SDCARD)
110 #define CONFIG_SYS_MMC_ENV_DEV 0
111 #define CONFIG_ENV_SIZE 0x2000
112 #define CONFIG_ENV_OFFSET (512 * 0x800)
113 #elif defined(CONFIG_NAND)
114 #define CONFIG_ENV_SIZE 0x2000
115 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
116 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
117 #define CONFIG_ENV_ADDR 0xffe20000
118 #define CONFIG_ENV_SIZE 0x2000
119 #elif defined(CONFIG_ENV_IS_NOWHERE)
120 #define CONFIG_ENV_SIZE 0x2000
122 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
123 #define CONFIG_ENV_SIZE 0x2000
124 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
128 unsigned long get_board_sys_clk(void);
129 unsigned long get_board_ddr_clk(void);
132 #define CONFIG_SYS_CLK_FREQ 66660000
133 #define CONFIG_DDR_CLK_FREQ 133330000
136 * Config the L3 Cache as L3 SRAM
138 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
139 #define CONFIG_SYS_L3_SIZE (512 << 10)
140 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
141 #ifdef CONFIG_RAMBOOT_PBL
142 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
144 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
145 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
146 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
148 #define CONFIG_SYS_DCSRBAR 0xf0000000
149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
152 #define CONFIG_ID_EEPROM
153 #define CONFIG_SYS_I2C_EEPROM_NXID
154 #define CONFIG_SYS_EEPROM_BUS_NUM 0
155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
161 #define CONFIG_VERY_BIG_RAM
162 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
163 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
164 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
165 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
166 #define CONFIG_DDR_SPD
167 #define CONFIG_SYS_SPD_BUS_NUM 0
168 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
169 #define SPD_EEPROM_ADDRESS1 0x51
170 #define SPD_EEPROM_ADDRESS2 0x52
171 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
172 #define CTRL_INTLV_PREFERED cacheline
177 #define CONFIG_SYS_FLASH_BASE 0xe8000000
178 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
179 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
180 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
181 CSPR_PORT_SIZE_16 | \
184 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
186 /* NOR Flash Timing Params */
187 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
189 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
190 FTIM0_NOR_TEADC(0x5) | \
191 FTIM0_NOR_TEAHC(0x5))
192 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
193 FTIM1_NOR_TRAD_NOR(0x1A) |\
194 FTIM1_NOR_TSEQRAD_NOR(0x13))
195 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
196 FTIM2_NOR_TCH(0x4) | \
197 FTIM2_NOR_TWPH(0x0E) | \
199 #define CONFIG_SYS_NOR_FTIM3 0x0
201 #define CONFIG_SYS_FLASH_QUIET_TEST
202 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
204 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
205 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
206 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
207 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
208 #define CONFIG_SYS_FLASH_EMPTY_INFO
209 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
212 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
213 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
214 #define CONFIG_SYS_CSPR2_EXT (0xf)
215 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
219 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
220 #define CONFIG_SYS_CSOR2 0x0
222 /* CPLD Timing parameters for IFC CS2 */
223 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
224 FTIM0_GPCM_TEADC(0x0e) | \
225 FTIM0_GPCM_TEAHC(0x0e))
226 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
227 FTIM1_GPCM_TRAD(0x1f))
228 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
229 FTIM2_GPCM_TCH(0x8) | \
230 FTIM2_GPCM_TWP(0x1f))
231 #define CONFIG_SYS_CS2_FTIM3 0x0
233 /* NAND Flash on IFC */
234 #define CONFIG_NAND_FSL_IFC
235 #define CONFIG_SYS_NAND_BASE 0xff800000
236 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
238 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
239 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
240 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
241 | CSPR_MSEL_NAND /* MSEL = NAND */ \
243 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
245 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
246 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
247 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
248 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
249 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
250 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
251 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
253 #define CONFIG_SYS_NAND_ONFI_DETECTION
255 /* ONFI NAND Flash mode0 Timing Params */
256 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
257 FTIM0_NAND_TWP(0x18) | \
258 FTIM0_NAND_TWCHT(0x07) | \
259 FTIM0_NAND_TWH(0x0a))
260 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
261 FTIM1_NAND_TWBE(0x39) | \
262 FTIM1_NAND_TRR(0x0e) | \
263 FTIM1_NAND_TRP(0x18))
264 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
265 FTIM2_NAND_TREH(0x0a) | \
266 FTIM2_NAND_TWHRE(0x1e))
267 #define CONFIG_SYS_NAND_FTIM3 0x0
269 #define CONFIG_SYS_NAND_DDR_LAW 11
270 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
271 #define CONFIG_SYS_MAX_NAND_DEVICE 1
272 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
274 #if defined(CONFIG_NAND)
275 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
276 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
277 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
278 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
279 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
280 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
281 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
282 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
283 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
284 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
285 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
286 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
287 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
288 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
289 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
290 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
292 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
293 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
294 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
295 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
296 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
297 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
298 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
299 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
300 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
301 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
302 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
303 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
304 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
305 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
306 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
307 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
310 #if defined(CONFIG_RAMBOOT_PBL)
311 #define CONFIG_SYS_RAMBOOT
314 #ifdef CONFIG_SPL_BUILD
315 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
317 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
320 #define CONFIG_HWCONFIG
322 /* define to use L1 as initial stack */
323 #define CONFIG_L1_INIT_RAM
324 #define CONFIG_SYS_INIT_RAM_LOCK
325 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
326 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
328 /* The assembler doesn't like typecast */
329 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
330 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
331 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
332 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
333 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
334 GENERATED_GBL_DATA_SIZE)
335 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
336 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
337 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
342 #define CONFIG_SYS_NS16550_SERIAL
343 #define CONFIG_SYS_NS16550_REG_SIZE 1
344 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
345 #define CONFIG_SYS_BAUDRATE_TABLE \
346 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
347 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
348 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
349 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
350 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
355 #define CONFIG_SYS_I2C
356 #define CONFIG_SYS_I2C_FSL
357 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
358 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
359 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
360 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
361 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
362 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
363 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
364 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
365 #define CONFIG_SYS_FSL_I2C_SPEED 100000
366 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
367 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
368 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
369 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
370 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
371 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
372 #define I2C_MUX_CH_DEFAULT 0x8
374 #define I2C_MUX_CH_VOL_MONITOR 0xa
376 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
377 #ifndef CONFIG_SPL_BUILD
380 #define CONFIG_VOL_MONITOR_IR36021_SET
381 #define CONFIG_VOL_MONITOR_IR36021_READ
382 /* The lowest and highest voltage allowed for T208xRDB */
383 #define VDD_MV_MIN 819
384 #define VDD_MV_MAX 1212
389 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
390 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
391 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
392 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
393 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
394 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
396 * for slave u-boot IMAGE instored in master memory space,
397 * PHYS must be aligned based on the SIZE
399 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
400 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
401 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
402 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
404 * for slave UCODE and ENV instored in master memory space,
405 * PHYS must be aligned based on the SIZE
407 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
408 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
409 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
411 /* slave core release by master*/
412 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
413 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
416 * SRIO_PCIE_BOOT - SLAVE
418 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
419 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
420 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
421 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
425 * eSPI - Enhanced SPI
430 * Memory space is mapped 1-1, but I/O space must start from 0.
432 #define CONFIG_PCIE1 /* PCIE controller 1 */
433 #define CONFIG_PCIE2 /* PCIE controller 2 */
434 #define CONFIG_PCIE3 /* PCIE controller 3 */
435 #define CONFIG_PCIE4 /* PCIE controller 4 */
436 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
437 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
438 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
439 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
440 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
441 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
442 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
443 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
444 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
445 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
446 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
448 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
449 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
452 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
453 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
454 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
455 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
456 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
458 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
459 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
460 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
461 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
462 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
463 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
464 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
465 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
466 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
468 /* controller 4, Base address 203000 */
469 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
470 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
472 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
473 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
474 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
475 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
478 #define CONFIG_PCI_INDIRECT_BRIDGE
479 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
480 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
484 #ifndef CONFIG_NOBQFMAN
485 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
486 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
487 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
488 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
489 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
490 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
491 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
492 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
493 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
494 CONFIG_SYS_BMAN_CENA_SIZE)
495 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
496 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
497 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
498 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
499 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
500 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
501 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
502 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
503 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
504 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
505 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
506 CONFIG_SYS_QMAN_CENA_SIZE)
507 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
508 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
510 #define CONFIG_SYS_DPAA_FMAN
511 #define CONFIG_SYS_DPAA_PME
512 #define CONFIG_SYS_PMAN
513 #define CONFIG_SYS_DPAA_DCE
514 #define CONFIG_SYS_DPAA_RMAN /* RMan */
515 #define CONFIG_SYS_INTERLAKEN
517 /* Default address of microcode for the Linux Fman driver */
518 #if defined(CONFIG_SPIFLASH)
520 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
521 * env, so we got 0x110000.
523 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
524 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
525 #define CONFIG_CORTINA_FW_ADDR 0x120000
527 #elif defined(CONFIG_SDCARD)
529 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
530 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
531 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
533 #define CONFIG_SYS_CORTINA_FW_IN_MMC
534 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
535 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
537 #elif defined(CONFIG_NAND)
538 #define CONFIG_SYS_CORTINA_FW_IN_NAND
539 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
540 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
541 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
543 * Slave has no ucode locally, it can fetch this from remote. When implementing
544 * in two corenet boards, slave's ucode could be stored in master's memory
545 * space, the address can be mapped from slave TLB->slave LAW->
546 * slave SRIO or PCIE outbound window->master inbound window->
547 * master LAW->the ucode address in master's memory space.
549 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
550 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
551 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
553 #define CONFIG_SYS_CORTINA_FW_IN_NOR
554 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
555 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
557 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
558 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
559 #endif /* CONFIG_NOBQFMAN */
561 #ifdef CONFIG_SYS_DPAA_FMAN
562 #define CONFIG_PHY_CORTINA
563 #define CONFIG_PHY_REALTEK
564 #define CONFIG_CORTINA_FW_LENGTH 0x40000
565 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
566 #define RGMII_PHY2_ADDR 0x02
567 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
568 #define CORTINA_PHY_ADDR2 0x0d
569 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
570 #define FM1_10GEC4_PHY_ADDR 0x01
573 #ifdef CONFIG_FMAN_ENET
574 #define CONFIG_ETHPRIME "FM1@DTSEC3"
580 #ifdef CONFIG_FSL_SATA_V2
581 #define CONFIG_SYS_SATA_MAX_DEVICE 2
583 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
584 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
586 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
587 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
594 #ifdef CONFIG_USB_EHCI_HCD
595 #define CONFIG_USB_EHCI_FSL
596 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
597 #define CONFIG_HAS_FSL_DR_USB
604 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
605 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
606 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
610 * Dynamic MTD Partition support with mtdparts
618 * Miscellaneous configurable options
620 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
623 * For booting Linux, the board info and command line data
624 * have to be in the first 64 MB of memory, since this is
625 * the maximum mapped by the Linux kernel during initialization.
627 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
628 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
630 #ifdef CONFIG_CMD_KGDB
631 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
632 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
636 * Environment Configuration
638 #define CONFIG_ROOTPATH "/opt/nfsroot"
639 #define CONFIG_BOOTFILE "uImage"
640 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
642 /* default location for tftp and bootm */
643 #define CONFIG_LOADADDR 1000000
644 #define __USB_PHY_TYPE utmi
646 #define CONFIG_EXTRA_ENV_SETTINGS \
647 "hwconfig=fsl_ddr:" \
648 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
650 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
652 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
653 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
654 "tftpflash=tftpboot $loadaddr $uboot && " \
655 "protect off $ubootaddr +$filesize && " \
656 "erase $ubootaddr +$filesize && " \
657 "cp.b $loadaddr $ubootaddr $filesize && " \
658 "protect on $ubootaddr +$filesize && " \
659 "cmp.b $loadaddr $ubootaddr $filesize\0" \
660 "consoledev=ttyS0\0" \
661 "ramdiskaddr=2000000\0" \
662 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
663 "fdtaddr=1e00000\0" \
664 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
668 * For emulation this causes u-boot to jump to the start of the
669 * proof point app code automatically
671 #define CONFIG_PROOF_POINTS \
672 "setenv bootargs root=/dev/$bdev rw " \
673 "console=$consoledev,$baudrate $othbootargs;" \
674 "cpu 1 release 0x29000000 - - -;" \
675 "cpu 2 release 0x29000000 - - -;" \
676 "cpu 3 release 0x29000000 - - -;" \
677 "cpu 4 release 0x29000000 - - -;" \
678 "cpu 5 release 0x29000000 - - -;" \
679 "cpu 6 release 0x29000000 - - -;" \
680 "cpu 7 release 0x29000000 - - -;" \
683 #define CONFIG_HVBOOT \
684 "setenv bootargs config-addr=0x60000000; " \
685 "bootm 0x01000000 - 0x00f00000"
688 "setenv bootargs root=/dev/$bdev rw " \
689 "console=$consoledev,$baudrate $othbootargs;" \
690 "cpu 1 release 0x01000000 - - -;" \
691 "cpu 2 release 0x01000000 - - -;" \
692 "cpu 3 release 0x01000000 - - -;" \
693 "cpu 4 release 0x01000000 - - -;" \
694 "cpu 5 release 0x01000000 - - -;" \
695 "cpu 6 release 0x01000000 - - -;" \
696 "cpu 7 release 0x01000000 - - -;" \
699 #define CONFIG_LINUX \
700 "setenv bootargs root=/dev/ram rw " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "setenv ramdiskaddr 0x02000000;" \
703 "setenv fdtaddr 0x00c00000;" \
704 "setenv loadaddr 0x1000000;" \
705 "bootm $loadaddr $ramdiskaddr $fdtaddr"
707 #define CONFIG_HDBOOT \
708 "setenv bootargs root=/dev/$bdev rw " \
709 "console=$consoledev,$baudrate $othbootargs;" \
710 "tftp $loadaddr $bootfile;" \
711 "tftp $fdtaddr $fdtfile;" \
712 "bootm $loadaddr - $fdtaddr"
714 #define CONFIG_NFSBOOTCOMMAND \
715 "setenv bootargs root=/dev/nfs rw " \
716 "nfsroot=$serverip:$rootpath " \
717 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
718 "console=$consoledev,$baudrate $othbootargs;" \
719 "tftp $loadaddr $bootfile;" \
720 "tftp $fdtaddr $fdtfile;" \
721 "bootm $loadaddr - $fdtaddr"
723 #define CONFIG_RAMBOOTCOMMAND \
724 "setenv bootargs root=/dev/ram rw " \
725 "console=$consoledev,$baudrate $othbootargs;" \
726 "tftp $ramdiskaddr $ramdiskfile;" \
727 "tftp $loadaddr $bootfile;" \
728 "tftp $fdtaddr $fdtfile;" \
729 "bootm $loadaddr $ramdiskaddr $fdtaddr"
731 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
733 #include <asm/fsl_secure_boot.h>
735 #endif /* __T2080RDB_H */