2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T2080 RDB/PCIe board configuration file
14 #define CONFIG_DISPLAY_BOARDINFO
15 #define CONFIG_T2080RDB
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 #define CONFIG_USB_EHCI
19 #define CONFIG_FSL_SATA_V2
21 /* High Level Configuration Options */
22 #define CONFIG_PHYS_64BIT
24 #define CONFIG_E500 /* BOOKE e500 family */
25 #define CONFIG_E500MC /* BOOKE e500mc family */
26 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
27 #define CONFIG_MP /* support multiple processors */
28 #define CONFIG_ENABLE_36BIT_PHYS
30 #ifdef CONFIG_PHYS_64BIT
31 #define CONFIG_ADDR_MAP 1
32 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
36 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
37 #define CONFIG_FSL_IFC /* Enable IFC Support */
38 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
39 #define CONFIG_FSL_LAW /* Use common FSL init code */
40 #define CONFIG_ENV_OVERWRITE
42 #ifdef CONFIG_RAMBOOT_PBL
43 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
44 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
47 #define CONFIG_SPL_ENV_SUPPORT
48 #define CONFIG_SPL_SERIAL_SUPPORT
49 #define CONFIG_SPL_FLUSH_IMAGE
50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
51 #define CONFIG_SPL_LIBGENERIC_SUPPORT
52 #define CONFIG_SPL_LIBCOMMON_SUPPORT
53 #define CONFIG_SPL_I2C_SUPPORT
54 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
55 #define CONFIG_FSL_LAW /* Use common FSL init code */
56 #define CONFIG_SYS_TEXT_BASE 0x00201000
57 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
58 #define CONFIG_SPL_PAD_TO 0x40000
59 #define CONFIG_SPL_MAX_SIZE 0x28000
60 #define RESET_VECTOR_OFFSET 0x27FFC
61 #define BOOT_PAGE_OFFSET 0x27000
62 #ifdef CONFIG_SPL_BUILD
63 #define CONFIG_SPL_SKIP_RELOCATE
64 #define CONFIG_SPL_COMMON_INIT_DDR
65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
66 #define CONFIG_SYS_NO_FLASH
70 #define CONFIG_SPL_NAND_SUPPORT
71 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
72 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
73 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
74 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
76 #define CONFIG_SPL_NAND_BOOT
79 #ifdef CONFIG_SPIFLASH
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
81 #define CONFIG_SPL_SPI_SUPPORT
82 #define CONFIG_SPL_SPI_FLASH_SUPPORT
83 #define CONFIG_SPL_SPI_FLASH_MINIMAL
84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
89 #ifndef CONFIG_SPL_BUILD
90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
92 #define CONFIG_SPL_SPI_BOOT
96 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
97 #define CONFIG_SPL_MMC_SUPPORT
98 #define CONFIG_SPL_MMC_MINIMAL
99 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
100 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
101 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
102 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
103 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
104 #ifndef CONFIG_SPL_BUILD
105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
107 #define CONFIG_SPL_MMC_BOOT
110 #endif /* CONFIG_RAMBOOT_PBL */
112 #define CONFIG_SRIO_PCIE_BOOT_MASTER
113 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
114 /* Set 1M boot space */
115 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
116 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
117 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
118 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
119 #define CONFIG_SYS_NO_FLASH
122 #ifndef CONFIG_SYS_TEXT_BASE
123 #define CONFIG_SYS_TEXT_BASE 0xeff40000
126 #ifndef CONFIG_RESET_VECTOR_ADDRESS
127 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
131 * These can be toggled for performance analysis, otherwise use default.
133 #define CONFIG_SYS_CACHE_STASHING
134 #define CONFIG_BTB /* toggle branch predition */
135 #define CONFIG_DDR_ECC
136 #ifdef CONFIG_DDR_ECC
137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
138 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
141 #define CONFIG_CMD_MEMTEST
142 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
143 #define CONFIG_SYS_MEMTEST_END 0x00400000
144 #define CONFIG_SYS_ALT_MEMTEST
146 #ifndef CONFIG_SYS_NO_FLASH
147 #define CONFIG_FLASH_CFI_DRIVER
148 #define CONFIG_SYS_FLASH_CFI
149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
152 #if defined(CONFIG_SPIFLASH)
153 #define CONFIG_SYS_EXTRA_ENV_RELOC
154 #define CONFIG_ENV_IS_IN_SPI_FLASH
155 #define CONFIG_ENV_SPI_BUS 0
156 #define CONFIG_ENV_SPI_CS 0
157 #define CONFIG_ENV_SPI_MAX_HZ 10000000
158 #define CONFIG_ENV_SPI_MODE 0
159 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
160 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
161 #define CONFIG_ENV_SECT_SIZE 0x10000
162 #elif defined(CONFIG_SDCARD)
163 #define CONFIG_SYS_EXTRA_ENV_RELOC
164 #define CONFIG_ENV_IS_IN_MMC
165 #define CONFIG_SYS_MMC_ENV_DEV 0
166 #define CONFIG_ENV_SIZE 0x2000
167 #define CONFIG_ENV_OFFSET (512 * 0x800)
168 #elif defined(CONFIG_NAND)
169 #define CONFIG_SYS_EXTRA_ENV_RELOC
170 #define CONFIG_ENV_IS_IN_NAND
171 #define CONFIG_ENV_SIZE 0x2000
172 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
173 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
174 #define CONFIG_ENV_IS_IN_REMOTE
175 #define CONFIG_ENV_ADDR 0xffe20000
176 #define CONFIG_ENV_SIZE 0x2000
177 #elif defined(CONFIG_ENV_IS_NOWHERE)
178 #define CONFIG_ENV_SIZE 0x2000
180 #define CONFIG_ENV_IS_IN_FLASH
181 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
182 #define CONFIG_ENV_SIZE 0x2000
183 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
187 unsigned long get_board_sys_clk(void);
188 unsigned long get_board_ddr_clk(void);
191 #define CONFIG_SYS_CLK_FREQ 66660000
192 #define CONFIG_DDR_CLK_FREQ 133330000
195 * Config the L3 Cache as L3 SRAM
197 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
198 #define CONFIG_SYS_L3_SIZE (512 << 10)
199 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
200 #ifdef CONFIG_RAMBOOT_PBL
201 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
203 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
204 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
205 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
206 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
208 #define CONFIG_SYS_DCSRBAR 0xf0000000
209 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
212 #define CONFIG_ID_EEPROM
213 #define CONFIG_SYS_I2C_EEPROM_NXID
214 #define CONFIG_SYS_EEPROM_BUS_NUM 0
215 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
221 #define CONFIG_VERY_BIG_RAM
222 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
223 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
224 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
225 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
226 #define CONFIG_DDR_SPD
227 #define CONFIG_SYS_FSL_DDR3
228 #undef CONFIG_FSL_DDR_INTERACTIVE
229 #define CONFIG_SYS_SPD_BUS_NUM 0
230 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
231 #define SPD_EEPROM_ADDRESS1 0x51
232 #define SPD_EEPROM_ADDRESS2 0x52
233 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
234 #define CTRL_INTLV_PREFERED cacheline
239 #define CONFIG_SYS_FLASH_BASE 0xe8000000
240 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
241 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
242 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
243 CSPR_PORT_SIZE_16 | \
246 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
248 /* NOR Flash Timing Params */
249 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
251 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
252 FTIM0_NOR_TEADC(0x5) | \
253 FTIM0_NOR_TEAHC(0x5))
254 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
255 FTIM1_NOR_TRAD_NOR(0x1A) |\
256 FTIM1_NOR_TSEQRAD_NOR(0x13))
257 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
258 FTIM2_NOR_TCH(0x4) | \
259 FTIM2_NOR_TWPH(0x0E) | \
261 #define CONFIG_SYS_NOR_FTIM3 0x0
263 #define CONFIG_SYS_FLASH_QUIET_TEST
264 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
266 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
267 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
268 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
269 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
270 #define CONFIG_SYS_FLASH_EMPTY_INFO
271 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
274 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
275 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
276 #define CONFIG_SYS_CSPR2_EXT (0xf)
277 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
281 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
282 #define CONFIG_SYS_CSOR2 0x0
284 /* CPLD Timing parameters for IFC CS2 */
285 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
286 FTIM0_GPCM_TEADC(0x0e) | \
287 FTIM0_GPCM_TEAHC(0x0e))
288 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
289 FTIM1_GPCM_TRAD(0x1f))
290 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
291 FTIM2_GPCM_TCH(0x8) | \
292 FTIM2_GPCM_TWP(0x1f))
293 #define CONFIG_SYS_CS2_FTIM3 0x0
295 /* NAND Flash on IFC */
296 #define CONFIG_NAND_FSL_IFC
297 #define CONFIG_SYS_NAND_BASE 0xff800000
298 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
300 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
301 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
302 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
303 | CSPR_MSEL_NAND /* MSEL = NAND */ \
305 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
307 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
308 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
309 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
310 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
311 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
312 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
313 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
315 #define CONFIG_SYS_NAND_ONFI_DETECTION
317 /* ONFI NAND Flash mode0 Timing Params */
318 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
319 FTIM0_NAND_TWP(0x18) | \
320 FTIM0_NAND_TWCHT(0x07) | \
321 FTIM0_NAND_TWH(0x0a))
322 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
323 FTIM1_NAND_TWBE(0x39) | \
324 FTIM1_NAND_TRR(0x0e) | \
325 FTIM1_NAND_TRP(0x18))
326 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
327 FTIM2_NAND_TREH(0x0a) | \
328 FTIM2_NAND_TWHRE(0x1e))
329 #define CONFIG_SYS_NAND_FTIM3 0x0
331 #define CONFIG_SYS_NAND_DDR_LAW 11
332 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
333 #define CONFIG_SYS_MAX_NAND_DEVICE 1
334 #define CONFIG_CMD_NAND
335 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
337 #if defined(CONFIG_NAND)
338 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
339 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
340 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
341 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
342 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
343 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
344 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
345 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
346 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
347 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
348 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
349 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
350 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
351 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
352 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
353 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
355 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
356 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
357 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
358 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
359 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
360 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
361 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
362 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
363 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
364 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
365 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
366 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
367 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
368 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
369 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
370 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
373 #if defined(CONFIG_RAMBOOT_PBL)
374 #define CONFIG_SYS_RAMBOOT
377 #ifdef CONFIG_SPL_BUILD
378 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
380 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
383 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
384 #define CONFIG_MISC_INIT_R
385 #define CONFIG_HWCONFIG
387 /* define to use L1 as initial stack */
388 #define CONFIG_L1_INIT_RAM
389 #define CONFIG_SYS_INIT_RAM_LOCK
390 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
393 /* The assembler doesn't like typecast */
394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
395 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
396 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
397 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
398 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
399 GENERATED_GBL_DATA_SIZE)
400 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
401 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
402 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
407 #define CONFIG_CONS_INDEX 1
408 #define CONFIG_SYS_NS16550_SERIAL
409 #define CONFIG_SYS_NS16550_REG_SIZE 1
410 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
411 #define CONFIG_SYS_BAUDRATE_TABLE \
412 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
413 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
414 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
415 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
416 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
418 /* Use the HUSH parser */
419 #define CONFIG_SYS_HUSH_PARSER
420 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
425 #define CONFIG_SYS_I2C
426 #define CONFIG_SYS_I2C_FSL
427 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
428 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
429 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
430 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
431 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
432 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
433 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
434 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
435 #define CONFIG_SYS_FSL_I2C_SPEED 100000
436 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
437 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
438 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
439 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
440 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
441 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
442 #define I2C_MUX_CH_DEFAULT 0x8
444 #define I2C_MUX_CH_VOL_MONITOR 0xa
446 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
447 #ifndef CONFIG_SPL_BUILD
450 #define CONFIG_VOL_MONITOR_IR36021_SET
451 #define CONFIG_VOL_MONITOR_IR36021_READ
452 /* The lowest and highest voltage allowed for T208xRDB */
453 #define VDD_MV_MIN 819
454 #define VDD_MV_MAX 1212
459 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
460 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
461 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
462 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
463 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
464 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
466 * for slave u-boot IMAGE instored in master memory space,
467 * PHYS must be aligned based on the SIZE
469 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
470 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
471 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
472 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
474 * for slave UCODE and ENV instored in master memory space,
475 * PHYS must be aligned based on the SIZE
477 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
478 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
479 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
481 /* slave core release by master*/
482 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
483 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
486 * SRIO_PCIE_BOOT - SLAVE
488 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
489 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
490 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
491 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
495 * eSPI - Enhanced SPI
497 #ifdef CONFIG_SPI_FLASH
498 #define CONFIG_SPI_FLASH_BAR
499 #define CONFIG_CMD_SF
500 #define CONFIG_SF_DEFAULT_SPEED 10000000
501 #define CONFIG_SF_DEFAULT_MODE 0
506 * Memory space is mapped 1-1, but I/O space must start from 0.
508 #define CONFIG_PCI /* Enable PCI/PCIE */
509 #define CONFIG_PCIE1 /* PCIE controler 1 */
510 #define CONFIG_PCIE2 /* PCIE controler 2 */
511 #define CONFIG_PCIE3 /* PCIE controler 3 */
512 #define CONFIG_PCIE4 /* PCIE controler 4 */
513 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
514 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
515 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
516 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
517 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
518 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
519 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
520 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
521 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
522 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
523 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
525 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
526 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
527 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
528 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
529 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
530 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
531 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
532 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
533 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
535 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
536 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
537 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
538 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
539 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
540 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
541 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
542 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
543 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
545 /* controller 4, Base address 203000 */
546 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
547 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
548 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
549 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
550 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
551 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
552 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
555 #define CONFIG_PCI_INDIRECT_BRIDGE
556 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
557 #define CONFIG_PCI_PNP /* do pci plug-and-play */
558 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
559 #define CONFIG_DOS_PARTITION
563 #ifndef CONFIG_NOBQFMAN
564 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
565 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
566 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
567 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
568 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
569 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
570 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
571 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
572 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
573 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
574 CONFIG_SYS_BMAN_CENA_SIZE)
575 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
576 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
577 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
578 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
579 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
580 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
581 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
582 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
583 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
584 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
585 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
586 CONFIG_SYS_QMAN_CENA_SIZE)
587 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
588 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
590 #define CONFIG_SYS_DPAA_FMAN
591 #define CONFIG_SYS_DPAA_PME
592 #define CONFIG_SYS_PMAN
593 #define CONFIG_SYS_DPAA_DCE
594 #define CONFIG_SYS_DPAA_RMAN /* RMan */
595 #define CONFIG_SYS_INTERLAKEN
597 /* Default address of microcode for the Linux Fman driver */
598 #if defined(CONFIG_SPIFLASH)
600 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
601 * env, so we got 0x110000.
603 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
604 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
605 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
606 #define CONFIG_CORTINA_FW_ADDR 0x120000
608 #elif defined(CONFIG_SDCARD)
610 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
611 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
612 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
614 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
615 #define CONFIG_SYS_CORTINA_FW_IN_MMC
616 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
617 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
619 #elif defined(CONFIG_NAND)
620 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
621 #define CONFIG_SYS_CORTINA_FW_IN_NAND
622 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
623 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
624 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
626 * Slave has no ucode locally, it can fetch this from remote. When implementing
627 * in two corenet boards, slave's ucode could be stored in master's memory
628 * space, the address can be mapped from slave TLB->slave LAW->
629 * slave SRIO or PCIE outbound window->master inbound window->
630 * master LAW->the ucode address in master's memory space.
632 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
633 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
634 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
635 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
637 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
638 #define CONFIG_SYS_CORTINA_FW_IN_NOR
639 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
640 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
642 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
643 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
644 #endif /* CONFIG_NOBQFMAN */
646 #ifdef CONFIG_SYS_DPAA_FMAN
647 #define CONFIG_FMAN_ENET
648 #define CONFIG_PHYLIB_10G
649 #define CONFIG_PHY_AQUANTIA
650 #define CONFIG_PHY_CORTINA
651 #define CONFIG_PHY_REALTEK
652 #define CONFIG_CORTINA_FW_LENGTH 0x40000
653 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
654 #define RGMII_PHY2_ADDR 0x02
655 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
656 #define CORTINA_PHY_ADDR2 0x0d
657 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
658 #define FM1_10GEC4_PHY_ADDR 0x01
662 #ifdef CONFIG_FMAN_ENET
663 #define CONFIG_MII /* MII PHY management */
664 #define CONFIG_ETHPRIME "FM1@DTSEC3"
665 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
671 #ifdef CONFIG_FSL_SATA_V2
672 #define CONFIG_LIBATA
673 #define CONFIG_FSL_SATA
674 #define CONFIG_SYS_SATA_MAX_DEVICE 2
676 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
677 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
679 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
680 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
682 #define CONFIG_CMD_SATA
683 #define CONFIG_DOS_PARTITION
684 #define CONFIG_CMD_EXT2
690 #ifdef CONFIG_USB_EHCI
691 #define CONFIG_CMD_USB
692 #define CONFIG_USB_STORAGE
693 #define CONFIG_USB_EHCI_FSL
694 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
695 #define CONFIG_CMD_EXT2
696 #define CONFIG_HAS_FSL_DR_USB
703 #define CONFIG_CMD_MMC
704 #define CONFIG_FSL_ESDHC
705 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
706 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
707 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
708 #define CONFIG_GENERIC_MMC
709 #define CONFIG_CMD_EXT2
710 #define CONFIG_CMD_FAT
711 #define CONFIG_DOS_PARTITION
715 * Dynamic MTD Partition support with mtdparts
717 #ifndef CONFIG_SYS_NO_FLASH
718 #define CONFIG_MTD_DEVICE
719 #define CONFIG_MTD_PARTITIONS
720 #define CONFIG_CMD_MTDPARTS
721 #define CONFIG_FLASH_CFI_MTD
722 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
724 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
725 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
726 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
727 "1m(uboot),5m(kernel),128k(dtb),-(user)"
735 * Command line configuration.
737 #define CONFIG_CMD_DHCP
738 #define CONFIG_CMD_ERRATA
739 #define CONFIG_CMD_MII
740 #define CONFIG_CMD_I2C
741 #define CONFIG_CMD_PING
742 #define CONFIG_CMD_REGINFO
745 #define CONFIG_CMD_PCI
748 /* Hash command with SHA acceleration supported in hardware */
749 #ifdef CONFIG_FSL_CAAM
750 #define CONFIG_CMD_HASH
751 #define CONFIG_SHA_HW_ACCEL
755 * Miscellaneous configurable options
757 #define CONFIG_SYS_LONGHELP /* undef to save memory */
758 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
759 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
760 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
761 #ifdef CONFIG_CMD_KGDB
762 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
764 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
766 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
767 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
768 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
771 * For booting Linux, the board info and command line data
772 * have to be in the first 64 MB of memory, since this is
773 * the maximum mapped by the Linux kernel during initialization.
775 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
776 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
778 #ifdef CONFIG_CMD_KGDB
779 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
780 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
784 * Environment Configuration
786 #define CONFIG_ROOTPATH "/opt/nfsroot"
787 #define CONFIG_BOOTFILE "uImage"
788 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
790 /* default location for tftp and bootm */
791 #define CONFIG_LOADADDR 1000000
792 #define CONFIG_BAUDRATE 115200
793 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
794 #define __USB_PHY_TYPE utmi
796 #define CONFIG_EXTRA_ENV_SETTINGS \
797 "hwconfig=fsl_ddr:" \
798 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
800 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
802 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
803 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
804 "tftpflash=tftpboot $loadaddr $uboot && " \
805 "protect off $ubootaddr +$filesize && " \
806 "erase $ubootaddr +$filesize && " \
807 "cp.b $loadaddr $ubootaddr $filesize && " \
808 "protect on $ubootaddr +$filesize && " \
809 "cmp.b $loadaddr $ubootaddr $filesize\0" \
810 "consoledev=ttyS0\0" \
811 "ramdiskaddr=2000000\0" \
812 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
814 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
818 * For emulation this causes u-boot to jump to the start of the
819 * proof point app code automatically
821 #define CONFIG_PROOF_POINTS \
822 "setenv bootargs root=/dev/$bdev rw " \
823 "console=$consoledev,$baudrate $othbootargs;" \
824 "cpu 1 release 0x29000000 - - -;" \
825 "cpu 2 release 0x29000000 - - -;" \
826 "cpu 3 release 0x29000000 - - -;" \
827 "cpu 4 release 0x29000000 - - -;" \
828 "cpu 5 release 0x29000000 - - -;" \
829 "cpu 6 release 0x29000000 - - -;" \
830 "cpu 7 release 0x29000000 - - -;" \
833 #define CONFIG_HVBOOT \
834 "setenv bootargs config-addr=0x60000000; " \
835 "bootm 0x01000000 - 0x00f00000"
838 "setenv bootargs root=/dev/$bdev rw " \
839 "console=$consoledev,$baudrate $othbootargs;" \
840 "cpu 1 release 0x01000000 - - -;" \
841 "cpu 2 release 0x01000000 - - -;" \
842 "cpu 3 release 0x01000000 - - -;" \
843 "cpu 4 release 0x01000000 - - -;" \
844 "cpu 5 release 0x01000000 - - -;" \
845 "cpu 6 release 0x01000000 - - -;" \
846 "cpu 7 release 0x01000000 - - -;" \
849 #define CONFIG_LINUX \
850 "setenv bootargs root=/dev/ram rw " \
851 "console=$consoledev,$baudrate $othbootargs;" \
852 "setenv ramdiskaddr 0x02000000;" \
853 "setenv fdtaddr 0x00c00000;" \
854 "setenv loadaddr 0x1000000;" \
855 "bootm $loadaddr $ramdiskaddr $fdtaddr"
857 #define CONFIG_HDBOOT \
858 "setenv bootargs root=/dev/$bdev rw " \
859 "console=$consoledev,$baudrate $othbootargs;" \
860 "tftp $loadaddr $bootfile;" \
861 "tftp $fdtaddr $fdtfile;" \
862 "bootm $loadaddr - $fdtaddr"
864 #define CONFIG_NFSBOOTCOMMAND \
865 "setenv bootargs root=/dev/nfs rw " \
866 "nfsroot=$serverip:$rootpath " \
867 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
868 "console=$consoledev,$baudrate $othbootargs;" \
869 "tftp $loadaddr $bootfile;" \
870 "tftp $fdtaddr $fdtfile;" \
871 "bootm $loadaddr - $fdtaddr"
873 #define CONFIG_RAMBOOTCOMMAND \
874 "setenv bootargs root=/dev/ram rw " \
875 "console=$consoledev,$baudrate $othbootargs;" \
876 "tftp $ramdiskaddr $ramdiskfile;" \
877 "tftp $loadaddr $bootfile;" \
878 "tftp $fdtaddr $fdtfile;" \
879 "bootm $loadaddr $ramdiskaddr $fdtaddr"
881 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
883 #include <asm/fsl_secure_boot.h>
885 #endif /* __T2080RDB_H */