include/configs/T208xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #define CONFIG_FSL_SATA_V2
  16
  17 /* High Level Configuration Options */
  18 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  19 #define CONFIG_MP               /* support multiple processors */
  20 #define CONFIG_ENABLE_36BIT_PHYS
  21
  22 #ifdef CONFIG_PHYS_64BIT
  23 #define CONFIG_ADDR_MAP 1
  24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  25 #endif
  26
  27 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  28 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  29 #define CONFIG_ENV_OVERWRITE
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  33
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  36 #define CONFIG_SYS_TEXT_BASE            0x00201000
  37 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  38 #define CONFIG_SPL_PAD_TO               0x40000
  39 #define CONFIG_SPL_MAX_SIZE             0x28000
  40 #define RESET_VECTOR_OFFSET             0x27FFC
  41 #define BOOT_PAGE_OFFSET                0x27000
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SPL_SKIP_RELOCATE
  44 #define CONFIG_SPL_COMMON_INIT_DDR
  45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  46 #endif
  47
  48 #ifdef CONFIG_NAND
  49 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  50 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  51 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  52 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  53 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  55 #define CONFIG_SPL_NAND_BOOT
  56 #endif
  57
  58 #ifdef CONFIG_SPIFLASH
  59 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  60 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  65 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  66 #ifndef CONFIG_SPL_BUILD
  67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  68 #endif
  69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  70 #define CONFIG_SPL_SPI_BOOT
  71 #endif
  72
  73 #ifdef CONFIG_SDCARD
  74 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  75 #define CONFIG_SPL_MMC_MINIMAL
  76 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  77 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  78 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  79 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  80 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  81 #ifndef CONFIG_SPL_BUILD
  82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83 #endif
  84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  85 #define CONFIG_SPL_MMC_BOOT
  86 #endif
  87
  88 #endif /* CONFIG_RAMBOOT_PBL */
  89
  90 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  91 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  92 /* Set 1M boot space */
  93 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  94 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  95                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  96 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  97 #endif
  98
  99 #ifndef CONFIG_SYS_TEXT_BASE
 100 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 101 #endif
 102
 103 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 104 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 105 #endif
 106
 107 /*
 108  * These can be toggled for performance analysis, otherwise use default.
 109  */
 110 #define CONFIG_SYS_CACHE_STASHING
 111 #define CONFIG_BTB              /* toggle branch predition */
 112 #define CONFIG_DDR_ECC
 113 #ifdef CONFIG_DDR_ECC
 114 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 115 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 116 #endif
 117
 118 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 119 #define CONFIG_SYS_MEMTEST_END          0x00400000
 120 #define CONFIG_SYS_ALT_MEMTEST
 121
 122 #ifdef CONFIG_MTD_NOR_FLASH
 123 #define CONFIG_FLASH_CFI_DRIVER
 124 #define CONFIG_SYS_FLASH_CFI
 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 126 #endif
 127
 128 #if defined(CONFIG_SPIFLASH)
 129 #define CONFIG_SYS_EXTRA_ENV_RELOC
 130 #define CONFIG_ENV_SPI_BUS      0
 131 #define CONFIG_ENV_SPI_CS       0
 132 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 133 #define CONFIG_ENV_SPI_MODE     0
 134 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 135 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 136 #define CONFIG_ENV_SECT_SIZE    0x10000
 137 #elif defined(CONFIG_SDCARD)
 138 #define CONFIG_SYS_EXTRA_ENV_RELOC
 139 #define CONFIG_SYS_MMC_ENV_DEV  0
 140 #define CONFIG_ENV_SIZE         0x2000
 141 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 142 #elif defined(CONFIG_NAND)
 143 #define CONFIG_SYS_EXTRA_ENV_RELOC
 144 #define CONFIG_ENV_SIZE         0x2000
 145 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 146 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 147 #define CONFIG_ENV_ADDR         0xffe20000
 148 #define CONFIG_ENV_SIZE         0x2000
 149 #elif defined(CONFIG_ENV_IS_NOWHERE)
 150 #define CONFIG_ENV_SIZE         0x2000
 151 #else
 152 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 153 #define CONFIG_ENV_SIZE         0x2000
 154 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 155 #endif
 156
 157 #ifndef __ASSEMBLY__
 158 unsigned long get_board_sys_clk(void);
 159 unsigned long get_board_ddr_clk(void);
 160 #endif
 161
 162 #define CONFIG_SYS_CLK_FREQ     66660000
 163 #define CONFIG_DDR_CLK_FREQ     133330000
 164
 165 /*
 166  * Config the L3 Cache as L3 SRAM
 167  */
 168 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 169 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 170 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 171 #ifdef CONFIG_RAMBOOT_PBL
 172 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 173 #endif
 174 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 175 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 176 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 177 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 178
 179 #define CONFIG_SYS_DCSRBAR      0xf0000000
 180 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 181
 182 /* EEPROM */
 183 #define CONFIG_ID_EEPROM
 184 #define CONFIG_SYS_I2C_EEPROM_NXID
 185 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 186 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 187 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 188
 189 /*
 190  * DDR Setup
 191  */
 192 #define CONFIG_VERY_BIG_RAM
 193 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 194 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 195 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 196 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 197 #define CONFIG_DDR_SPD
 198 #undef CONFIG_FSL_DDR_INTERACTIVE
 199 #define CONFIG_SYS_SPD_BUS_NUM  0
 200 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 201 #define SPD_EEPROM_ADDRESS1     0x51
 202 #define SPD_EEPROM_ADDRESS2     0x52
 203 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 204 #define CTRL_INTLV_PREFERED     cacheline
 205
 206 /*
 207  * IFC Definitions
 208  */
 209 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 210 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 211 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 212 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 213                                 CSPR_PORT_SIZE_16 | \
 214                                 CSPR_MSEL_NOR | \
 215                                 CSPR_V)
 216 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 217
 218 /* NOR Flash Timing Params */
 219 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 220
 221 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 222                                 FTIM0_NOR_TEADC(0x5) | \
 223                                 FTIM0_NOR_TEAHC(0x5))
 224 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 225                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 226                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 227 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 228                                 FTIM2_NOR_TCH(0x4) | \
 229                                 FTIM2_NOR_TWPH(0x0E) | \
 230                                 FTIM2_NOR_TWP(0x1c))
 231 #define CONFIG_SYS_NOR_FTIM3    0x0
 232
 233 #define CONFIG_SYS_FLASH_QUIET_TEST
 234 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 235
 236 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 237 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 238 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 239 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 240 #define CONFIG_SYS_FLASH_EMPTY_INFO
 241 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 242
 243 /* CPLD on IFC */
 244 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 245 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 246 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 247 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 248                                 | CSPR_PORT_SIZE_8 \
 249                                 | CSPR_MSEL_GPCM \
 250                                 | CSPR_V)
 251 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 252 #define CONFIG_SYS_CSOR2        0x0
 253
 254 /* CPLD Timing parameters for IFC CS2 */
 255 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 256                                         FTIM0_GPCM_TEADC(0x0e) | \
 257                                         FTIM0_GPCM_TEAHC(0x0e))
 258 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 259                                         FTIM1_GPCM_TRAD(0x1f))
 260 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 261                                         FTIM2_GPCM_TCH(0x8) | \
 262                                         FTIM2_GPCM_TWP(0x1f))
 263 #define CONFIG_SYS_CS2_FTIM3            0x0
 264
 265 /* NAND Flash on IFC */
 266 #define CONFIG_NAND_FSL_IFC
 267 #define CONFIG_SYS_NAND_BASE            0xff800000
 268 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 269
 270 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 271 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 272                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 273                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 274                                 | CSPR_V)
 275 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 276
 277 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 278                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 279                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 280                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 281                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 282                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 283                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 284
 285 #define CONFIG_SYS_NAND_ONFI_DETECTION
 286
 287 /* ONFI NAND Flash mode0 Timing Params */
 288 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 289                                         FTIM0_NAND_TWP(0x18)    | \
 290                                         FTIM0_NAND_TWCHT(0x07)  | \
 291                                         FTIM0_NAND_TWH(0x0a))
 292 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 293                                         FTIM1_NAND_TWBE(0x39)   | \
 294                                         FTIM1_NAND_TRR(0x0e)    | \
 295                                         FTIM1_NAND_TRP(0x18))
 296 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 297                                         FTIM2_NAND_TREH(0x0a)   | \
 298                                         FTIM2_NAND_TWHRE(0x1e))
 299 #define CONFIG_SYS_NAND_FTIM3           0x0
 300
 301 #define CONFIG_SYS_NAND_DDR_LAW         11
 302 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 303 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 304 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 305
 306 #if defined(CONFIG_NAND)
 307 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 308 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 309 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 310 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 311 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 312 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 313 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 314 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 315 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 316 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 317 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 318 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 319 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 320 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 321 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 322 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 323 #else
 324 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 325 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 326 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 327 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 328 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 329 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 330 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 331 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 332 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 333 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 334 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 335 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 336 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 337 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 338 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 339 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 340 #endif
 341
 342 #if defined(CONFIG_RAMBOOT_PBL)
 343 #define CONFIG_SYS_RAMBOOT
 344 #endif
 345
 346 #ifdef CONFIG_SPL_BUILD
 347 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 348 #else
 349 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 350 #endif
 351
 352 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 353 #define CONFIG_MISC_INIT_R
 354 #define CONFIG_HWCONFIG
 355
 356 /* define to use L1 as initial stack */
 357 #define CONFIG_L1_INIT_RAM
 358 #define CONFIG_SYS_INIT_RAM_LOCK
 359 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 361 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 362 /* The assembler doesn't like typecast */
 363 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 364                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 365                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 366 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 367 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 368                                                 GENERATED_GBL_DATA_SIZE)
 369 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 370 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 371 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 372
 373 /*
 374  * Serial Port
 375  */
 376 #define CONFIG_CONS_INDEX               1
 377 #define CONFIG_SYS_NS16550_SERIAL
 378 #define CONFIG_SYS_NS16550_REG_SIZE     1
 379 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 380 #define CONFIG_SYS_BAUDRATE_TABLE       \
 381         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 382 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 383 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 384 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 385 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 386
 387 /*
 388  * I2C
 389  */
 390 #define CONFIG_SYS_I2C
 391 #define CONFIG_SYS_I2C_FSL
 392 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 393 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 394 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 395 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 396 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 397 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 398 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 399 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 400 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 401 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 402 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 403 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 404 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 405 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 406 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 407 #define I2C_MUX_CH_DEFAULT      0x8
 408
 409 #define I2C_MUX_CH_VOL_MONITOR  0xa
 410
 411 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 412 #ifndef CONFIG_SPL_BUILD
 413 #define CONFIG_VID
 414 #endif
 415 #define CONFIG_VOL_MONITOR_IR36021_SET
 416 #define CONFIG_VOL_MONITOR_IR36021_READ
 417 /* The lowest and highest voltage allowed for T208xRDB */
 418 #define VDD_MV_MIN                      819
 419 #define VDD_MV_MAX                      1212
 420
 421 /*
 422  * RapidIO
 423  */
 424 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 425 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 426 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 427 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 428 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 429 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 430 /*
 431  * for slave u-boot IMAGE instored in master memory space,
 432  * PHYS must be aligned based on the SIZE
 433  */
 434 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 435 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 436 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 437 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 438 /*
 439  * for slave UCODE and ENV instored in master memory space,
 440  * PHYS must be aligned based on the SIZE
 441  */
 442 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 443 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 444 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 445
 446 /* slave core release by master*/
 447 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 448 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 449
 450 /*
 451  * SRIO_PCIE_BOOT - SLAVE
 452  */
 453 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 454 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 455 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 456                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 457 #endif
 458
 459 /*
 460  * eSPI - Enhanced SPI
 461  */
 462 #ifdef CONFIG_SPI_FLASH
 463 #define CONFIG_SPI_FLASH_BAR
 464 #define CONFIG_SF_DEFAULT_SPEED  10000000
 465 #define CONFIG_SF_DEFAULT_MODE    0
 466 #endif
 467
 468 /*
 469  * General PCI
 470  * Memory space is mapped 1-1, but I/O space must start from 0.
 471  */
 472 #define CONFIG_PCIE1            /* PCIE controller 1 */
 473 #define CONFIG_PCIE2            /* PCIE controller 2 */
 474 #define CONFIG_PCIE3            /* PCIE controller 3 */
 475 #define CONFIG_PCIE4            /* PCIE controller 4 */
 476 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 477 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 478 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 479 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 480 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 481 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 482 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 483 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 484 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 485 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 486 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 487
 488 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 489 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 490 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 491 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 492 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 493 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 494 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 495 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 496 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 497
 498 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 499 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 500 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 501 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 502 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 503 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 504 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 505 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 506 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 507
 508 /* controller 4, Base address 203000 */
 509 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 510 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 511 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 512 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 513 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 514 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 515 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 516
 517 #ifdef CONFIG_PCI
 518 #define CONFIG_PCI_INDIRECT_BRIDGE
 519 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 520 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 521 #endif
 522
 523 /* Qman/Bman */
 524 #ifndef CONFIG_NOBQFMAN
 525 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 526 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 527 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 528 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 529 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 530 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 531 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 532 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 533 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 534 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 535                                         CONFIG_SYS_BMAN_CENA_SIZE)
 536 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 537 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 538 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 539 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 540 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 541 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 542 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 543 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 544 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 545 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 546 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 547                                         CONFIG_SYS_QMAN_CENA_SIZE)
 548 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 549 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 550
 551 #define CONFIG_SYS_DPAA_FMAN
 552 #define CONFIG_SYS_DPAA_PME
 553 #define CONFIG_SYS_PMAN
 554 #define CONFIG_SYS_DPAA_DCE
 555 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 556 #define CONFIG_SYS_INTERLAKEN
 557
 558 /* Default address of microcode for the Linux Fman driver */
 559 #if defined(CONFIG_SPIFLASH)
 560 /*
 561  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 562  * env, so we got 0x110000.
 563  */
 564 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 565 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 566 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 567 #define CONFIG_CORTINA_FW_ADDR          0x120000
 568
 569 #elif defined(CONFIG_SDCARD)
 570 /*
 571  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 572  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 573  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 574  */
 575 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 576 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 577 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 578 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 579
 580 #elif defined(CONFIG_NAND)
 581 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 582 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 583 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 584 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 585 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 586 /*
 587  * Slave has no ucode locally, it can fetch this from remote. When implementing
 588  * in two corenet boards, slave's ucode could be stored in master's memory
 589  * space, the address can be mapped from slave TLB->slave LAW->
 590  * slave SRIO or PCIE outbound window->master inbound window->
 591  * master LAW->the ucode address in master's memory space.
 592  */
 593 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 594 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 595 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 596 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 597 #else
 598 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 599 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 600 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 601 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 602 #endif
 603 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 604 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 605 #endif /* CONFIG_NOBQFMAN */
 606
 607 #ifdef CONFIG_SYS_DPAA_FMAN
 608 #define CONFIG_FMAN_ENET
 609 #define CONFIG_PHYLIB_10G
 610 #define CONFIG_PHY_AQUANTIA
 611 #define CONFIG_PHY_CORTINA
 612 #define CONFIG_PHY_REALTEK
 613 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 614 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 615 #define RGMII_PHY2_ADDR         0x02
 616 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 617 #define CORTINA_PHY_ADDR2       0x0d
 618 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 619 #define FM1_10GEC4_PHY_ADDR     0x01
 620 #endif
 621
 622 #ifdef CONFIG_FMAN_ENET
 623 #define CONFIG_MII              /* MII PHY management */
 624 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 625 #endif
 626
 627 /*
 628  * SATA
 629  */
 630 #ifdef CONFIG_FSL_SATA_V2
 631 #define CONFIG_LIBATA
 632 #define CONFIG_FSL_SATA
 633 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 634 #define CONFIG_SATA1
 635 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 636 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 637 #define CONFIG_SATA2
 638 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 639 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 640 #define CONFIG_LBA48
 641 #endif
 642
 643 /*
 644  * USB
 645  */
 646 #ifdef CONFIG_USB_EHCI_HCD
 647 #define CONFIG_USB_EHCI_FSL
 648 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 649 #define CONFIG_HAS_FSL_DR_USB
 650 #endif
 651
 652 /*
 653  * SDHC
 654  */
 655 #ifdef CONFIG_MMC
 656 #define CONFIG_FSL_ESDHC
 657 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 658 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 659 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 660 #endif
 661
 662 /*
 663  * Dynamic MTD Partition support with mtdparts
 664  */
 665 #ifdef CONFIG_MTD_NOR_FLASH
 666 #define CONFIG_MTD_DEVICE
 667 #define CONFIG_MTD_PARTITIONS
 668 #define CONFIG_FLASH_CFI_MTD
 669 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 670                         "spi0=spife110000.1"
 671 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 672                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 673                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
 674                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 675 #endif
 676
 677 /*
 678  * Environment
 679  */
 680
 681 /*
 682  * Miscellaneous configurable options
 683  */
 684 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 685 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 686 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 687 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 688 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 689 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 690 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 691
 692 /*
 693  * For booting Linux, the board info and command line data
 694  * have to be in the first 64 MB of memory, since this is
 695  * the maximum mapped by the Linux kernel during initialization.
 696  */
 697 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 698 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 699
 700 #ifdef CONFIG_CMD_KGDB
 701 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 702 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 703 #endif
 704
 705 /*
 706  * Environment Configuration
 707  */
 708 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 709 #define CONFIG_BOOTFILE  "uImage"
 710 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 711
 712 /* default location for tftp and bootm */
 713 #define CONFIG_LOADADDR         1000000
 714 #define __USB_PHY_TYPE          utmi
 715
 716 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 717         "hwconfig=fsl_ddr:"                                     \
 718         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 719         "bank_intlv=auto;"                                      \
 720         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 721         "netdev=eth0\0"                                         \
 722         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 723         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 724         "tftpflash=tftpboot $loadaddr $uboot && "               \
 725         "protect off $ubootaddr +$filesize && "                 \
 726         "erase $ubootaddr +$filesize && "                       \
 727         "cp.b $loadaddr $ubootaddr $filesize && "               \
 728         "protect on $ubootaddr +$filesize && "                  \
 729         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 730         "consoledev=ttyS0\0"                                    \
 731         "ramdiskaddr=2000000\0"                                 \
 732         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 733         "fdtaddr=1e00000\0"                                     \
 734         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 735         "bdev=sda3\0"
 736
 737 /*
 738  * For emulation this causes u-boot to jump to the start of the
 739  * proof point app code automatically
 740  */
 741 #define CONFIG_PROOF_POINTS                             \
 742         "setenv bootargs root=/dev/$bdev rw "           \
 743         "console=$consoledev,$baudrate $othbootargs;"   \
 744         "cpu 1 release 0x29000000 - - -;"               \
 745         "cpu 2 release 0x29000000 - - -;"               \
 746         "cpu 3 release 0x29000000 - - -;"               \
 747         "cpu 4 release 0x29000000 - - -;"               \
 748         "cpu 5 release 0x29000000 - - -;"               \
 749         "cpu 6 release 0x29000000 - - -;"               \
 750         "cpu 7 release 0x29000000 - - -;"               \
 751         "go 0x29000000"
 752
 753 #define CONFIG_HVBOOT                           \
 754         "setenv bootargs config-addr=0x60000000; "      \
 755         "bootm 0x01000000 - 0x00f00000"
 756
 757 #define CONFIG_ALU                              \
 758         "setenv bootargs root=/dev/$bdev rw "           \
 759         "console=$consoledev,$baudrate $othbootargs;"   \
 760         "cpu 1 release 0x01000000 - - -;"               \
 761         "cpu 2 release 0x01000000 - - -;"               \
 762         "cpu 3 release 0x01000000 - - -;"               \
 763         "cpu 4 release 0x01000000 - - -;"               \
 764         "cpu 5 release 0x01000000 - - -;"               \
 765         "cpu 6 release 0x01000000 - - -;"               \
 766         "cpu 7 release 0x01000000 - - -;"               \
 767         "go 0x01000000"
 768
 769 #define CONFIG_LINUX                            \
 770         "setenv bootargs root=/dev/ram rw "             \
 771         "console=$consoledev,$baudrate $othbootargs;"   \
 772         "setenv ramdiskaddr 0x02000000;"                \
 773         "setenv fdtaddr 0x00c00000;"                    \
 774         "setenv loadaddr 0x1000000;"                    \
 775         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 776
 777 #define CONFIG_HDBOOT                                   \
 778         "setenv bootargs root=/dev/$bdev rw "           \
 779         "console=$consoledev,$baudrate $othbootargs;"   \
 780         "tftp $loadaddr $bootfile;"                     \
 781         "tftp $fdtaddr $fdtfile;"                       \
 782         "bootm $loadaddr - $fdtaddr"
 783
 784 #define CONFIG_NFSBOOTCOMMAND                   \
 785         "setenv bootargs root=/dev/nfs rw "     \
 786         "nfsroot=$serverip:$rootpath "          \
 787         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 788         "console=$consoledev,$baudrate $othbootargs;"   \
 789         "tftp $loadaddr $bootfile;"             \
 790         "tftp $fdtaddr $fdtfile;"               \
 791         "bootm $loadaddr - $fdtaddr"
 792
 793 #define CONFIG_RAMBOOTCOMMAND                           \
 794         "setenv bootargs root=/dev/ram rw "             \
 795         "console=$consoledev,$baudrate $othbootargs;"   \
 796         "tftp $ramdiskaddr $ramdiskfile;"               \
 797         "tftp $loadaddr $bootfile;"                     \
 798         "tftp $fdtaddr $fdtfile;"                       \
 799         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 800
 801 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 802
 803 #include <asm/fsl_secure_boot.h>
 804
 805 #endif  /* __T2080RDB_H */