include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #if defined(CONFIG_ARCH_T2080)
  16 #define CONFIG_FSL_SATA_V2
  17 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  18 #define CONFIG_SRIO1            /* SRIO port 1 */
  19 #define CONFIG_SRIO2            /* SRIO port 2 */
  20 #elif defined(CONFIG_ARCH_T2081)
  21 #endif
  22
  23 /* High Level Configuration Options */
  24 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  25 #define CONFIG_ENABLE_36BIT_PHYS
  26
  27 #ifdef CONFIG_PHYS_64BIT
  28 #define CONFIG_ADDR_MAP 1
  29 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  30 #endif
  31
  32 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  33 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  34 #define CONFIG_ENV_OVERWRITE
  35
  36 #ifdef CONFIG_RAMBOOT_PBL
  37 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  38
  39 #define CONFIG_SPL_FLUSH_IMAGE
  40 #define CONFIG_SPL_PAD_TO               0x40000
  41 #define CONFIG_SPL_MAX_SIZE             0x28000
  42 #define RESET_VECTOR_OFFSET             0x27FFC
  43 #define BOOT_PAGE_OFFSET                0x27000
  44 #ifdef CONFIG_SPL_BUILD
  45 #define CONFIG_SPL_SKIP_RELOCATE
  46 #define CONFIG_SPL_COMMON_INIT_DDR
  47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  48 #endif
  49
  50 #ifdef CONFIG_MTD_RAW_NAND
  51 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  52 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  53 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  54 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  55 #if defined(CONFIG_ARCH_T2080)
  56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  57 #elif defined(CONFIG_ARCH_T2081)
  58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
  59 #endif
  60 #endif
  61
  62 #ifdef CONFIG_SPIFLASH
  63 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  64 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  69 #ifndef CONFIG_SPL_BUILD
  70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  71 #endif
  72 #if defined(CONFIG_ARCH_T2080)
  73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  74 #elif defined(CONFIG_ARCH_T2081)
  75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
  76 #endif
  77 #endif
  78
  79 #ifdef CONFIG_SDCARD
  80 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  81 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  82 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  83 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  84 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  85 #ifndef CONFIG_SPL_BUILD
  86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  87 #endif
  88 #if defined(CONFIG_ARCH_T2080)
  89 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  90 #elif defined(CONFIG_ARCH_T2081)
  91 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
  92 #endif
  93 #endif
  94
  95 #endif /* CONFIG_RAMBOOT_PBL */
  96
  97 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  98 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  99 /* Set 1M boot space */
 100 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 101 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 102                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 103 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 104 #endif
 105
 106 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 107 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 108 #endif
 109
 110 /*
 111  * These can be toggled for performance analysis, otherwise use default.
 112  */
 113 #define CONFIG_SYS_CACHE_STASHING
 114 #define CONFIG_BTB              /* toggle branch predition */
 115 #define CONFIG_DDR_ECC
 116 #ifdef CONFIG_DDR_ECC
 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 118 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 119 #endif
 120
 121 #if defined(CONFIG_SPIFLASH)
 122 #elif defined(CONFIG_SDCARD)
 123 #define CONFIG_SYS_MMC_ENV_DEV  0
 124 #endif
 125
 126 #ifndef __ASSEMBLY__
 127 unsigned long get_board_sys_clk(void);
 128 unsigned long get_board_ddr_clk(void);
 129 #endif
 130
 131 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 132 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 133
 134 /*
 135  * Config the L3 Cache as L3 SRAM
 136  */
 137 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 138 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 139 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 140 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 141 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 142 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 143 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 144
 145 #define CONFIG_SYS_DCSRBAR      0xf0000000
 146 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 147
 148 /* EEPROM */
 149 #define CONFIG_ID_EEPROM
 150 #define CONFIG_SYS_I2C_EEPROM_NXID
 151 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 154
 155 /*
 156  * DDR Setup
 157  */
 158 #define CONFIG_VERY_BIG_RAM
 159 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 160 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 161 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 162 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 163 #define CONFIG_DDR_SPD
 164 #define CONFIG_SYS_SPD_BUS_NUM  0
 165 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 166 #define SPD_EEPROM_ADDRESS1     0x51
 167 #define SPD_EEPROM_ADDRESS2     0x52
 168 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 169 #define CTRL_INTLV_PREFERED     cacheline
 170
 171 /*
 172  * IFC Definitions
 173  */
 174 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 175 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 176 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 177 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 178                                 + 0x8000000) | \
 179                                 CSPR_PORT_SIZE_16 | \
 180                                 CSPR_MSEL_NOR | \
 181                                 CSPR_V)
 182 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 183 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 184                                 CSPR_PORT_SIZE_16 | \
 185                                 CSPR_MSEL_NOR | \
 186                                 CSPR_V)
 187 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 188 /* NOR Flash Timing Params */
 189 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 190
 191 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 192                                 FTIM0_NOR_TEADC(0x5) | \
 193                                 FTIM0_NOR_TEAHC(0x5))
 194 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 195                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 196                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 197 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 198                                 FTIM2_NOR_TCH(0x4) | \
 199                                 FTIM2_NOR_TWPH(0x0E) | \
 200                                 FTIM2_NOR_TWP(0x1c))
 201 #define CONFIG_SYS_NOR_FTIM3    0x0
 202
 203 #define CONFIG_SYS_FLASH_QUIET_TEST
 204 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 205
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 207 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 208 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 209 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 210
 211 #define CONFIG_SYS_FLASH_EMPTY_INFO
 212 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 213                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 214
 215 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 216 #define QIXIS_BASE                      0xffdf0000
 217 #define QIXIS_LBMAP_SWITCH              6
 218 #define QIXIS_LBMAP_MASK                0x0f
 219 #define QIXIS_LBMAP_SHIFT               0
 220 #define QIXIS_LBMAP_DFLTBANK            0x00
 221 #define QIXIS_LBMAP_ALTBANK             0x04
 222 #define QIXIS_LBMAP_NAND                0x09
 223 #define QIXIS_LBMAP_SD                  0x00
 224 #define QIXIS_RCW_SRC_NAND              0x104
 225 #define QIXIS_RCW_SRC_SD                0x040
 226 #define QIXIS_RST_CTL_RESET             0x83
 227 #define QIXIS_RST_FORCE_MEM             0x1
 228 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 229 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 230 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 231 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 232
 233 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 234 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 235                                 | CSPR_PORT_SIZE_8 \
 236                                 | CSPR_MSEL_GPCM \
 237                                 | CSPR_V)
 238 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 239 #define CONFIG_SYS_CSOR3        0x0
 240 /* QIXIS Timing parameters for IFC CS3 */
 241 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 242                                         FTIM0_GPCM_TEADC(0x0e) | \
 243                                         FTIM0_GPCM_TEAHC(0x0e))
 244 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 245                                         FTIM1_GPCM_TRAD(0x3f))
 246 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 247                                         FTIM2_GPCM_TCH(0x8) | \
 248                                         FTIM2_GPCM_TWP(0x1f))
 249 #define CONFIG_SYS_CS3_FTIM3            0x0
 250
 251 /* NAND Flash on IFC */
 252 #define CONFIG_NAND_FSL_IFC
 253 #define CONFIG_SYS_NAND_BASE            0xff800000
 254 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 255
 256 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 257 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 258                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 259                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 260                                 | CSPR_V)
 261 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 262
 263 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 264                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 265                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 266                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 267                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 268                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 269                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 270
 271 #define CONFIG_SYS_NAND_ONFI_DETECTION
 272
 273 /* ONFI NAND Flash mode0 Timing Params */
 274 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 275                                         FTIM0_NAND_TWP(0x18)    | \
 276                                         FTIM0_NAND_TWCHT(0x07)  | \
 277                                         FTIM0_NAND_TWH(0x0a))
 278 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 279                                         FTIM1_NAND_TWBE(0x39)   | \
 280                                         FTIM1_NAND_TRR(0x0e)    | \
 281                                         FTIM1_NAND_TRP(0x18))
 282 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 283                                         FTIM2_NAND_TREH(0x0a)   | \
 284                                         FTIM2_NAND_TWHRE(0x1e))
 285 #define CONFIG_SYS_NAND_FTIM3           0x0
 286
 287 #define CONFIG_SYS_NAND_DDR_LAW         11
 288 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 289 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 290 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 291
 292 #if defined(CONFIG_MTD_RAW_NAND)
 293 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 294 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 295 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 296 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 297 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 298 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 299 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 300 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 301 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 302 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 303 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 304 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 305 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 306 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 307 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 308 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 309 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 310 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 311 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 312 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 313 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 314 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 315 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 316 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 317 #else
 318 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 319 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 320 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 321 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 322 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 323 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 324 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 325 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 326 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 327 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 328 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 329 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 330 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 331 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 332 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 333 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 334 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 335 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 336 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 337 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 338 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 339 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 340 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 341 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 342 #endif
 343
 344 #if defined(CONFIG_RAMBOOT_PBL)
 345 #define CONFIG_SYS_RAMBOOT
 346 #endif
 347
 348 #ifdef CONFIG_SPL_BUILD
 349 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 350 #else
 351 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 352 #endif
 353
 354 #define CONFIG_HWCONFIG
 355
 356 /* define to use L1 as initial stack */
 357 #define CONFIG_L1_INIT_RAM
 358 #define CONFIG_SYS_INIT_RAM_LOCK
 359 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 361 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 362 /* The assembler doesn't like typecast */
 363 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 364                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 365                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 366 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 367 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 368                                                 GENERATED_GBL_DATA_SIZE)
 369 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 370 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 371 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 372
 373 /*
 374  * Serial Port
 375  */
 376 #define CONFIG_SYS_NS16550_SERIAL
 377 #define CONFIG_SYS_NS16550_REG_SIZE     1
 378 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 379 #define CONFIG_SYS_BAUDRATE_TABLE       \
 380         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 381 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 382 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 383 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 384 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 385
 386 /*
 387  * I2C
 388  */
 389 #ifndef CONFIG_DM_I2C
 390 #define CONFIG_SYS_I2C
 391 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 392 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 393 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 394 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 395 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 396 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 397 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 398 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 399 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 400 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 401 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 402 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 403 #endif
 404
 405 #define CONFIG_SYS_I2C_FSL
 406
 407 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 408 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 409 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 410 #define I2C_MUX_CH_DEFAULT      0x8
 411
 412 #define I2C_MUX_CH_VOL_MONITOR 0xa
 413
 414 /* Voltage monitor on channel 2*/
 415 #define I2C_VOL_MONITOR_ADDR           0x40
 416 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 417 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 418 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 419
 420 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
 421 #ifndef CONFIG_SPL_BUILD
 422 #define CONFIG_VID
 423 #endif
 424 #define CONFIG_VOL_MONITOR_IR36021_SET
 425 #define CONFIG_VOL_MONITOR_IR36021_READ
 426 /* The lowest and highest voltage allowed for T208xQDS */
 427 #define VDD_MV_MIN                      819
 428 #define VDD_MV_MAX                      1212
 429
 430 /*
 431  * RapidIO
 432  */
 433 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 434 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 435 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 436 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 437 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 438 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 439 /*
 440  * for slave u-boot IMAGE instored in master memory space,
 441  * PHYS must be aligned based on the SIZE
 442  */
 443 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 444 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 445 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 446 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 447 /*
 448  * for slave UCODE and ENV instored in master memory space,
 449  * PHYS must be aligned based on the SIZE
 450  */
 451 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 452 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 453 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 454
 455 /* slave core release by master*/
 456 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 457 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 458
 459 /*
 460  * SRIO_PCIE_BOOT - SLAVE
 461  */
 462 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 463 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 464 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 465                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 466 #endif
 467
 468 /*
 469  * eSPI - Enhanced SPI
 470  */
 471
 472 /*
 473  * General PCI
 474  * Memory space is mapped 1-1, but I/O space must start from 0.
 475  */
 476 #define CONFIG_PCIE1            /* PCIE controller 1 */
 477 #define CONFIG_PCIE2            /* PCIE controller 2 */
 478 #define CONFIG_PCIE3            /* PCIE controller 3 */
 479 #define CONFIG_PCIE4            /* PCIE controller 4 */
 480 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 481 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 482 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 483 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 484 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 485 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 486
 487 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 488 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 489 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 490 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 491 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 492
 493 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 494 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 495 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 496 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 497 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 498
 499 /* controller 4, Base address 203000 */
 500 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 501 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 502 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 503
 504 #ifdef CONFIG_PCI
 505 #if !defined(CONFIG_DM_PCI)
 506 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 507 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 508 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 509 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 510 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 511 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 512 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 513 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 514 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 515 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 516 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 517 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 518 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 519 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 520 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 521 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 522 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 523 #define CONFIG_PCI_INDIRECT_BRIDGE
 524 #endif
 525 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 526 #endif
 527
 528 /* Qman/Bman */
 529 #ifndef CONFIG_NOBQFMAN
 530 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 531 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 532 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 533 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 534 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 535 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 536 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 537 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 538 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 539                                         CONFIG_SYS_BMAN_CENA_SIZE)
 540 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 541 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 542 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 543 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 544 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 545 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 546 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 547 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 548 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 549 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 550 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 551                                         CONFIG_SYS_QMAN_CENA_SIZE)
 552 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 553 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 554
 555 #define CONFIG_SYS_DPAA_FMAN
 556 #define CONFIG_SYS_DPAA_PME
 557 #define CONFIG_SYS_PMAN
 558 #define CONFIG_SYS_DPAA_DCE
 559 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 560 #define CONFIG_SYS_INTERLAKEN
 561
 562 /* Default address of microcode for the Linux Fman driver */
 563 #if defined(CONFIG_SPIFLASH)
 564 /*
 565  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 566  * env, so we got 0x110000.
 567  */
 568 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 569 #elif defined(CONFIG_SDCARD)
 570 /*
 571  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 572  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 573  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 574  */
 575 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 576 #elif defined(CONFIG_MTD_RAW_NAND)
 577 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 578 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 579 /*
 580  * Slave has no ucode locally, it can fetch this from remote. When implementing
 581  * in two corenet boards, slave's ucode could be stored in master's memory
 582  * space, the address can be mapped from slave TLB->slave LAW->
 583  * slave SRIO or PCIE outbound window->master inbound window->
 584  * master LAW->the ucode address in master's memory space.
 585  */
 586 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 587 #else
 588 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 589 #endif
 590 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 591 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 592 #endif /* CONFIG_NOBQFMAN */
 593
 594 #ifdef CONFIG_SYS_DPAA_FMAN
 595 #define RGMII_PHY1_ADDR 0x1
 596 #define RGMII_PHY2_ADDR 0x2
 597 #define FM1_10GEC1_PHY_ADDR       0x3
 598 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 599 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 600 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 601 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 602 #endif
 603
 604 #ifdef CONFIG_FMAN_ENET
 605 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 606 #endif
 607
 608 /*
 609  * SATA
 610  */
 611 #ifdef CONFIG_FSL_SATA_V2
 612 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 613 #define CONFIG_SATA1
 614 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 615 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 616 #define CONFIG_SATA2
 617 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 618 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 619 #define CONFIG_LBA48
 620 #endif
 621
 622 /*
 623  * USB
 624  */
 625 #ifdef CONFIG_USB_EHCI_HCD
 626 #define CONFIG_USB_EHCI_FSL
 627 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 628 #define CONFIG_HAS_FSL_DR_USB
 629 #endif
 630
 631 /*
 632  * SDHC
 633  */
 634 #ifdef CONFIG_MMC
 635 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 636 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 637 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 638 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 639 #endif
 640
 641 /*
 642  * Dynamic MTD Partition support with mtdparts
 643  */
 644
 645 /*
 646  * Environment
 647  */
 648 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 649 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 650
 651 /*
 652  * Miscellaneous configurable options
 653  */
 654 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 655
 656 /*
 657  * For booting Linux, the board info and command line data
 658  * have to be in the first 64 MB of memory, since this is
 659  * the maximum mapped by the Linux kernel during initialization.
 660  */
 661 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 662 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 663
 664 #ifdef CONFIG_CMD_KGDB
 665 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 666 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 667 #endif
 668
 669 /*
 670  * Environment Configuration
 671  */
 672 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 673 #define CONFIG_BOOTFILE  "uImage"
 674 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 675
 676 /* default location for tftp and bootm */
 677 #define CONFIG_LOADADDR         1000000
 678 #define __USB_PHY_TYPE          utmi
 679
 680 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 681         "hwconfig=fsl_ddr:"                                     \
 682         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 683         "bank_intlv=auto;"                                      \
 684         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 685         "netdev=eth0\0"                                         \
 686         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 687         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 688         "tftpflash=tftpboot $loadaddr $uboot && "               \
 689         "protect off $ubootaddr +$filesize && "                 \
 690         "erase $ubootaddr +$filesize && "                       \
 691         "cp.b $loadaddr $ubootaddr $filesize && "               \
 692         "protect on $ubootaddr +$filesize && "                  \
 693         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 694         "consoledev=ttyS0\0"                                    \
 695         "ramdiskaddr=2000000\0"                                 \
 696         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 697         "fdtaddr=1e00000\0"                                     \
 698         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 699         "bdev=sda3\0"
 700
 701 /*
 702  * For emulation this causes u-boot to jump to the start of the
 703  * proof point app code automatically
 704  */
 705 #define CONFIG_PROOF_POINTS                             \
 706         "setenv bootargs root=/dev/$bdev rw "           \
 707         "console=$consoledev,$baudrate $othbootargs;"   \
 708         "cpu 1 release 0x29000000 - - -;"               \
 709         "cpu 2 release 0x29000000 - - -;"               \
 710         "cpu 3 release 0x29000000 - - -;"               \
 711         "cpu 4 release 0x29000000 - - -;"               \
 712         "cpu 5 release 0x29000000 - - -;"               \
 713         "cpu 6 release 0x29000000 - - -;"               \
 714         "cpu 7 release 0x29000000 - - -;"               \
 715         "go 0x29000000"
 716
 717 #define CONFIG_HVBOOT                           \
 718         "setenv bootargs config-addr=0x60000000; "      \
 719         "bootm 0x01000000 - 0x00f00000"
 720
 721 #define CONFIG_ALU                              \
 722         "setenv bootargs root=/dev/$bdev rw "           \
 723         "console=$consoledev,$baudrate $othbootargs;"   \
 724         "cpu 1 release 0x01000000 - - -;"               \
 725         "cpu 2 release 0x01000000 - - -;"               \
 726         "cpu 3 release 0x01000000 - - -;"               \
 727         "cpu 4 release 0x01000000 - - -;"               \
 728         "cpu 5 release 0x01000000 - - -;"               \
 729         "cpu 6 release 0x01000000 - - -;"               \
 730         "cpu 7 release 0x01000000 - - -;"               \
 731         "go 0x01000000"
 732
 733 #define CONFIG_LINUX                            \
 734         "setenv bootargs root=/dev/ram rw "             \
 735         "console=$consoledev,$baudrate $othbootargs;"   \
 736         "setenv ramdiskaddr 0x02000000;"                \
 737         "setenv fdtaddr 0x00c00000;"                    \
 738         "setenv loadaddr 0x1000000;"                    \
 739         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 740
 741 #define CONFIG_HDBOOT                                   \
 742         "setenv bootargs root=/dev/$bdev rw "           \
 743         "console=$consoledev,$baudrate $othbootargs;"   \
 744         "tftp $loadaddr $bootfile;"                     \
 745         "tftp $fdtaddr $fdtfile;"                       \
 746         "bootm $loadaddr - $fdtaddr"
 747
 748 #define CONFIG_NFSBOOTCOMMAND                   \
 749         "setenv bootargs root=/dev/nfs rw "     \
 750         "nfsroot=$serverip:$rootpath "          \
 751         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 752         "console=$consoledev,$baudrate $othbootargs;"   \
 753         "tftp $loadaddr $bootfile;"             \
 754         "tftp $fdtaddr $fdtfile;"               \
 755         "bootm $loadaddr - $fdtaddr"
 756
 757 #define CONFIG_RAMBOOTCOMMAND                           \
 758         "setenv bootargs root=/dev/ram rw "             \
 759         "console=$consoledev,$baudrate $othbootargs;"   \
 760         "tftp $ramdiskaddr $ramdiskfile;"               \
 761         "tftp $loadaddr $bootfile;"                     \
 762         "tftp $fdtaddr $fdtfile;"                       \
 763         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 764
 765 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 766
 767 #include <asm/fsl_secure_boot.h>
 768
 769 #endif  /* __T208xQDS_H */