2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #define CONFIG_T104xRDB
14 #define CONFIG_PHYS_64BIT
16 #ifdef CONFIG_RAMBOOT_PBL
17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
18 #ifdef CONFIG_T1040RDB
19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
21 #ifdef CONFIG_T1042RDB_PI
22 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
24 #ifdef CONFIG_T1042RDB
25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
29 #define CONFIG_SPL_ENV_SUPPORT
30 #define CONFIG_SPL_SERIAL_SUPPORT
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
33 #define CONFIG_SPL_LIBGENERIC_SUPPORT
34 #define CONFIG_SPL_LIBCOMMON_SUPPORT
35 #define CONFIG_SPL_I2C_SUPPORT
36 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
37 #define CONFIG_FSL_LAW /* Use common FSL init code */
38 #define CONFIG_SYS_TEXT_BASE 0x30001000
39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40 #define CONFIG_SPL_PAD_TO 0x40000
41 #define CONFIG_SPL_MAX_SIZE 0x28000
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SPL_SKIP_RELOCATE
44 #define CONFIG_SPL_COMMON_INIT_DDR
45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
46 #define CONFIG_SYS_NO_FLASH
48 #define RESET_VECTOR_OFFSET 0x27FFC
49 #define BOOT_PAGE_OFFSET 0x27000
52 #define CONFIG_SPL_NAND_SUPPORT
53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
54 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
55 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
56 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
58 #define CONFIG_SPL_NAND_BOOT
61 #ifdef CONFIG_SPIFLASH
62 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
63 #define CONFIG_SPL_SPI_SUPPORT
64 #define CONFIG_SPL_SPI_FLASH_SUPPORT
65 #define CONFIG_SPL_SPI_FLASH_MINIMAL
66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
71 #ifndef CONFIG_SPL_BUILD
72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
74 #define CONFIG_SPL_SPI_BOOT
78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
79 #define CONFIG_SPL_MMC_SUPPORT
80 #define CONFIG_SPL_MMC_MINIMAL
81 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
82 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
83 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
84 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
86 #ifndef CONFIG_SPL_BUILD
87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
89 #define CONFIG_SPL_MMC_BOOT
94 /* High Level Configuration Options */
96 #define CONFIG_E500 /* BOOKE e500 family */
97 #define CONFIG_E500MC /* BOOKE e500mc family */
98 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
99 #define CONFIG_MP /* support multiple processors */
101 /* support deep sleep */
102 #define CONFIG_DEEP_SLEEP
103 #define CONFIG_SILENT_CONSOLE
105 #ifndef CONFIG_SYS_TEXT_BASE
106 #define CONFIG_SYS_TEXT_BASE 0xeff40000
109 #ifndef CONFIG_RESET_VECTOR_ADDRESS
110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
113 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
114 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
115 #define CONFIG_FSL_IFC /* Enable IFC Support */
116 #define CONFIG_PCI /* Enable PCI/PCIE */
117 #define CONFIG_PCI_INDIRECT_BRIDGE
118 #define CONFIG_PCIE1 /* PCIE controler 1 */
119 #define CONFIG_PCIE2 /* PCIE controler 2 */
120 #define CONFIG_PCIE3 /* PCIE controler 3 */
121 #define CONFIG_PCIE4 /* PCIE controler 4 */
123 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
124 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
126 #define CONFIG_FSL_LAW /* Use common FSL init code */
128 #define CONFIG_ENV_OVERWRITE
130 #ifndef CONFIG_SYS_NO_FLASH
131 #define CONFIG_FLASH_CFI_DRIVER
132 #define CONFIG_SYS_FLASH_CFI
133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
136 #if defined(CONFIG_SPIFLASH)
137 #define CONFIG_SYS_EXTRA_ENV_RELOC
138 #define CONFIG_ENV_IS_IN_SPI_FLASH
139 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
140 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
141 #define CONFIG_ENV_SECT_SIZE 0x10000
142 #elif defined(CONFIG_SDCARD)
143 #define CONFIG_SYS_EXTRA_ENV_RELOC
144 #define CONFIG_ENV_IS_IN_MMC
145 #define CONFIG_SYS_MMC_ENV_DEV 0
146 #define CONFIG_ENV_SIZE 0x2000
147 #define CONFIG_ENV_OFFSET (512 * 0x800)
148 #elif defined(CONFIG_NAND)
149 #define CONFIG_SYS_EXTRA_ENV_RELOC
150 #define CONFIG_ENV_IS_IN_NAND
151 #define CONFIG_ENV_SIZE 0x2000
152 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
154 #define CONFIG_ENV_IS_IN_FLASH
155 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
156 #define CONFIG_ENV_SIZE 0x2000
157 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
160 #define CONFIG_SYS_CLK_FREQ 100000000
161 #define CONFIG_DDR_CLK_FREQ 66666666
164 * These can be toggled for performance analysis, otherwise use default.
166 #define CONFIG_SYS_CACHE_STASHING
167 #define CONFIG_BACKSIDE_L2_CACHE
168 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
169 #define CONFIG_BTB /* toggle branch predition */
170 #define CONFIG_DDR_ECC
171 #ifdef CONFIG_DDR_ECC
172 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
173 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
176 #define CONFIG_ENABLE_36BIT_PHYS
178 #define CONFIG_ADDR_MAP
179 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
181 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
182 #define CONFIG_SYS_MEMTEST_END 0x00400000
183 #define CONFIG_SYS_ALT_MEMTEST
184 #define CONFIG_PANIC_HANG /* do not reset board on panic */
187 * Config the L3 Cache as L3 SRAM
189 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
190 #define CONFIG_SYS_L3_SIZE 256 << 10
191 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
192 #ifdef CONFIG_RAMBOOT_PBL
193 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
195 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
196 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
197 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
198 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
200 #define CONFIG_SYS_DCSRBAR 0xf0000000
201 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
206 #define CONFIG_VERY_BIG_RAM
207 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
208 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
210 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
211 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
212 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
214 #define CONFIG_DDR_SPD
215 #define CONFIG_SYS_DDR_RAW_TIMING
216 #define CONFIG_SYS_FSL_DDR3
218 #define CONFIG_SYS_SPD_BUS_NUM 0
219 #define SPD_EEPROM_ADDRESS 0x51
221 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
226 #define CONFIG_SYS_FLASH_BASE 0xe8000000
227 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
229 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
230 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
231 CSPR_PORT_SIZE_16 | \
234 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
239 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
241 /* NOR Flash Timing Params */
242 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
243 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
244 FTIM0_NOR_TEADC(0x5) | \
245 FTIM0_NOR_TEAHC(0x5))
246 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
247 FTIM1_NOR_TRAD_NOR(0x1A) |\
248 FTIM1_NOR_TSEQRAD_NOR(0x13))
249 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
250 FTIM2_NOR_TCH(0x4) | \
251 FTIM2_NOR_TWPH(0x0E) | \
253 #define CONFIG_SYS_NOR_FTIM3 0x0
255 #define CONFIG_SYS_FLASH_QUIET_TEST
256 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
258 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
259 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
260 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
261 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
263 #define CONFIG_SYS_FLASH_EMPTY_INFO
264 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
267 #define CPLD_LBMAP_MASK 0x3F
268 #define CPLD_BANK_SEL_MASK 0x07
269 #define CPLD_BANK_OVERRIDE 0x40
270 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
271 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
272 #define CPLD_LBMAP_RESET 0xFF
273 #define CPLD_LBMAP_SHIFT 0x03
274 #ifdef CONFIG_T1042RDB_PI
275 #define CPLD_DIU_SEL_DFP 0x80
278 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
279 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
280 #define CONFIG_SYS_CSPR2_EXT (0xf)
281 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
285 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
286 #define CONFIG_SYS_CSOR2 0x0
287 /* CPLD Timing parameters for IFC CS2 */
288 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
289 FTIM0_GPCM_TEADC(0x0e) | \
290 FTIM0_GPCM_TEAHC(0x0e))
291 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
292 FTIM1_GPCM_TRAD(0x1f))
293 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
294 FTIM2_GPCM_TCH(0x8) | \
295 FTIM2_GPCM_TWP(0x1f))
296 #define CONFIG_SYS_CS2_FTIM3 0x0
298 /* NAND Flash on IFC */
299 #define CONFIG_NAND_FSL_IFC
300 #define CONFIG_SYS_NAND_BASE 0xff800000
301 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
303 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
304 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
305 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
306 | CSPR_MSEL_NAND /* MSEL = NAND */ \
308 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
310 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
311 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
312 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
313 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
314 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
315 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
316 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
318 #define CONFIG_SYS_NAND_ONFI_DETECTION
320 /* ONFI NAND Flash mode0 Timing Params */
321 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
322 FTIM0_NAND_TWP(0x18) | \
323 FTIM0_NAND_TWCHT(0x07) | \
324 FTIM0_NAND_TWH(0x0a))
325 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
326 FTIM1_NAND_TWBE(0x39) | \
327 FTIM1_NAND_TRR(0x0e) | \
328 FTIM1_NAND_TRP(0x18))
329 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
330 FTIM2_NAND_TREH(0x0a) | \
331 FTIM2_NAND_TWHRE(0x1e))
332 #define CONFIG_SYS_NAND_FTIM3 0x0
334 #define CONFIG_SYS_NAND_DDR_LAW 11
335 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
336 #define CONFIG_SYS_MAX_NAND_DEVICE 1
337 #define CONFIG_MTD_NAND_VERIFY_WRITE
338 #define CONFIG_CMD_NAND
340 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
342 #if defined(CONFIG_NAND)
343 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
344 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
345 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
346 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
347 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
348 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
349 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
350 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
351 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
352 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
353 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
354 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
355 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
356 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
357 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
358 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
360 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
361 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
362 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
363 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
364 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
365 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
366 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
367 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
368 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
369 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
370 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
371 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
372 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
373 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
374 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
375 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
378 #ifdef CONFIG_SPL_BUILD
379 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
381 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
384 #if defined(CONFIG_RAMBOOT_PBL)
385 #define CONFIG_SYS_RAMBOOT
388 #define CONFIG_BOARD_EARLY_INIT_R
389 #define CONFIG_MISC_INIT_R
391 #define CONFIG_HWCONFIG
393 /* define to use L1 as initial stack */
394 #define CONFIG_L1_INIT_RAM
395 #define CONFIG_SYS_INIT_RAM_LOCK
396 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
399 /* The assembler doesn't like typecast */
400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
401 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
402 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
403 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
405 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
406 GENERATED_GBL_DATA_SIZE)
407 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
409 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
410 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
412 /* Serial Port - controlled on board with jumper J8
416 #define CONFIG_CONS_INDEX 1
417 #define CONFIG_SYS_NS16550
418 #define CONFIG_SYS_NS16550_SERIAL
419 #define CONFIG_SYS_NS16550_REG_SIZE 1
420 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
422 #define CONFIG_SYS_BAUDRATE_TABLE \
423 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
425 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
426 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
427 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
428 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
429 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
430 #ifndef CONFIG_SPL_BUILD
431 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
434 /* Use the HUSH parser */
435 #define CONFIG_SYS_HUSH_PARSER
436 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
438 #ifdef CONFIG_T1042RDB_PI
440 #define CONFIG_FSL_DIU_FB
442 #ifdef CONFIG_FSL_DIU_FB
443 #define CONFIG_FSL_DIU_CH7301
444 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
446 #define CONFIG_CMD_BMP
447 #define CONFIG_CFB_CONSOLE
448 #define CONFIG_CFB_CONSOLE_ANSI
449 #define CONFIG_VIDEO_SW_CURSOR
450 #define CONFIG_VGA_AS_SINGLE_DEVICE
451 #define CONFIG_VIDEO_LOGO
452 #define CONFIG_VIDEO_BMP_LOGO
456 /* pass open firmware flat tree */
457 #define CONFIG_OF_LIBFDT
458 #define CONFIG_OF_BOARD_SETUP
459 #define CONFIG_OF_STDOUT_VIA_ALIAS
461 /* new uImage format support */
463 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
466 #define CONFIG_SYS_I2C
467 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
468 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
469 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
470 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
471 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
472 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
473 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
474 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
475 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
476 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
477 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
478 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
479 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
481 /* I2C bus multiplexer */
482 #define I2C_MUX_PCA_ADDR 0x70
483 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
484 #define I2C_MUX_CH_DEFAULT 0x8
487 #ifdef CONFIG_T1042RDB_PI
488 /* LDI/DVI Encoder for display */
489 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
490 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
496 #define CONFIG_RTC_DS1337 1
497 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
500 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
504 * eSPI - Enhanced SPI
506 #define CONFIG_FSL_ESPI
507 #define CONFIG_SPI_FLASH
508 #define CONFIG_SPI_FLASH_STMICRO
509 #define CONFIG_SPI_FLASH_BAR
510 #define CONFIG_CMD_SF
511 #define CONFIG_SF_DEFAULT_SPEED 10000000
512 #define CONFIG_SF_DEFAULT_MODE 0
513 #define CONFIG_ENV_SPI_BUS 0
514 #define CONFIG_ENV_SPI_CS 0
515 #define CONFIG_ENV_SPI_MAX_HZ 10000000
516 #define CONFIG_ENV_SPI_MODE 0
520 * Memory space is mapped 1-1, but I/O space must start from 0.
524 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
526 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
527 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
528 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
529 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
530 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
531 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
532 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
533 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
536 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
538 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
539 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
540 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
541 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
542 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
543 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
544 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
545 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
548 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
550 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
551 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
552 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
553 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
554 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
555 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
556 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
557 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
560 /* controller 4, Base address 203000 */
562 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
563 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
564 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
565 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
566 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
567 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
568 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
569 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
572 #define CONFIG_PCI_PNP /* do pci plug-and-play */
575 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
576 #define CONFIG_DOS_PARTITION
577 #endif /* CONFIG_PCI */
580 #define CONFIG_FSL_SATA_V2
581 #ifdef CONFIG_FSL_SATA_V2
582 #define CONFIG_LIBATA
583 #define CONFIG_FSL_SATA
585 #define CONFIG_SYS_SATA_MAX_DEVICE 1
587 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
588 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
591 #define CONFIG_CMD_SATA
592 #define CONFIG_DOS_PARTITION
593 #define CONFIG_CMD_EXT2
599 #define CONFIG_HAS_FSL_DR_USB
601 #ifdef CONFIG_HAS_FSL_DR_USB
602 #define CONFIG_USB_EHCI
604 #ifdef CONFIG_USB_EHCI
605 #define CONFIG_CMD_USB
606 #define CONFIG_USB_STORAGE
607 #define CONFIG_USB_EHCI_FSL
608 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
609 #define CONFIG_CMD_EXT2
616 #define CONFIG_FSL_ESDHC
617 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
618 #define CONFIG_CMD_MMC
619 #define CONFIG_GENERIC_MMC
620 #define CONFIG_CMD_EXT2
621 #define CONFIG_CMD_FAT
622 #define CONFIG_DOS_PARTITION
626 #ifndef CONFIG_NOBQFMAN
627 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
628 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
629 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
630 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
631 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
632 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
633 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
634 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
635 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
637 #define CONFIG_SYS_DPAA_FMAN
638 #define CONFIG_SYS_DPAA_PME
640 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
645 /* Default address of microcode for the Linux Fman driver */
646 #if defined(CONFIG_SPIFLASH)
648 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
649 * env, so we got 0x110000.
651 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
652 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
653 #elif defined(CONFIG_SDCARD)
655 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
656 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
657 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
659 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
660 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
661 #elif defined(CONFIG_NAND)
662 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
663 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
665 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
666 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
669 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
670 #if defined(CONFIG_SPIFLASH)
671 #define CONFIG_SYS_QE_FW_ADDR 0x130000
672 #elif defined(CONFIG_SDCARD)
673 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
674 #elif defined(CONFIG_NAND)
675 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
677 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
682 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
683 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
684 #endif /* CONFIG_NOBQFMAN */
686 #ifdef CONFIG_SYS_DPAA_FMAN
687 #define CONFIG_FMAN_ENET
688 #define CONFIG_PHY_VITESSE
689 #define CONFIG_PHY_REALTEK
692 #ifdef CONFIG_FMAN_ENET
693 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
694 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
696 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
697 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
699 #define CONFIG_MII /* MII PHY management */
700 #define CONFIG_ETHPRIME "FM1@DTSEC4"
701 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
707 #define CONFIG_LOADS_ECHO /* echo on for serial download */
708 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
711 * Command line configuration.
713 #include <config_cmd_default.h>
715 #ifdef CONFIG_T1042RDB_PI
716 #define CONFIG_CMD_DATE
718 #define CONFIG_CMD_DHCP
719 #define CONFIG_CMD_ELF
720 #define CONFIG_CMD_ERRATA
721 #define CONFIG_CMD_GREPENV
722 #define CONFIG_CMD_IRQ
723 #define CONFIG_CMD_I2C
724 #define CONFIG_CMD_MII
725 #define CONFIG_CMD_PING
726 #define CONFIG_CMD_REGINFO
727 #define CONFIG_CMD_SETEXPR
730 #define CONFIG_CMD_PCI
731 #define CONFIG_CMD_NET
735 * Miscellaneous configurable options
737 #define CONFIG_SYS_LONGHELP /* undef to save memory */
738 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
739 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
740 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
741 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
742 #ifdef CONFIG_CMD_KGDB
743 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
745 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
747 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
748 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
749 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
752 * For booting Linux, the board info and command line data
753 * have to be in the first 64 MB of memory, since this is
754 * the maximum mapped by the Linux kernel during initialization.
756 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
757 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
759 #ifdef CONFIG_CMD_KGDB
760 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
764 * Dynamic MTD Partition support with mtdparts
766 #ifndef CONFIG_SYS_NO_FLASH
767 #define CONFIG_MTD_DEVICE
768 #define CONFIG_MTD_PARTITIONS
769 #define CONFIG_CMD_MTDPARTS
770 #define CONFIG_FLASH_CFI_MTD
771 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
773 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
774 "128k(dtb),96m(fs),-(user);"\
775 "fff800000.flash:2m(uboot),9m(kernel),"\
776 "128k(dtb),96m(fs),-(user);spife110000.0:" \
777 "2m(uboot),9m(kernel),128k(dtb),-(user)"
781 * Environment Configuration
783 #define CONFIG_ROOTPATH "/opt/nfsroot"
784 #define CONFIG_BOOTFILE "uImage"
785 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
787 /* default location for tftp and bootm */
788 #define CONFIG_LOADADDR 1000000
790 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
792 #define CONFIG_BAUDRATE 115200
794 #define __USB_PHY_TYPE utmi
795 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
797 #ifdef CONFIG_T1040RDB
798 #define FDTFILE "t1040rdb/t1040rdb.dtb"
799 #elif defined(CONFIG_T1042RDB_PI)
800 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
801 #elif defined(CONFIG_T1042RDB)
802 #define FDTFILE "t1042rdb/t1042rdb.dtb"
805 #ifdef CONFIG_FSL_DIU_FB
806 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
808 #define DIU_ENVIRONMENT
811 #define CONFIG_EXTRA_ENV_SETTINGS \
812 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
813 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
814 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
816 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
817 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
818 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
819 "tftpflash=tftpboot $loadaddr $uboot && " \
820 "protect off $ubootaddr +$filesize && " \
821 "erase $ubootaddr +$filesize && " \
822 "cp.b $loadaddr $ubootaddr $filesize && " \
823 "protect on $ubootaddr +$filesize && " \
824 "cmp.b $loadaddr $ubootaddr $filesize\0" \
825 "consoledev=ttyS0\0" \
826 "ramdiskaddr=2000000\0" \
827 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
829 "fdtfile=" __stringify(FDTFILE) "\0" \
832 #define CONFIG_LINUX \
833 "setenv bootargs root=/dev/ram rw " \
834 "console=$consoledev,$baudrate $othbootargs;" \
835 "setenv ramdiskaddr 0x02000000;" \
836 "setenv fdtaddr 0x00c00000;" \
837 "setenv loadaddr 0x1000000;" \
838 "bootm $loadaddr $ramdiskaddr $fdtaddr"
840 #define CONFIG_HDBOOT \
841 "setenv bootargs root=/dev/$bdev rw " \
842 "console=$consoledev,$baudrate $othbootargs;" \
843 "tftp $loadaddr $bootfile;" \
844 "tftp $fdtaddr $fdtfile;" \
845 "bootm $loadaddr - $fdtaddr"
847 #define CONFIG_NFSBOOTCOMMAND \
848 "setenv bootargs root=/dev/nfs rw " \
849 "nfsroot=$serverip:$rootpath " \
850 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
851 "console=$consoledev,$baudrate $othbootargs;" \
852 "tftp $loadaddr $bootfile;" \
853 "tftp $fdtaddr $fdtfile;" \
854 "bootm $loadaddr - $fdtaddr"
856 #define CONFIG_RAMBOOTCOMMAND \
857 "setenv bootargs root=/dev/ram rw " \
858 "console=$consoledev,$baudrate $othbootargs;" \
859 "tftp $ramdiskaddr $ramdiskfile;" \
860 "tftp $loadaddr $bootfile;" \
861 "tftp $fdtaddr $fdtfile;" \
862 "bootm $loadaddr $ramdiskaddr $fdtaddr"
864 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
866 #ifdef CONFIG_SECURE_BOOT
867 #include <asm/fsl_secure_boot.h>
870 #endif /* __CONFIG_H */