include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_T104xRDB
  14 #define CONFIG_PHYS_64BIT
  15
  16 #ifdef CONFIG_RAMBOOT_PBL
  17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  18 #ifdef CONFIG_T1040RDB
  19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
  20 #endif
  21 #ifdef CONFIG_T1042RDB_PI
  22 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
  23 #endif
  24
  25 #define CONFIG_SPL
  26 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  27 #define CONFIG_SPL_ENV_SUPPORT
  28 #define CONFIG_SPL_SERIAL_SUPPORT
  29 #define CONFIG_SPL_FLUSH_IMAGE
  30 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  31 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  32 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  33 #define CONFIG_SPL_I2C_SUPPORT
  34 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  35 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  36 #define CONFIG_SYS_TEXT_BASE            0x00201000
  37 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  38 #define CONFIG_SPL_PAD_TO               0x40000
  39 #define CONFIG_SPL_MAX_SIZE             0x28000
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SPL_SKIP_RELOCATE
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #define CONFIG_SYS_NO_FLASH
  45 #endif
  46 #define RESET_VECTOR_OFFSET             0x27FFC
  47 #define BOOT_PAGE_OFFSET                0x27000
  48
  49 #ifdef CONFIG_NAND
  50 #define CONFIG_SPL_NAND_SUPPORT
  51 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  52 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  53 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  54 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  56 #define CONFIG_SPL_NAND_BOOT
  57 #endif
  58
  59 #ifdef CONFIG_SPIFLASH
  60 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  61 #define CONFIG_SPL_SPI_SUPPORT
  62 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  63 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  68 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  69 #ifndef CONFIG_SPL_BUILD
  70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  71 #endif
  72 #define CONFIG_SPL_SPI_BOOT
  73 #endif
  74
  75 #ifdef CONFIG_SDCARD
  76 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  77 #define CONFIG_SPL_MMC_SUPPORT
  78 #define CONFIG_SPL_MMC_MINIMAL
  79 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  80 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  81 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  82 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  83 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  84 #ifndef CONFIG_SPL_BUILD
  85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  86 #endif
  87 #define CONFIG_SPL_MMC_BOOT
  88 #endif
  89
  90 #endif
  91
  92 /* High Level Configuration Options */
  93 #define CONFIG_BOOKE
  94 #define CONFIG_E500                     /* BOOKE e500 family */
  95 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  96 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  97 #define CONFIG_MP                       /* support multiple processors */
  98
  99 /* support deep sleep */
 100 #define CONFIG_DEEP_SLEEP
 101 #define CONFIG_SILENT_CONSOLE
 102
 103 #ifndef CONFIG_SYS_TEXT_BASE
 104 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 105 #endif
 106
 107 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 108 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 109 #endif
 110
 111 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 112 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
 113 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 114 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 115 #define CONFIG_PCI_INDIRECT_BRIDGE
 116 #define CONFIG_PCIE1                    /* PCIE controler 1 */
 117 #define CONFIG_PCIE2                    /* PCIE controler 2 */
 118 #define CONFIG_PCIE3                    /* PCIE controler 3 */
 119 #define CONFIG_PCIE4                    /* PCIE controler 4 */
 120
 121 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 122 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 123
 124 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 125
 126 #define CONFIG_ENV_OVERWRITE
 127
 128 #ifndef CONFIG_SYS_NO_FLASH
 129 #define CONFIG_FLASH_CFI_DRIVER
 130 #define CONFIG_SYS_FLASH_CFI
 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 132 #endif
 133
 134 #if defined(CONFIG_SPIFLASH)
 135 #define CONFIG_SYS_EXTRA_ENV_RELOC
 136 #define CONFIG_ENV_IS_IN_SPI_FLASH
 137 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 138 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 139 #define CONFIG_ENV_SECT_SIZE            0x10000
 140 #elif defined(CONFIG_SDCARD)
 141 #define CONFIG_SYS_EXTRA_ENV_RELOC
 142 #define CONFIG_ENV_IS_IN_MMC
 143 #define CONFIG_SYS_MMC_ENV_DEV          0
 144 #define CONFIG_ENV_SIZE                 0x2000
 145 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 146 #elif defined(CONFIG_NAND)
 147 #define CONFIG_SYS_EXTRA_ENV_RELOC
 148 #define CONFIG_ENV_IS_IN_NAND
 149 #define CONFIG_ENV_SIZE                 0x2000
 150 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 151 #else
 152 #define CONFIG_ENV_IS_IN_FLASH
 153 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 154 #define CONFIG_ENV_SIZE         0x2000
 155 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 156 #endif
 157
 158 #define CONFIG_SYS_CLK_FREQ     100000000
 159 #define CONFIG_DDR_CLK_FREQ     66666666
 160
 161 /*
 162  * These can be toggled for performance analysis, otherwise use default.
 163  */
 164 #define CONFIG_SYS_CACHE_STASHING
 165 #define CONFIG_BACKSIDE_L2_CACHE
 166 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 167 #define CONFIG_BTB                      /* toggle branch predition */
 168 #define CONFIG_DDR_ECC
 169 #ifdef CONFIG_DDR_ECC
 170 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 171 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 172 #endif
 173
 174 #define CONFIG_ENABLE_36BIT_PHYS
 175
 176 #define CONFIG_ADDR_MAP
 177 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 178
 179 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 180 #define CONFIG_SYS_MEMTEST_END          0x00400000
 181 #define CONFIG_SYS_ALT_MEMTEST
 182 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 183
 184 /*
 185  *  Config the L3 Cache as L3 SRAM
 186  */
 187 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 188 #define CONFIG_SYS_L3_SIZE              256 << 10
 189 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 190 #ifdef CONFIG_RAMBOOT_PBL
 191 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 192 #endif
 193 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 194 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 195 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 196 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 197
 198 #define CONFIG_SYS_DCSRBAR              0xf0000000
 199 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 200
 201 /*
 202  * DDR Setup
 203  */
 204 #define CONFIG_VERY_BIG_RAM
 205 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 206 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 207
 208 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 209 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 210 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 211
 212 #define CONFIG_DDR_SPD
 213 #define CONFIG_SYS_DDR_RAW_TIMING
 214 #define CONFIG_SYS_FSL_DDR3
 215
 216 #define CONFIG_SYS_SPD_BUS_NUM  0
 217 #define SPD_EEPROM_ADDRESS      0x51
 218
 219 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 220
 221 /*
 222  * IFC Definitions
 223  */
 224 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 225 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 226
 227 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 228 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 229                                 CSPR_PORT_SIZE_16 | \
 230                                 CSPR_MSEL_NOR | \
 231                                 CSPR_V)
 232 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 233
 234 /*
 235  * TDM Definition
 236  */
 237 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 238
 239 /* NOR Flash Timing Params */
 240 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 241 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 242                                 FTIM0_NOR_TEADC(0x5) | \
 243                                 FTIM0_NOR_TEAHC(0x5))
 244 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 245                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 246                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 247 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 248                                 FTIM2_NOR_TCH(0x4) | \
 249                                 FTIM2_NOR_TWPH(0x0E) | \
 250                                 FTIM2_NOR_TWP(0x1c))
 251 #define CONFIG_SYS_NOR_FTIM3    0x0
 252
 253 #define CONFIG_SYS_FLASH_QUIET_TEST
 254 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 255
 256 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 257 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 258 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 259 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 260
 261 #define CONFIG_SYS_FLASH_EMPTY_INFO
 262 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 263
 264 /* CPLD on IFC */
 265 #define CPLD_LBMAP_MASK                 0x3F
 266 #define CPLD_BANK_SEL_MASK              0x07
 267 #define CPLD_BANK_OVERRIDE              0x40
 268 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 269 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 270 #define CPLD_LBMAP_RESET                0xFF
 271 #define CPLD_LBMAP_SHIFT                0x03
 272
 273 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 274 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 275 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 276 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 277                                 | CSPR_PORT_SIZE_8 \
 278                                 | CSPR_MSEL_GPCM \
 279                                 | CSPR_V)
 280 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 281 #define CONFIG_SYS_CSOR2        0x0
 282 /* CPLD Timing parameters for IFC CS2 */
 283 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 284                                         FTIM0_GPCM_TEADC(0x0e) | \
 285                                         FTIM0_GPCM_TEAHC(0x0e))
 286 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 287                                         FTIM1_GPCM_TRAD(0x1f))
 288 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 289                                         FTIM2_GPCM_TCH(0x0) | \
 290                                         FTIM2_GPCM_TWP(0x1f))
 291 #define CONFIG_SYS_CS2_FTIM3            0x0
 292
 293 /* NAND Flash on IFC */
 294 #define CONFIG_NAND_FSL_IFC
 295 #define CONFIG_SYS_NAND_BASE            0xff800000
 296 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 297
 298 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 299 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 300                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 301                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 302                                 | CSPR_V)
 303 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 304
 305 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 306                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 307                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 308                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 309                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 310                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 311                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 312
 313 #define CONFIG_SYS_NAND_ONFI_DETECTION
 314
 315 /* ONFI NAND Flash mode0 Timing Params */
 316 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 317                                         FTIM0_NAND_TWP(0x18)   | \
 318                                         FTIM0_NAND_TWCHT(0x07) | \
 319                                         FTIM0_NAND_TWH(0x0a))
 320 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 321                                         FTIM1_NAND_TWBE(0x39)  | \
 322                                         FTIM1_NAND_TRR(0x0e)   | \
 323                                         FTIM1_NAND_TRP(0x18))
 324 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 325                                         FTIM2_NAND_TREH(0x0a) | \
 326                                         FTIM2_NAND_TWHRE(0x1e))
 327 #define CONFIG_SYS_NAND_FTIM3           0x0
 328
 329 #define CONFIG_SYS_NAND_DDR_LAW         11
 330 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 331 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 332 #define CONFIG_MTD_NAND_VERIFY_WRITE
 333 #define CONFIG_CMD_NAND
 334
 335 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 336
 337 #if defined(CONFIG_NAND)
 338 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 339 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 340 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 341 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 342 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 343 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 344 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 345 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 346 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 347 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 348 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 349 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 350 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 351 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 352 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 353 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 354 #else
 355 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 356 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 357 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 358 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 359 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 360 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 361 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 362 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 363 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 364 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 365 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 366 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 367 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 368 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 369 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 370 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 371 #endif
 372
 373 #ifdef CONFIG_SPL_BUILD
 374 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 375 #else
 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 377 #endif
 378
 379 #if defined(CONFIG_RAMBOOT_PBL)
 380 #define CONFIG_SYS_RAMBOOT
 381 #endif
 382
 383 #define CONFIG_BOARD_EARLY_INIT_R
 384 #define CONFIG_MISC_INIT_R
 385
 386 #define CONFIG_HWCONFIG
 387
 388 /* define to use L1 as initial stack */
 389 #define CONFIG_L1_INIT_RAM
 390 #define CONFIG_SYS_INIT_RAM_LOCK
 391 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 394 /* The assembler doesn't like typecast */
 395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 396         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 397           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 398 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 399
 400 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 401                                         GENERATED_GBL_DATA_SIZE)
 402 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 403
 404 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 405 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 406
 407 /* Serial Port - controlled on board with jumper J8
 408  * open - index 2
 409  * shorted - index 1
 410  */
 411 #define CONFIG_CONS_INDEX       1
 412 #define CONFIG_SYS_NS16550
 413 #define CONFIG_SYS_NS16550_SERIAL
 414 #define CONFIG_SYS_NS16550_REG_SIZE     1
 415 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 416
 417 #define CONFIG_SYS_BAUDRATE_TABLE       \
 418         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 419
 420 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 421 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 422 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 423 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 424 #define CONFIG_SERIAL_MULTI             /* Enable both serial ports */
 425 #ifndef CONFIG_SPL_BUILD
 426 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 427 #endif
 428
 429 /* Use the HUSH parser */
 430 #define CONFIG_SYS_HUSH_PARSER
 431 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 432
 433 /* pass open firmware flat tree */
 434 #define CONFIG_OF_LIBFDT
 435 #define CONFIG_OF_BOARD_SETUP
 436 #define CONFIG_OF_STDOUT_VIA_ALIAS
 437
 438 /* new uImage format support */
 439 #define CONFIG_FIT
 440 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 441
 442 /* I2C */
 443 #define CONFIG_SYS_I2C
 444 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 445 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 446 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 447 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 448 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 449 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 450 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 451
 452 /* I2C bus multiplexer */
 453 #define I2C_MUX_PCA_ADDR                0x70
 454 #ifdef CONFIG_T1040RDB
 455 #define I2C_MUX_CH_DEFAULT      0x8
 456 #endif
 457
 458 #ifdef CONFIG_T1042RDB_PI
 459 /*
 460  * RTC configuration
 461  */
 462 #define RTC
 463 #define CONFIG_RTC_DS1337               1
 464 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 465
 466 /*DVI encoder*/
 467 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 468 #endif
 469
 470 /*
 471  * eSPI - Enhanced SPI
 472  */
 473 #define CONFIG_FSL_ESPI
 474 #define CONFIG_SPI_FLASH
 475 #define CONFIG_SPI_FLASH_STMICRO
 476 #define CONFIG_CMD_SF
 477 #define CONFIG_SF_DEFAULT_SPEED         10000000
 478 #define CONFIG_SF_DEFAULT_MODE          0
 479 #define CONFIG_ENV_SPI_BUS              0
 480 #define CONFIG_ENV_SPI_CS               0
 481 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 482 #define CONFIG_ENV_SPI_MODE             0
 483
 484 /*
 485  * General PCI
 486  * Memory space is mapped 1-1, but I/O space must start from 0.
 487  */
 488
 489 #ifdef CONFIG_PCI
 490 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 491 #ifdef CONFIG_PCIE1
 492 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 493 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 494 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 495 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 496 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 497 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 498 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 499 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 500 #endif
 501
 502 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 503 #ifdef CONFIG_PCIE2
 504 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 505 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 506 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 507 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 508 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 509 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 510 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 511 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 512 #endif
 513
 514 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 515 #ifdef CONFIG_PCIE3
 516 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 517 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 518 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 519 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 520 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 521 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 522 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 523 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 524 #endif
 525
 526 /* controller 4, Base address 203000 */
 527 #ifdef CONFIG_PCIE4
 528 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 529 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 530 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 531 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 532 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 533 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 534 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 535 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 536 #endif
 537
 538 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 539 #define CONFIG_E1000
 540
 541 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 542 #define CONFIG_DOS_PARTITION
 543 #endif  /* CONFIG_PCI */
 544
 545 /* SATA */
 546 #define CONFIG_FSL_SATA_V2
 547 #ifdef CONFIG_FSL_SATA_V2
 548 #define CONFIG_LIBATA
 549 #define CONFIG_FSL_SATA
 550
 551 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 552 #define CONFIG_SATA1
 553 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 554 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 555
 556 #define CONFIG_LBA48
 557 #define CONFIG_CMD_SATA
 558 #define CONFIG_DOS_PARTITION
 559 #define CONFIG_CMD_EXT2
 560 #endif
 561
 562 /*
 563 * USB
 564 */
 565 #define CONFIG_HAS_FSL_DR_USB
 566
 567 #ifdef CONFIG_HAS_FSL_DR_USB
 568 #define CONFIG_USB_EHCI
 569
 570 #ifdef CONFIG_USB_EHCI
 571 #define CONFIG_CMD_USB
 572 #define CONFIG_USB_STORAGE
 573 #define CONFIG_USB_EHCI_FSL
 574 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 575 #define CONFIG_CMD_EXT2
 576 #endif
 577 #endif
 578
 579 #define CONFIG_MMC
 580
 581 #ifdef CONFIG_MMC
 582 #define CONFIG_FSL_ESDHC
 583 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 584 #define CONFIG_CMD_MMC
 585 #define CONFIG_GENERIC_MMC
 586 #define CONFIG_CMD_EXT2
 587 #define CONFIG_CMD_FAT
 588 #define CONFIG_DOS_PARTITION
 589 #endif
 590
 591 /* Qman/Bman */
 592 #ifndef CONFIG_NOBQFMAN
 593 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 594 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 595 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 596 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 597 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 598 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 599 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 600 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 601 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 602
 603 #define CONFIG_SYS_DPAA_FMAN
 604 #define CONFIG_SYS_DPAA_PME
 605
 606 #ifdef CONFIG_T1040RDB
 607 #define CONFIG_QE
 608 #define CONFIG_U_QE
 609 #endif
 610
 611 /* Default address of microcode for the Linux Fman driver */
 612 #if defined(CONFIG_SPIFLASH)
 613 /*
 614  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 615  * env, so we got 0x110000.
 616  */
 617 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 618 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 619 #elif defined(CONFIG_SDCARD)
 620 /*
 621  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 622  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 623  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 624  */
 625 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 626 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 627 #elif defined(CONFIG_NAND)
 628 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 629 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 630 #else
 631 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 632 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 633 #endif
 634
 635 #ifdef CONFIG_T1040RDB
 636 #if defined(CONFIG_SPIFLASH)
 637 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 638 #elif defined(CONFIG_SDCARD)
 639 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 640 #elif defined(CONFIG_NAND)
 641 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 642 #else
 643 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 644 #endif
 645 #endif
 646
 647
 648 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 649 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 650 #endif /* CONFIG_NOBQFMAN */
 651
 652 #ifdef CONFIG_SYS_DPAA_FMAN
 653 #define CONFIG_FMAN_ENET
 654 #define CONFIG_PHY_VITESSE
 655 #define CONFIG_PHY_REALTEK
 656 #endif
 657
 658 #ifdef CONFIG_FMAN_ENET
 659 #ifdef CONFIG_T1040RDB
 660 #define CONFIG_SYS_SGMII1_PHY_ADDR              0x03
 661 #endif
 662 #define CONFIG_SYS_RGMII1_PHY_ADDR              0x01
 663 #define CONFIG_SYS_RGMII2_PHY_ADDR              0x02
 664
 665 #define CONFIG_MII              /* MII PHY management */
 666 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 667 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 668 #endif
 669
 670 /*
 671  * Environment
 672  */
 673 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 674 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 675
 676 /*
 677  * Command line configuration.
 678  */
 679 #include <config_cmd_default.h>
 680
 681 #ifdef CONFIG_T1042RDB_PI
 682 #define CONFIG_CMD_DATE
 683 #endif
 684 #define CONFIG_CMD_DHCP
 685 #define CONFIG_CMD_ELF
 686 #define CONFIG_CMD_ERRATA
 687 #define CONFIG_CMD_GREPENV
 688 #define CONFIG_CMD_IRQ
 689 #define CONFIG_CMD_I2C
 690 #define CONFIG_CMD_MII
 691 #define CONFIG_CMD_PING
 692 #define CONFIG_CMD_REGINFO
 693 #define CONFIG_CMD_SETEXPR
 694
 695 #ifdef CONFIG_PCI
 696 #define CONFIG_CMD_PCI
 697 #define CONFIG_CMD_NET
 698 #endif
 699
 700 /*
 701  * Miscellaneous configurable options
 702  */
 703 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 704 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 705 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 706 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 707 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 708 #ifdef CONFIG_CMD_KGDB
 709 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 710 #else
 711 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 712 #endif
 713 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 714 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 715 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 716
 717 /*
 718  * For booting Linux, the board info and command line data
 719  * have to be in the first 64 MB of memory, since this is
 720  * the maximum mapped by the Linux kernel during initialization.
 721  */
 722 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 723 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 724
 725 #ifdef CONFIG_CMD_KGDB
 726 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 727 #endif
 728
 729 /*
 730  * Dynamic MTD Partition support with mtdparts
 731  */
 732 #ifndef CONFIG_SYS_NO_FLASH
 733 #define CONFIG_MTD_DEVICE
 734 #define CONFIG_MTD_PARTITIONS
 735 #define CONFIG_CMD_MTDPARTS
 736 #define CONFIG_FLASH_CFI_MTD
 737 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 738                         "spi0=spife110000.0"
 739 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 740                                 "128k(dtb),96m(fs),-(user);"\
 741                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 742                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 743                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 744 #endif
 745
 746 /*
 747  * Environment Configuration
 748  */
 749 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 750 #define CONFIG_BOOTFILE         "uImage"
 751 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 752
 753 /* default location for tftp and bootm */
 754 #define CONFIG_LOADADDR         1000000
 755
 756 #define CONFIG_BOOTDELAY        10      /*-1 disables auto-boot*/
 757
 758 #define CONFIG_BAUDRATE 115200
 759
 760 #define __USB_PHY_TYPE  utmi
 761
 762 #ifdef CONFIG_T1040RDB
 763 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 764 #define RAMDISKFILE     "t1040rdb/ramdisk.uboot"
 765 #elif CONFIG_T1042RDB_PI
 766 #define FDTFILE         "t1040rdb_pi/t1040rdb_pi.dtb"
 767 #define RAMDISKFILE     "t1040rdb_pi/ramdisk.uboot"
 768 #endif
 769
 770 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 771         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 772         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 773         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 774         "netdev=eth0\0"                                         \
 775         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 776         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 777         "tftpflash=tftpboot $loadaddr $uboot && "               \
 778         "protect off $ubootaddr +$filesize && "                 \
 779         "erase $ubootaddr +$filesize && "                       \
 780         "cp.b $loadaddr $ubootaddr $filesize && "               \
 781         "protect on $ubootaddr +$filesize && "                  \
 782         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 783         "consoledev=ttyS0\0"                                    \
 784         "ramdiskaddr=2000000\0"                                 \
 785         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 786         "fdtaddr=c00000\0"                                      \
 787         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 788         "bdev=sda3\0"
 789
 790 #define CONFIG_LINUX                       \
 791         "setenv bootargs root=/dev/ram rw "            \
 792         "console=$consoledev,$baudrate $othbootargs;"  \
 793         "setenv ramdiskaddr 0x02000000;"               \
 794         "setenv fdtaddr 0x00c00000;"                   \
 795         "setenv loadaddr 0x1000000;"                   \
 796         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 797
 798 #define CONFIG_HDBOOT                                   \
 799         "setenv bootargs root=/dev/$bdev rw "           \
 800         "console=$consoledev,$baudrate $othbootargs;"   \
 801         "tftp $loadaddr $bootfile;"                     \
 802         "tftp $fdtaddr $fdtfile;"                       \
 803         "bootm $loadaddr - $fdtaddr"
 804
 805 #define CONFIG_NFSBOOTCOMMAND                   \
 806         "setenv bootargs root=/dev/nfs rw "     \
 807         "nfsroot=$serverip:$rootpath "          \
 808         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 809         "console=$consoledev,$baudrate $othbootargs;"   \
 810         "tftp $loadaddr $bootfile;"             \
 811         "tftp $fdtaddr $fdtfile;"               \
 812         "bootm $loadaddr - $fdtaddr"
 813
 814 #define CONFIG_RAMBOOTCOMMAND                           \
 815         "setenv bootargs root=/dev/ram rw "             \
 816         "console=$consoledev,$baudrate $othbootargs;"   \
 817         "tftp $ramdiskaddr $ramdiskfile;"               \
 818         "tftp $loadaddr $bootfile;"                     \
 819         "tftp $fdtaddr $fdtfile;"                       \
 820         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 821
 822 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 823
 824 #ifdef CONFIG_SECURE_BOOT
 825 #include <asm/fsl_secure_boot.h>
 826 #endif
 827
 828 #endif  /* __CONFIG_H */