2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * T1040 RDB board configuration file
29 #define CONFIG_T104xRDB
30 #define CONFIG_T1040RDB
31 #define CONFIG_PHYS_64BIT
33 #ifdef CONFIG_RAMBOOT_PBL
34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
38 /* High Level Configuration Options */
40 #define CONFIG_E500 /* BOOKE e500 family */
41 #define CONFIG_E500MC /* BOOKE e500mc family */
42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
43 #define CONFIG_MP /* support multiple processors */
45 #ifndef CONFIG_SYS_TEXT_BASE
46 #define CONFIG_SYS_TEXT_BASE 0xeff40000
49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
55 #define CONFIG_FSL_IFC /* Enable IFC Support */
56 #define CONFIG_PCI /* Enable PCI/PCIE */
57 #define CONFIG_PCI_INDIRECT_BRIDGE
58 #define CONFIG_PCIE1 /* PCIE controler 1 */
59 #define CONFIG_PCIE2 /* PCIE controler 2 */
60 #define CONFIG_PCIE3 /* PCIE controler 3 */
61 #define CONFIG_PCIE4 /* PCIE controler 4 */
63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
66 #define CONFIG_FSL_LAW /* Use common FSL init code */
68 #define CONFIG_ENV_OVERWRITE
70 #ifdef CONFIG_SYS_NO_FLASH
71 #define CONFIG_ENV_IS_NOWHERE
73 #define CONFIG_FLASH_CFI_DRIVER
74 #define CONFIG_SYS_FLASH_CFI
75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
78 #ifndef CONFIG_SYS_NO_FLASH
79 #if defined(CONFIG_SPIFLASH)
80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_ENV_IS_IN_SPI_FLASH
82 #define CONFIG_ENV_SPI_BUS 0
83 #define CONFIG_ENV_SPI_CS 0
84 #define CONFIG_ENV_SPI_MAX_HZ 10000000
85 #define CONFIG_ENV_SPI_MODE 0
86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
88 #define CONFIG_ENV_SECT_SIZE 0x10000
89 #elif defined(CONFIG_SDCARD)
90 #define CONFIG_SYS_EXTRA_ENV_RELOC
91 #define CONFIG_ENV_IS_IN_MMC
92 #define CONFIG_SYS_MMC_ENV_DEV 0
93 #define CONFIG_ENV_SIZE 0x2000
94 #define CONFIG_ENV_OFFSET (512 * 1658)
95 #elif defined(CONFIG_NAND)
96 #define CONFIG_SYS_EXTRA_ENV_RELOC
97 #define CONFIG_ENV_IS_IN_NAND
98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
99 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
101 #define CONFIG_ENV_IS_IN_FLASH
102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
103 #define CONFIG_ENV_SIZE 0x2000
104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
106 #else /* CONFIG_SYS_NO_FLASH */
107 #define CONFIG_ENV_SIZE 0x2000
108 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
111 #define CONFIG_SYS_CLK_FREQ 100000000
112 #define CONFIG_DDR_CLK_FREQ 66666666
115 * These can be toggled for performance analysis, otherwise use default.
117 #define CONFIG_SYS_CACHE_STASHING
118 #define CONFIG_BACKSIDE_L2_CACHE
119 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
120 #define CONFIG_BTB /* toggle branch predition */
121 #define CONFIG_DDR_ECC
122 #ifdef CONFIG_DDR_ECC
123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
124 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
127 #define CONFIG_ENABLE_36BIT_PHYS
129 #define CONFIG_ADDR_MAP
130 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
132 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_END 0x00400000
134 #define CONFIG_SYS_ALT_MEMTEST
135 #define CONFIG_PANIC_HANG /* do not reset board on panic */
138 * Config the L3 Cache as L3 SRAM
140 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
142 #define CONFIG_SYS_DCSRBAR 0xf0000000
143 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
148 #define CONFIG_VERY_BIG_RAM
149 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
150 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
152 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
153 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
154 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
156 #define CONFIG_DDR_SPD
157 #define CONFIG_SYS_DDR_RAW_TIMING
158 #define CONFIG_SYS_FSL_DDR3
160 #define CONFIG_SYS_SPD_BUS_NUM 0
161 #define SPD_EEPROM_ADDRESS 0x51
163 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
168 #define CONFIG_SYS_FLASH_BASE 0xe8000000
169 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
171 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
172 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
173 CSPR_PORT_SIZE_16 | \
176 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
177 /* NOR Flash Timing Params */
178 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
179 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
180 FTIM0_NOR_TEADC(0x5) | \
181 FTIM0_NOR_TEAHC(0x5))
182 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
183 FTIM1_NOR_TRAD_NOR(0x1A) |\
184 FTIM1_NOR_TSEQRAD_NOR(0x13))
185 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
186 FTIM2_NOR_TCH(0x4) | \
187 FTIM2_NOR_TWPH(0x0E) | \
189 #define CONFIG_SYS_NOR_FTIM3 0x0
191 #define CONFIG_SYS_FLASH_QUIET_TEST
192 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
194 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
195 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
196 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
197 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
199 #define CONFIG_SYS_FLASH_EMPTY_INFO
200 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
203 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
204 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
205 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
209 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
210 #define CONFIG_SYS_CSOR2 0x0
211 /* CPLD Timing parameters for IFC CS2 */
212 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
213 FTIM0_GPCM_TEADC(0x0e) | \
214 FTIM0_GPCM_TEAHC(0x0e))
215 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
216 FTIM1_GPCM_TRAD(0x1f))
217 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
218 FTIM2_GPCM_TCH(0x0) | \
219 FTIM2_GPCM_TWP(0x1f))
220 #define CONFIG_SYS_CS2_FTIM3 0x0
222 /* NAND Flash on IFC */
223 #define CONFIG_NAND_FSL_IFC
224 #define CONFIG_SYS_NAND_BASE 0xff800000
225 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
227 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
228 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
229 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
230 | CSPR_MSEL_NAND /* MSEL = NAND */ \
232 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
234 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
235 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
236 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
237 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
238 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
239 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
240 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
242 #define CONFIG_SYS_NAND_ONFI_DETECTION
244 /* ONFI NAND Flash mode0 Timing Params */
245 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
246 FTIM0_NAND_TWP(0x18) | \
247 FTIM0_NAND_TWCHT(0x07) | \
248 FTIM0_NAND_TWH(0x0a))
249 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
250 FTIM1_NAND_TWBE(0x39) | \
251 FTIM1_NAND_TRR(0x0e) | \
252 FTIM1_NAND_TRP(0x18))
253 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
254 FTIM2_NAND_TREH(0x0a) | \
255 FTIM2_NAND_TWHRE(0x1e))
256 #define CONFIG_SYS_NAND_FTIM3 0x0
258 #define CONFIG_SYS_NAND_DDR_LAW 11
259 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
260 #define CONFIG_SYS_MAX_NAND_DEVICE 1
261 #define CONFIG_MTD_NAND_VERIFY_WRITE
262 #define CONFIG_CMD_NAND
264 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
266 #if defined(CONFIG_NAND)
267 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
268 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
269 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
270 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
271 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
272 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
273 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
274 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
275 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
276 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
277 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
278 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
279 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
280 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
281 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
282 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
284 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
285 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
286 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
287 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
288 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
289 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
290 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
291 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
292 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
293 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
294 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
295 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
296 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
297 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
298 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
299 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
302 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
304 #if defined(CONFIG_RAMBOOT_PBL)
305 #define CONFIG_SYS_RAMBOOT
308 #define CONFIG_BOARD_EARLY_INIT_R
309 #define CONFIG_MISC_INIT_R
311 #define CONFIG_HWCONFIG
313 /* define to use L1 as initial stack */
314 #define CONFIG_L1_INIT_RAM
315 #define CONFIG_SYS_INIT_RAM_LOCK
316 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
319 /* The assembler doesn't like typecast */
320 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
321 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
322 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
323 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
325 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
326 GENERATED_GBL_DATA_SIZE)
327 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
329 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
330 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
332 /* Serial Port - controlled on board with jumper J8
336 #define CONFIG_CONS_INDEX 1
337 #define CONFIG_SYS_NS16550
338 #define CONFIG_SYS_NS16550_SERIAL
339 #define CONFIG_SYS_NS16550_REG_SIZE 1
340 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
342 #define CONFIG_SYS_BAUDRATE_TABLE \
343 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
345 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
346 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
347 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
348 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
349 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
350 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
352 /* Use the HUSH parser */
353 #define CONFIG_SYS_HUSH_PARSER
354 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
356 /* pass open firmware flat tree */
357 #define CONFIG_OF_LIBFDT
358 #define CONFIG_OF_BOARD_SETUP
359 #define CONFIG_OF_STDOUT_VIA_ALIAS
361 /* new uImage format support */
363 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
366 #define CONFIG_SYS_I2C
367 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
368 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
369 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
370 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
371 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
372 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
373 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
375 /* I2C bus multiplexer */
376 #define I2C_MUX_PCA_ADDR 0x70
377 #define I2C_MUX_CH_DEFAULT 0x8
381 * eSPI - Enhanced SPI
383 #define CONFIG_FSL_ESPI
384 #define CONFIG_SPI_FLASH
385 #define CONFIG_SPI_FLASH_STMICRO
386 #define CONFIG_CMD_SF
387 #define CONFIG_SF_DEFAULT_SPEED 10000000
388 #define CONFIG_SF_DEFAULT_MODE 0
392 * Memory space is mapped 1-1, but I/O space must start from 0.
396 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
398 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
399 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
401 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
402 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
403 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
404 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
405 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
408 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
410 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
411 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
412 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
413 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
414 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
415 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
416 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
417 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
420 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
422 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
423 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
424 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
425 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
426 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
427 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
428 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
429 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
432 /* controller 4, Base address 203000 */
434 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
435 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
436 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
437 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
438 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
439 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
440 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
441 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
444 #define CONFIG_PCI_PNP /* do pci plug-and-play */
447 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
448 #define CONFIG_DOS_PARTITION
449 #endif /* CONFIG_PCI */
452 #define CONFIG_FSL_SATA_V2
453 #ifdef CONFIG_FSL_SATA_V2
454 #define CONFIG_LIBATA
455 #define CONFIG_FSL_SATA
457 #define CONFIG_SYS_SATA_MAX_DEVICE 1
459 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
460 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
463 #define CONFIG_CMD_SATA
464 #define CONFIG_DOS_PARTITION
465 #define CONFIG_CMD_EXT2
471 #define CONFIG_HAS_FSL_DR_USB
473 #ifdef CONFIG_HAS_FSL_DR_USB
474 #define CONFIG_USB_EHCI
476 #ifdef CONFIG_USB_EHCI
477 #define CONFIG_CMD_USB
478 #define CONFIG_USB_STORAGE
479 #define CONFIG_USB_EHCI_FSL
480 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
481 #define CONFIG_CMD_EXT2
488 #define CONFIG_FSL_ESDHC
489 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
490 #define CONFIG_CMD_MMC
491 #define CONFIG_GENERIC_MMC
492 #define CONFIG_CMD_EXT2
493 #define CONFIG_CMD_FAT
494 #define CONFIG_DOS_PARTITION
498 #ifndef CONFIG_NOBQFMAN
499 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
500 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
501 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
502 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
503 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
504 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
505 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
506 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
507 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
509 #define CONFIG_SYS_DPAA_FMAN
510 #define CONFIG_SYS_DPAA_PME
512 /* Default address of microcode for the Linux Fman driver */
513 #if defined(CONFIG_SPIFLASH)
515 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
516 * env, so we got 0x110000.
518 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
519 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
520 #elif defined(CONFIG_SDCARD)
522 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
523 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
524 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
526 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
527 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
528 #elif defined(CONFIG_NAND)
529 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
530 #define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
532 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
533 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
535 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
536 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
537 #endif /* CONFIG_NOBQFMAN */
539 #ifdef CONFIG_SYS_DPAA_FMAN
540 #define CONFIG_FMAN_ENET
541 #define CONFIG_PHY_VITESSE
542 #define CONFIG_PHY_REALTEK
545 #ifdef CONFIG_FMAN_ENET
546 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
547 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
548 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
549 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
551 #define CONFIG_MII /* MII PHY management */
552 #define CONFIG_ETHPRIME "FM1@DTSEC1"
553 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
559 #define CONFIG_LOADS_ECHO /* echo on for serial download */
560 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
563 * Command line configuration.
565 #include <config_cmd_default.h>
567 #define CONFIG_CMD_DHCP
568 #define CONFIG_CMD_ELF
569 #define CONFIG_CMD_ERRATA
570 #define CONFIG_CMD_GREPENV
571 #define CONFIG_CMD_IRQ
572 #define CONFIG_CMD_I2C
573 #define CONFIG_CMD_MII
574 #define CONFIG_CMD_PING
575 #define CONFIG_CMD_REGINFO
576 #define CONFIG_CMD_SETEXPR
579 #define CONFIG_CMD_PCI
580 #define CONFIG_CMD_NET
584 * Miscellaneous configurable options
586 #define CONFIG_SYS_LONGHELP /* undef to save memory */
587 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
588 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
589 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
590 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
591 #ifdef CONFIG_CMD_KGDB
592 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
594 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
596 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
597 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
598 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
599 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
602 * For booting Linux, the board info and command line data
603 * have to be in the first 64 MB of memory, since this is
604 * the maximum mapped by the Linux kernel during initialization.
606 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
607 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
609 #ifdef CONFIG_CMD_KGDB
610 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
614 * Environment Configuration
616 #define CONFIG_ROOTPATH "/opt/nfsroot"
617 #define CONFIG_BOOTFILE "uImage"
618 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
620 /* default location for tftp and bootm */
621 #define CONFIG_LOADADDR 1000000
623 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
625 #define CONFIG_BAUDRATE 115200
627 #define __USB_PHY_TYPE utmi
629 #define CONFIG_EXTRA_ENV_SETTINGS \
630 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
631 "bank_intlv=cs0_cs1;" \
632 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
634 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
635 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
636 "tftpflash=tftpboot $loadaddr $uboot && " \
637 "protect off $ubootaddr +$filesize && " \
638 "erase $ubootaddr +$filesize && " \
639 "cp.b $loadaddr $ubootaddr $filesize && " \
640 "protect on $ubootaddr +$filesize && " \
641 "cmp.b $loadaddr $ubootaddr $filesize\0" \
642 "consoledev=ttyS0\0" \
643 "ramdiskaddr=2000000\0" \
644 "ramdiskfile=t1040rdb/ramdisk.uboot\0" \
646 "fdtfile=t1040rdb/t1040rdb.dtb\0" \
650 #define CONFIG_LINUX \
651 "setenv bootargs root=/dev/ram rw " \
652 "console=$consoledev,$baudrate $othbootargs;" \
653 "setenv ramdiskaddr 0x02000000;" \
654 "setenv fdtaddr 0x00c00000;" \
655 "setenv loadaddr 0x1000000;" \
656 "bootm $loadaddr $ramdiskaddr $fdtaddr"
658 #define CONFIG_HDBOOT \
659 "setenv bootargs root=/dev/$bdev rw " \
660 "console=$consoledev,$baudrate $othbootargs;" \
661 "tftp $loadaddr $bootfile;" \
662 "tftp $fdtaddr $fdtfile;" \
663 "bootm $loadaddr - $fdtaddr"
665 #define CONFIG_NFSBOOTCOMMAND \
666 "setenv bootargs root=/dev/nfs rw " \
667 "nfsroot=$serverip:$rootpath " \
668 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
669 "console=$consoledev,$baudrate $othbootargs;" \
670 "tftp $loadaddr $bootfile;" \
671 "tftp $fdtaddr $fdtfile;" \
672 "bootm $loadaddr - $fdtaddr"
674 #define CONFIG_RAMBOOTCOMMAND \
675 "setenv bootargs root=/dev/ram rw " \
676 "console=$consoledev,$baudrate $othbootargs;" \
677 "tftp $ramdiskaddr $ramdiskfile;" \
678 "tftp $loadaddr $bootfile;" \
679 "tftp $fdtaddr $fdtfile;" \
680 "bootm $loadaddr $ramdiskaddr $fdtaddr"
682 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
684 #ifdef CONFIG_SECURE_BOOT
685 #include <asm/fsl_secure_boot.h>
688 #endif /* __CONFIG_H */