2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * T1040 QDS board configuration file
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
38 /* High Level Configuration Options */
39 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
41 /* support deep sleep */
42 #define CONFIG_DEEP_SLEEP
44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
49 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
50 #define CONFIG_PCI_INDIRECT_BRIDGE
51 #define CONFIG_PCIE1 /* PCIE controller 1 */
52 #define CONFIG_PCIE2 /* PCIE controller 2 */
53 #define CONFIG_PCIE3 /* PCIE controller 3 */
54 #define CONFIG_PCIE4 /* PCIE controller 4 */
56 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
57 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
59 #define CONFIG_ENV_OVERWRITE
61 #ifdef CONFIG_MTD_NOR_FLASH
62 #if defined(CONFIG_SPIFLASH)
63 #elif defined(CONFIG_SDCARD)
64 #define CONFIG_SYS_MMC_ENV_DEV 0
69 unsigned long get_board_sys_clk(void);
70 unsigned long get_board_ddr_clk(void);
73 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
74 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
77 * These can be toggled for performance analysis, otherwise use default.
79 #define CONFIG_SYS_CACHE_STASHING
80 #define CONFIG_BACKSIDE_L2_CACHE
81 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
82 #define CONFIG_BTB /* toggle branch predition */
83 #define CONFIG_DDR_ECC
85 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
86 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
89 #define CONFIG_ENABLE_36BIT_PHYS
91 #define CONFIG_ADDR_MAP
92 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
94 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
95 #define CONFIG_SYS_MEMTEST_END 0x00400000
98 * Config the L3 Cache as L3 SRAM
100 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
102 #define CONFIG_SYS_DCSRBAR 0xf0000000
103 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
106 #define CONFIG_ID_EEPROM
107 #define CONFIG_SYS_I2C_EEPROM_NXID
108 #define CONFIG_SYS_EEPROM_BUS_NUM 0
109 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
110 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
112 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
117 #define CONFIG_VERY_BIG_RAM
118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
122 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
124 #define CONFIG_DDR_SPD
126 #define CONFIG_SYS_SPD_BUS_NUM 0
127 #define SPD_EEPROM_ADDRESS 0x51
129 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
134 #define CONFIG_SYS_FLASH_BASE 0xe0000000
135 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
137 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
138 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
140 CSPR_PORT_SIZE_16 | \
143 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
144 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
145 CSPR_PORT_SIZE_16 | \
148 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
153 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
155 /* NOR Flash Timing Params */
156 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
157 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
158 FTIM0_NOR_TEADC(0x5) | \
159 FTIM0_NOR_TEAHC(0x5))
160 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
161 FTIM1_NOR_TRAD_NOR(0x1A) |\
162 FTIM1_NOR_TSEQRAD_NOR(0x13))
163 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
164 FTIM2_NOR_TCH(0x4) | \
165 FTIM2_NOR_TWPH(0x0E) | \
167 #define CONFIG_SYS_NOR_FTIM3 0x0
169 #define CONFIG_SYS_FLASH_QUIET_TEST
170 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
172 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
173 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
174 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
175 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
177 #define CONFIG_SYS_FLASH_EMPTY_INFO
178 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
179 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
180 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
181 #define QIXIS_BASE 0xffdf0000
182 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
183 #define QIXIS_LBMAP_SWITCH 0x06
184 #define QIXIS_LBMAP_MASK 0x0f
185 #define QIXIS_LBMAP_SHIFT 0
186 #define QIXIS_LBMAP_DFLTBANK 0x00
187 #define QIXIS_LBMAP_ALTBANK 0x04
188 #define QIXIS_RST_CTL_RESET 0x31
189 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
190 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
191 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
192 #define QIXIS_RST_FORCE_MEM 0x01
194 #define CONFIG_SYS_CSPR3_EXT (0xf)
195 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
199 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
200 #define CONFIG_SYS_CSOR3 0x0
201 /* QIXIS Timing parameters for IFC CS3 */
202 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
203 FTIM0_GPCM_TEADC(0x0e) | \
204 FTIM0_GPCM_TEAHC(0x0e))
205 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
206 FTIM1_GPCM_TRAD(0x3f))
207 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
208 FTIM2_GPCM_TCH(0x8) | \
209 FTIM2_GPCM_TWP(0x1f))
210 #define CONFIG_SYS_CS3_FTIM3 0x0
212 #define CONFIG_NAND_FSL_IFC
213 #define CONFIG_SYS_NAND_BASE 0xff800000
214 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
216 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
217 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
218 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
219 | CSPR_MSEL_NAND /* MSEL = NAND */ \
221 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
223 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
224 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
225 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
226 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
227 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
228 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
229 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
231 #define CONFIG_SYS_NAND_ONFI_DETECTION
233 /* ONFI NAND Flash mode0 Timing Params */
234 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
235 FTIM0_NAND_TWP(0x18) | \
236 FTIM0_NAND_TWCHT(0x07) | \
237 FTIM0_NAND_TWH(0x0a))
238 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
239 FTIM1_NAND_TWBE(0x39) | \
240 FTIM1_NAND_TRR(0x0e) | \
241 FTIM1_NAND_TRP(0x18))
242 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
243 FTIM2_NAND_TREH(0x0a) | \
244 FTIM2_NAND_TWHRE(0x1e))
245 #define CONFIG_SYS_NAND_FTIM3 0x0
247 #define CONFIG_SYS_NAND_DDR_LAW 11
248 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
249 #define CONFIG_SYS_MAX_NAND_DEVICE 1
251 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
253 #if defined(CONFIG_MTD_RAW_NAND)
254 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
255 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
256 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
257 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
258 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
259 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
260 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
261 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
262 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
263 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
264 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
265 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
266 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
267 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
268 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
269 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
270 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
271 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
272 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
273 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
274 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
275 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
276 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
277 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
279 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
280 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
281 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
282 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
283 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
284 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
285 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
286 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
287 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
288 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
289 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
290 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
291 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
292 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
293 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
294 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
295 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
296 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
297 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
298 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
299 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
300 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
301 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
302 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
305 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
307 #if defined(CONFIG_RAMBOOT_PBL)
308 #define CONFIG_SYS_RAMBOOT
311 #define CONFIG_HWCONFIG
313 /* define to use L1 as initial stack */
314 #define CONFIG_L1_INIT_RAM
315 #define CONFIG_SYS_INIT_RAM_LOCK
316 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
319 /* The assembler doesn't like typecast */
320 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
321 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
322 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
323 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
325 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
326 GENERATED_GBL_DATA_SIZE)
327 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
329 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
330 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
332 /* Serial Port - controlled on board with jumper J8
336 #define CONFIG_SYS_NS16550_SERIAL
337 #define CONFIG_SYS_NS16550_REG_SIZE 1
338 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
340 #define CONFIG_SYS_BAUDRATE_TABLE \
341 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
343 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
344 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
345 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
346 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
349 #define CONFIG_FSL_DIU_FB
350 #ifdef CONFIG_FSL_DIU_FB
351 #define CONFIG_FSL_DIU_CH7301
352 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
353 #define CONFIG_VIDEO_LOGO
354 #define CONFIG_VIDEO_BMP_LOGO
355 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
357 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
358 * disable empty flash sector detection, which is I/O-intensive.
360 #undef CONFIG_SYS_FLASH_EMPTY_INFO
365 #ifndef CONFIG_DM_I2C
366 #define CONFIG_SYS_I2C
367 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
368 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
369 #define CONFIG_SYS_FSL_I2C2_SPEED 50000
370 #define CONFIG_SYS_FSL_I2C3_SPEED 50000
371 #define CONFIG_SYS_FSL_I2C4_SPEED 50000
372 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
373 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
374 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
375 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
376 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
377 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
378 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
379 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
382 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
384 #define I2C_MUX_PCA_ADDR 0x77
385 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
387 /* I2C bus multiplexer */
388 #define I2C_MUX_CH_DEFAULT 0x8
389 #define I2C_MUX_CH_DIU 0xC
391 /* LDI/DVI Encoder for display */
392 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
393 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
394 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
400 #define CONFIG_RTC_DS3231 1
401 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
404 * eSPI - Enhanced SPI
409 * Memory space is mapped 1-1, but I/O space must start from 0.
413 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
415 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
416 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
417 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
418 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
419 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
420 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
421 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
422 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
425 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
427 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
428 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
429 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
430 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
431 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
432 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
433 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
434 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
437 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
439 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
440 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
441 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
442 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
443 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
444 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
445 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
446 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
449 /* controller 4, Base address 203000 */
451 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
452 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
453 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
454 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
455 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
456 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
457 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
458 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
461 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
462 #endif /* CONFIG_PCI */
465 #define CONFIG_FSL_SATA_V2
466 #ifdef CONFIG_FSL_SATA_V2
467 #define CONFIG_SYS_SATA_MAX_DEVICE 2
469 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
470 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
472 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
473 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
481 #define CONFIG_HAS_FSL_DR_USB
483 #ifdef CONFIG_HAS_FSL_DR_USB
484 #ifdef CONFIG_USB_EHCI_HCD
485 #define CONFIG_USB_EHCI_FSL
486 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
491 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
492 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
496 #ifndef CONFIG_NOBQFMAN
497 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
498 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
499 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
500 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
501 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
502 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
503 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
504 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
505 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
506 CONFIG_SYS_BMAN_CENA_SIZE)
507 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
508 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
509 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
510 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
511 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
512 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
513 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
514 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
515 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
516 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
517 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
518 CONFIG_SYS_QMAN_CENA_SIZE)
519 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
520 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
522 #define CONFIG_SYS_DPAA_FMAN
523 #define CONFIG_SYS_DPAA_PME
525 /* Default address of microcode for the Linux Fman driver */
526 #if defined(CONFIG_SPIFLASH)
528 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
529 * env, so we got 0x110000.
531 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
532 #elif defined(CONFIG_SDCARD)
534 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
535 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
536 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
538 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
539 #elif defined(CONFIG_MTD_RAW_NAND)
540 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
542 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
543 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
545 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
546 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
547 #endif /* CONFIG_NOBQFMAN */
549 #ifdef CONFIG_SYS_DPAA_FMAN
550 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
551 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
552 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
553 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
556 #ifdef CONFIG_FMAN_ENET
557 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
558 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
560 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
561 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
562 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
563 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
565 #define CONFIG_ETHPRIME "FM1@DTSEC1"
568 /* Enable VSC9953 L2 Switch driver */
569 #define CONFIG_VSC9953
570 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
571 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
574 * Dynamic MTD Partition support with mtdparts
580 #define CONFIG_LOADS_ECHO /* echo on for serial download */
581 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
584 * Miscellaneous configurable options
586 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
589 * For booting Linux, the board info and command line data
590 * have to be in the first 64 MB of memory, since this is
591 * the maximum mapped by the Linux kernel during initialization.
593 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
594 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
596 #ifdef CONFIG_CMD_KGDB
597 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
601 * Environment Configuration
603 #define CONFIG_ROOTPATH "/opt/nfsroot"
604 #define CONFIG_BOOTFILE "uImage"
605 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
607 /* default location for tftp and bootm */
608 #define CONFIG_LOADADDR 1000000
610 #define __USB_PHY_TYPE utmi
612 #define CONFIG_EXTRA_ENV_SETTINGS \
613 "hwconfig=fsl_ddr:bank_intlv=auto;" \
614 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
616 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
617 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
618 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
619 "tftpflash=tftpboot $loadaddr $uboot && " \
620 "protect off $ubootaddr +$filesize && " \
621 "erase $ubootaddr +$filesize && " \
622 "cp.b $loadaddr $ubootaddr $filesize && " \
623 "protect on $ubootaddr +$filesize && " \
624 "cmp.b $loadaddr $ubootaddr $filesize\0" \
625 "consoledev=ttyS0\0" \
626 "ramdiskaddr=2000000\0" \
627 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
628 "fdtaddr=1e00000\0" \
629 "fdtfile=t1040qds/t1040qds.dtb\0" \
632 #define CONFIG_LINUX \
633 "setenv bootargs root=/dev/ram rw " \
634 "console=$consoledev,$baudrate $othbootargs;" \
635 "setenv ramdiskaddr 0x02000000;" \
636 "setenv fdtaddr 0x00c00000;" \
637 "setenv loadaddr 0x1000000;" \
638 "bootm $loadaddr $ramdiskaddr $fdtaddr"
640 #define CONFIG_HDBOOT \
641 "setenv bootargs root=/dev/$bdev rw " \
642 "console=$consoledev,$baudrate $othbootargs;" \
643 "tftp $loadaddr $bootfile;" \
644 "tftp $fdtaddr $fdtfile;" \
645 "bootm $loadaddr - $fdtaddr"
647 #define CONFIG_NFSBOOTCOMMAND \
648 "setenv bootargs root=/dev/nfs rw " \
649 "nfsroot=$serverip:$rootpath " \
650 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
651 "console=$consoledev,$baudrate $othbootargs;" \
652 "tftp $loadaddr $bootfile;" \
653 "tftp $fdtaddr $fdtfile;" \
654 "bootm $loadaddr - $fdtaddr"
656 #define CONFIG_RAMBOOTCOMMAND \
657 "setenv bootargs root=/dev/ram rw " \
658 "console=$consoledev,$baudrate $othbootargs;" \
659 "tftp $ramdiskaddr $ramdiskfile;" \
660 "tftp $loadaddr $bootfile;" \
661 "tftp $fdtaddr $fdtfile;" \
662 "bootm $loadaddr $ramdiskaddr $fdtaddr"
664 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
666 #include <asm/fsl_secure_boot.h>
668 #endif /* __CONFIG_H */