include/configs/T102xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_GENERIC_BOARD
  16 #define CONFIG_DISPLAY_BOARDINFO
  17 #define CONFIG_BOOKE
  18 #define CONFIG_E500                     /* BOOKE e500 family */
  19 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  20 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  21 #define CONFIG_MP                       /* support multiple processors */
  22 #define CONFIG_PHYS_64BIT
  23 #define CONFIG_ENABLE_36BIT_PHYS
  24
  25 #ifdef CONFIG_PHYS_64BIT
  26 #define CONFIG_ADDR_MAP         1
  27 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  28 #endif
  29
  30 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  31 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  32 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  33
  34 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  35 #define CONFIG_ENV_OVERWRITE
  36
  37 /* support deep sleep */
  38 #define CONFIG_DEEP_SLEEP
  39 #define CONFIG_SILENT_CONSOLE
  40
  41 #ifdef CONFIG_RAMBOOT_PBL
  42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
  44 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  45 #define CONFIG_SPL_ENV_SUPPORT
  46 #define CONFIG_SPL_SERIAL_SUPPORT
  47 #define CONFIG_SPL_FLUSH_IMAGE
  48 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  49 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  50 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  51 #define CONFIG_SPL_I2C_SUPPORT
  52 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  53 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  54 #define CONFIG_SYS_TEXT_BASE            0x00201000
  55 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  56 #define CONFIG_SPL_PAD_TO               0x40000
  57 #define CONFIG_SPL_MAX_SIZE             0x28000
  58 #define RESET_VECTOR_OFFSET             0x27FFC
  59 #define BOOT_PAGE_OFFSET                0x27000
  60 #ifdef CONFIG_SPL_BUILD
  61 #define CONFIG_SPL_SKIP_RELOCATE
  62 #define CONFIG_SPL_COMMON_INIT_DDR
  63 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  64 #define CONFIG_SYS_NO_FLASH
  65 #endif
  66
  67 #ifdef CONFIG_NAND
  68 #define CONFIG_SPL_NAND_SUPPORT
  69 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  70 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  71 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  72 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  73 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  74 #define CONFIG_SPL_NAND_BOOT
  75 #endif
  76
  77 #ifdef CONFIG_SPIFLASH
  78 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  79 #define CONFIG_SPL_SPI_SUPPORT
  80 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  81 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  86 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  87 #ifndef CONFIG_SPL_BUILD
  88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  89 #endif
  90 #define CONFIG_SPL_SPI_BOOT
  91 #endif
  92
  93 #ifdef CONFIG_SDCARD
  94 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  95 #define CONFIG_SPL_MMC_SUPPORT
  96 #define CONFIG_SPL_MMC_MINIMAL
  97 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  98 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  99 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
 100 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 101 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 102 #ifndef CONFIG_SPL_BUILD
 103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 104 #endif
 105 #define CONFIG_SPL_MMC_BOOT
 106 #endif
 107
 108 #endif /* CONFIG_RAMBOOT_PBL */
 109
 110 #ifndef CONFIG_SYS_TEXT_BASE
 111 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 112 #endif
 113
 114 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 115 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 116 #endif
 117
 118 #ifndef CONFIG_SYS_NO_FLASH
 119 #define CONFIG_FLASH_CFI_DRIVER
 120 #define CONFIG_SYS_FLASH_CFI
 121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 122 #endif
 123
 124 /* PCIe Boot - Master */
 125 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 126 /*
 127  * for slave u-boot IMAGE instored in master memory space,
 128  * PHYS must be aligned based on the SIZE
 129  */
 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 135 #else
 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 138 #endif
 139 /*
 140  * for slave UCODE and ENV instored in master memory space,
 141  * PHYS must be aligned based on the SIZE
 142  */
 143 #ifdef CONFIG_PHYS_64BIT
 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 146 #else
 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 149 #endif
 150 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 151 /* slave core release by master*/
 152 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 153 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 154
 155 /* PCIe Boot - Slave */
 156 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 157 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 159                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 160 /* Set 1M boot space for PCIe boot */
 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 162 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 163                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 164 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 165 #define CONFIG_SYS_NO_FLASH
 166 #endif
 167
 168 #if defined(CONFIG_SPIFLASH)
 169 #define CONFIG_SYS_EXTRA_ENV_RELOC
 170 #define CONFIG_ENV_IS_IN_SPI_FLASH
 171 #define CONFIG_ENV_SPI_BUS              0
 172 #define CONFIG_ENV_SPI_CS               0
 173 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 174 #define CONFIG_ENV_SPI_MODE             0
 175 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 176 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 177 #define CONFIG_ENV_SECT_SIZE            0x10000
 178 #elif defined(CONFIG_SDCARD)
 179 #define CONFIG_SYS_EXTRA_ENV_RELOC
 180 #define CONFIG_ENV_IS_IN_MMC
 181 #define CONFIG_SYS_MMC_ENV_DEV          0
 182 #define CONFIG_ENV_SIZE                 0x2000
 183 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 184 #elif defined(CONFIG_NAND)
 185 #define CONFIG_SYS_EXTRA_ENV_RELOC
 186 #define CONFIG_ENV_IS_IN_NAND
 187 #define CONFIG_ENV_SIZE                 0x2000
 188 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 189 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 190 #define CONFIG_ENV_IS_IN_REMOTE
 191 #define CONFIG_ENV_ADDR         0xffe20000
 192 #define CONFIG_ENV_SIZE         0x2000
 193 #elif defined(CONFIG_ENV_IS_NOWHERE)
 194 #define CONFIG_ENV_SIZE         0x2000
 195 #else
 196 #define CONFIG_ENV_IS_IN_FLASH
 197 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 198 #define CONFIG_ENV_SIZE         0x2000
 199 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 200 #endif
 201
 202
 203 #ifndef __ASSEMBLY__
 204 unsigned long get_board_sys_clk(void);
 205 unsigned long get_board_ddr_clk(void);
 206 #endif
 207
 208 #define CONFIG_SYS_CLK_FREQ     100000000
 209 #define CONFIG_DDR_CLK_FREQ     66660000
 210
 211 /*
 212  * These can be toggled for performance analysis, otherwise use default.
 213  */
 214 #define CONFIG_SYS_CACHE_STASHING
 215 #define CONFIG_BACKSIDE_L2_CACHE
 216 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 217 #define CONFIG_BTB                      /* toggle branch predition */
 218 #define CONFIG_DDR_ECC
 219 #ifdef CONFIG_DDR_ECC
 220 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 221 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 222 #endif
 223
 224 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 225 #define CONFIG_SYS_MEMTEST_END          0x00400000
 226 #define CONFIG_SYS_ALT_MEMTEST
 227 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 228
 229 /*
 230  *  Config the L3 Cache as L3 SRAM
 231  */
 232 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 233 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 234 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 235 #ifdef CONFIG_RAMBOOT_PBL
 236 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 237 #endif
 238 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 239 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 240 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 241 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 242
 243 #ifdef CONFIG_PHYS_64BIT
 244 #define CONFIG_SYS_DCSRBAR              0xf0000000
 245 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 246 #endif
 247
 248 /* EEPROM */
 249 #define CONFIG_ID_EEPROM
 250 #define CONFIG_SYS_I2C_EEPROM_NXID
 251 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 252 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 253 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 256
 257 /*
 258  * DDR Setup
 259  */
 260 #define CONFIG_VERY_BIG_RAM
 261 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 262 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 263 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 264 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 265 #define CONFIG_DDR_SPD
 266 #define CONFIG_SYS_FSL_DDR3
 267
 268 #define CONFIG_SYS_SPD_BUS_NUM  0
 269 #define SPD_EEPROM_ADDRESS      0x51
 270
 271 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 272
 273 /*
 274  * IFC Definitions
 275  */
 276 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 277 #ifdef CONFIG_PHYS_64BIT
 278 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 279 #else
 280 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 281 #endif
 282
 283 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 284 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 285                                 CSPR_PORT_SIZE_16 | \
 286                                 CSPR_MSEL_NOR | \
 287                                 CSPR_V)
 288 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 289
 290 /* NOR Flash Timing Params */
 291 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 292 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 293                                 FTIM0_NOR_TEADC(0x5) | \
 294                                 FTIM0_NOR_TEAHC(0x5))
 295 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 296                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 297                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 298 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 299                                 FTIM2_NOR_TCH(0x4) | \
 300                                 FTIM2_NOR_TWPH(0x0E) | \
 301                                 FTIM2_NOR_TWP(0x1c))
 302 #define CONFIG_SYS_NOR_FTIM3    0x0
 303
 304 #define CONFIG_SYS_FLASH_QUIET_TEST
 305 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 306
 307 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 308 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 309 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 310 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 311
 312 #define CONFIG_SYS_FLASH_EMPTY_INFO
 313 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 314
 315 /* CPLD on IFC */
 316 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 317 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 318 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 319 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 320                                                 | CSPR_PORT_SIZE_8 \
 321                                                 | CSPR_MSEL_GPCM \
 322                                                 | CSPR_V)
 323 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 324 #define CONFIG_SYS_CSOR2                0x0
 325
 326 /* CPLD Timing parameters for IFC CS2 */
 327 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 328                                                 FTIM0_GPCM_TEADC(0x0e) | \
 329                                                 FTIM0_GPCM_TEAHC(0x0e))
 330 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 331                                                 FTIM1_GPCM_TRAD(0x1f))
 332 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 333                                                 FTIM2_GPCM_TCH(0x8) | \
 334                                                 FTIM2_GPCM_TWP(0x1f))
 335 #define CONFIG_SYS_CS2_FTIM3            0x0
 336
 337 /* NAND Flash on IFC */
 338 #define CONFIG_NAND_FSL_IFC
 339 #define CONFIG_SYS_NAND_BASE            0xff800000
 340 #ifdef CONFIG_PHYS_64BIT
 341 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 342 #else
 343 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 344 #endif
 345 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 346 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 347                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 348                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 349                                 | CSPR_V)
 350 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 351
 352 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 353                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 354                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 355                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 356                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 357                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 358                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 359
 360 #define CONFIG_SYS_NAND_ONFI_DETECTION
 361
 362 /* ONFI NAND Flash mode0 Timing Params */
 363 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 364                                         FTIM0_NAND_TWP(0x18)   | \
 365                                         FTIM0_NAND_TWCHT(0x07) | \
 366                                         FTIM0_NAND_TWH(0x0a))
 367 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 368                                         FTIM1_NAND_TWBE(0x39)  | \
 369                                         FTIM1_NAND_TRR(0x0e)   | \
 370                                         FTIM1_NAND_TRP(0x18))
 371 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 372                                         FTIM2_NAND_TREH(0x0a) | \
 373                                         FTIM2_NAND_TWHRE(0x1e))
 374 #define CONFIG_SYS_NAND_FTIM3           0x0
 375
 376 #define CONFIG_SYS_NAND_DDR_LAW         11
 377 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 378 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 379 #define CONFIG_MTD_NAND_VERIFY_WRITE
 380 #define CONFIG_CMD_NAND
 381
 382 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 383
 384 #if defined(CONFIG_NAND)
 385 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 386 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 387 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 388 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 389 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 390 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 391 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 392 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 393 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 394 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 395 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 396 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 397 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 398 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 399 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 400 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 401 #else
 402 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 403 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 404 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 405 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 406 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 407 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 408 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 409 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 410 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 411 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 412 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 413 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 414 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 415 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 416 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 417 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 418 #endif
 419
 420 #ifdef CONFIG_SPL_BUILD
 421 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 422 #else
 423 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 424 #endif
 425
 426 #if defined(CONFIG_RAMBOOT_PBL)
 427 #define CONFIG_SYS_RAMBOOT
 428 #endif
 429
 430 #define CONFIG_BOARD_EARLY_INIT_R
 431 #define CONFIG_MISC_INIT_R
 432
 433 #define CONFIG_HWCONFIG
 434
 435 /* define to use L1 as initial stack */
 436 #define CONFIG_L1_INIT_RAM
 437 #define CONFIG_SYS_INIT_RAM_LOCK
 438 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 439 #ifdef CONFIG_PHYS_64BIT
 440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 442 /* The assembler doesn't like typecast */
 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 444         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 445           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 446 #else
 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe0ec000 /* Initial L1 address */
 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 450 #endif
 451 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 452
 453 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 454                                         GENERATED_GBL_DATA_SIZE)
 455 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 456
 457 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 458 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 459
 460 /* Serial Port */
 461 #define CONFIG_CONS_INDEX       1
 462 #define CONFIG_SYS_NS16550
 463 #define CONFIG_SYS_NS16550_SERIAL
 464 #define CONFIG_SYS_NS16550_REG_SIZE     1
 465 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 466
 467 #define CONFIG_SYS_BAUDRATE_TABLE       \
 468         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 469
 470 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 471 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 472 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 473 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 474 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 475
 476 /* Use the HUSH parser */
 477 #define CONFIG_SYS_HUSH_PARSER
 478 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 479
 480 /* Video */
 481 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 482 #ifdef CONFIG_FSL_DIU_FB
 483 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 484 #define CONFIG_VIDEO
 485 #define CONFIG_CMD_BMP
 486 #define CONFIG_CFB_CONSOLE
 487 #define CONFIG_VIDEO_SW_CURSOR
 488 #define CONFIG_VGA_AS_SINGLE_DEVICE
 489 #define CONFIG_VIDEO_LOGO
 490 #define CONFIG_VIDEO_BMP_LOGO
 491 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 492 /*
 493  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 494  * disable empty flash sector detection, which is I/O-intensive.
 495  */
 496 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 497 #endif
 498
 499 /* pass open firmware flat tree */
 500 #define CONFIG_OF_LIBFDT
 501 #define CONFIG_OF_BOARD_SETUP
 502 #define CONFIG_OF_STDOUT_VIA_ALIAS
 503
 504 /* new uImage format support */
 505 #define CONFIG_FIT
 506 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 507
 508 /* I2C */
 509 #define CONFIG_SYS_I2C
 510 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 511 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 512 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 513 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 514 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 515 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 516 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 517
 518 #define I2C_MUX_PCA_ADDR                0x77
 519 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 520
 521
 522 /* I2C bus multiplexer */
 523 #define I2C_MUX_CH_DEFAULT      0x8
 524
 525 /*
 526  * RTC configuration
 527  */
 528 #define RTC
 529 #define CONFIG_RTC_DS1337       1
 530 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 531
 532 /*
 533  * eSPI - Enhanced SPI
 534  */
 535 #define CONFIG_FSL_ESPI
 536 #define CONFIG_SPI_FLASH
 537 #define CONFIG_SPI_FLASH_STMICRO
 538 #define CONFIG_CMD_SF
 539 #define CONFIG_SPI_FLASH_BAR
 540 #define CONFIG_SF_DEFAULT_SPEED 10000000
 541 #define CONFIG_SF_DEFAULT_MODE  0
 542
 543 /*
 544  * General PCIe
 545  * Memory space is mapped 1-1, but I/O space must start from 0.
 546  */
 547 #define CONFIG_PCI              /* Enable PCI/PCIE */
 548 #define CONFIG_PCIE1            /* PCIE controler 1 */
 549 #define CONFIG_PCIE2            /* PCIE controler 2 */
 550 #define CONFIG_PCIE3            /* PCIE controler 3 */
 551 #ifdef CONFIG_PPC_T1040
 552 #define CONFIG_PCIE4            /* PCIE controler 4 */
 553 #endif
 554 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 555 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 556 #define CONFIG_PCI_INDIRECT_BRIDGE
 557
 558 #ifdef CONFIG_PCI
 559 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 560 #ifdef CONFIG_PCIE1
 561 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 562 #ifdef CONFIG_PHYS_64BIT
 563 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 564 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 565 #else
 566 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 567 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 568 #endif
 569 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 570 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 571 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 572 #ifdef CONFIG_PHYS_64BIT
 573 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 574 #else
 575 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 576 #endif
 577 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 578 #endif
 579
 580 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 581 #ifdef CONFIG_PCIE2
 582 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 583 #ifdef CONFIG_PHYS_64BIT
 584 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 585 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 586 #else
 587 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 588 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 589 #endif
 590 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 591 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 592 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 593 #ifdef CONFIG_PHYS_64BIT
 594 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 595 #else
 596 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 597 #endif
 598 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 599 #endif
 600
 601 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 602 #ifdef CONFIG_PCIE3
 603 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 604 #ifdef CONFIG_PHYS_64BIT
 605 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 606 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 607 #else
 608 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 609 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 610 #endif
 611 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 612 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 613 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 614 #ifdef CONFIG_PHYS_64BIT
 615 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 616 #else
 617 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 618 #endif
 619 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 620 #endif
 621
 622 /* controller 4, Base address 203000, to be removed */
 623 #ifdef CONFIG_PCIE4
 624 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 625 #ifdef CONFIG_PHYS_64BIT
 626 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 627 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 628 #else
 629 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 630 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 631 #endif
 632 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 633 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 634 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 635 #ifdef CONFIG_PHYS_64BIT
 636 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 637 #else
 638 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 639 #endif
 640 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 641 #endif
 642
 643 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 644 #define CONFIG_E1000
 645 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 646 #define CONFIG_DOS_PARTITION
 647 #endif  /* CONFIG_PCI */
 648
 649 /*
 650  * USB
 651  */
 652 #define CONFIG_HAS_FSL_DR_USB
 653
 654 #ifdef CONFIG_HAS_FSL_DR_USB
 655 #define CONFIG_USB_EHCI
 656 #define CONFIG_CMD_USB
 657 #define CONFIG_USB_STORAGE
 658 #define CONFIG_USB_EHCI_FSL
 659 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 660 #define CONFIG_CMD_EXT2
 661 #endif
 662
 663 /*
 664  * SDHC
 665  */
 666 #define CONFIG_MMC
 667 #ifdef CONFIG_MMC
 668 #define CONFIG_FSL_ESDHC
 669 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 670 #define CONFIG_CMD_MMC
 671 #define CONFIG_GENERIC_MMC
 672 #define CONFIG_CMD_EXT2
 673 #define CONFIG_CMD_FAT
 674 #define CONFIG_DOS_PARTITION
 675 #endif
 676
 677 /* Qman/Bman */
 678 #ifndef CONFIG_NOBQFMAN
 679 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 680 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 681 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 682 #ifdef CONFIG_PHYS_64BIT
 683 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 684 #else
 685 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 686 #endif
 687 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 688 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 689 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 690 #ifdef CONFIG_PHYS_64BIT
 691 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 692 #else
 693 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 694 #endif
 695 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 696
 697 #define CONFIG_SYS_DPAA_FMAN
 698
 699 #define CONFIG_QE
 700 #define CONFIG_U_QE
 701 /* Default address of microcode for the Linux FMan driver */
 702 #if defined(CONFIG_SPIFLASH)
 703 /*
 704  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 705  * env, so we got 0x110000.
 706  */
 707 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 708 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 709 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 710 #elif defined(CONFIG_SDCARD)
 711 /*
 712  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 713  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 714  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 715  */
 716 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 717 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 718 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 719 #elif defined(CONFIG_NAND)
 720 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 721 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 722 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 723 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 724 /*
 725  * Slave has no ucode locally, it can fetch this from remote. When implementing
 726  * in two corenet boards, slave's ucode could be stored in master's memory
 727  * space, the address can be mapped from slave TLB->slave LAW->
 728  * slave SRIO or PCIE outbound window->master inbound window->
 729  * master LAW->the ucode address in master's memory space.
 730  */
 731 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 732 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 733 #else
 734 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 735 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 736 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 737 #endif
 738 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 739 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 740 #endif /* CONFIG_NOBQFMAN */
 741
 742 #ifdef CONFIG_SYS_DPAA_FMAN
 743 #define CONFIG_FMAN_ENET
 744 #define CONFIG_PHYLIB_10G
 745 #define CONFIG_PHY_REALTEK
 746 #define RGMII_PHY1_ADDR         0x2
 747 #define RGMII_PHY2_ADDR         0x6
 748 #define FM1_10GEC1_PHY_ADDR     0x1
 749 #endif
 750
 751 #ifdef CONFIG_FMAN_ENET
 752 #define CONFIG_MII              /* MII PHY management */
 753 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 754 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 755 #endif
 756
 757 /*
 758  * Dynamic MTD Partition support with mtdparts
 759  */
 760 #ifndef CONFIG_SYS_NO_FLASH
 761 #define CONFIG_MTD_DEVICE
 762 #define CONFIG_MTD_PARTITIONS
 763 #define CONFIG_CMD_MTDPARTS
 764 #define CONFIG_FLASH_CFI_MTD
 765 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 766                         "spi0=spife110000.1"
 767 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 768                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 769                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
 770                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 771 #endif
 772
 773 /*
 774  * Environment
 775  */
 776 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 777 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 778
 779 /*
 780  * Command line configuration.
 781  */
 782 #include <config_cmd_default.h>
 783
 784 #define CONFIG_CMD_DATE
 785 #define CONFIG_CMD_DHCP
 786 #define CONFIG_CMD_EEPROM
 787 #define CONFIG_CMD_ELF
 788 #define CONFIG_CMD_ERRATA
 789 #define CONFIG_CMD_GREPENV
 790 #define CONFIG_CMD_IRQ
 791 #define CONFIG_CMD_I2C
 792 #define CONFIG_CMD_MII
 793 #define CONFIG_CMD_PING
 794 #define CONFIG_CMD_ECHO
 795 #define CONFIG_CMD_REGINFO
 796 #define CONFIG_CMD_SETEXPR
 797 #define CONFIG_CMD_BDI
 798
 799 #ifdef CONFIG_PCI
 800 #define CONFIG_CMD_PCI
 801 #define CONFIG_CMD_NET
 802 #endif
 803
 804 /*
 805  * Miscellaneous configurable options
 806  */
 807 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 808 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 809 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 810 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 811 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 812 #ifdef CONFIG_CMD_KGDB
 813 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 814 #else
 815 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 816 #endif
 817 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 818 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 819 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 820
 821 /*
 822  * For booting Linux, the board info and command line data
 823  * have to be in the first 64 MB of memory, since this is
 824  * the maximum mapped by the Linux kernel during initialization.
 825  */
 826 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 827 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 828
 829 #ifdef CONFIG_CMD_KGDB
 830 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 831 #endif
 832
 833 /*
 834  * Environment Configuration
 835  */
 836 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 837 #define CONFIG_BOOTFILE         "uImage"
 838 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 839 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 840 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 841 #define CONFIG_BAUDRATE         115200
 842 #define __USB_PHY_TYPE          utmi
 843
 844 #ifdef CONFIG_PPC_T1024
 845 #define CONFIG_BOARDNAME "t1024rdb"
 846 #else
 847 #define CONFIG_BOARDNAME "t1023rdb"
 848 #endif
 849
 850 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 851         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 852         "bank_intlv=cs0_cs1\0"                                  \
 853         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 854         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 855         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 856         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 857         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 858         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 859         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 860         "netdev=eth0\0"                                         \
 861         "tftpflash=tftpboot $loadaddr $uboot && "               \
 862         "protect off $ubootaddr +$filesize && "                 \
 863         "erase $ubootaddr +$filesize && "                       \
 864         "cp.b $loadaddr $ubootaddr $filesize && "               \
 865         "protect on $ubootaddr +$filesize && "                  \
 866         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 867         "consoledev=ttyS0\0"                                    \
 868         "ramdiskaddr=2000000\0"                                 \
 869         "fdtaddr=c00000\0"                                      \
 870         "bdev=sda3\0"
 871
 872 #define CONFIG_LINUX                                    \
 873         "setenv bootargs root=/dev/ram rw "             \
 874         "console=$consoledev,$baudrate $othbootargs;"   \
 875         "setenv ramdiskaddr 0x02000000;"                \
 876         "setenv fdtaddr 0x00c00000;"                    \
 877         "setenv loadaddr 0x1000000;"                    \
 878         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 879
 880
 881 #define CONFIG_NFSBOOTCOMMAND                   \
 882         "setenv bootargs root=/dev/nfs rw "     \
 883         "nfsroot=$serverip:$rootpath "          \
 884         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 885         "console=$consoledev,$baudrate $othbootargs;"   \
 886         "tftp $loadaddr $bootfile;"             \
 887         "tftp $fdtaddr $fdtfile;"               \
 888         "bootm $loadaddr - $fdtaddr"
 889
 890 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 891
 892 #ifdef CONFIG_SECURE_BOOT
 893 #include <asm/fsl_secure_boot.h>
 894 #endif
 895
 896 #endif  /* __T1024RDB_H */