include/configs/T102xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_MP                       /* support multiple processors */
  17 #define CONFIG_ENABLE_36BIT_PHYS
  18
  19 #ifdef CONFIG_PHYS_64BIT
  20 #define CONFIG_ADDR_MAP         1
  21 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  22 #endif
  23
  24 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  25 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  26
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 /* support deep sleep */
  30 #ifdef CONFIG_ARCH_T1024
  31 #define CONFIG_DEEP_SLEEP
  32 #endif
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  36 #define CONFIG_SPL_FLUSH_IMAGE
  37 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  38 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  39 #define CONFIG_SPL_PAD_TO               0x40000
  40 #define CONFIG_SPL_MAX_SIZE             0x28000
  41 #define RESET_VECTOR_OFFSET             0x27FFC
  42 #define BOOT_PAGE_OFFSET                0x27000
  43 #ifdef CONFIG_SPL_BUILD
  44 #define CONFIG_SPL_SKIP_RELOCATE
  45 #define CONFIG_SPL_COMMON_INIT_DDR
  46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  47 #endif
  48
  49 #ifdef CONFIG_NAND
  50 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  51 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  52 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  53 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  54 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  55 #if defined(CONFIG_TARGET_T1024RDB)
  56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  57 #elif defined(CONFIG_TARGET_T1023RDB)
  58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  59 #endif
  60 #define CONFIG_SPL_NAND_BOOT
  61 #endif
  62
  63 #ifdef CONFIG_SPIFLASH
  64 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  65 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  70 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  71 #ifndef CONFIG_SPL_BUILD
  72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  73 #endif
  74 #if defined(CONFIG_TARGET_T1024RDB)
  75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  76 #elif defined(CONFIG_TARGET_T1023RDB)
  77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  78 #endif
  79 #define CONFIG_SPL_SPI_BOOT
  80 #endif
  81
  82 #ifdef CONFIG_SDCARD
  83 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  84 #define CONFIG_SPL_MMC_MINIMAL
  85 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  86 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  87 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  88 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  89 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  90 #ifndef CONFIG_SPL_BUILD
  91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  92 #endif
  93 #if defined(CONFIG_TARGET_T1024RDB)
  94 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  95 #elif defined(CONFIG_TARGET_T1023RDB)
  96 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  97 #endif
  98 #define CONFIG_SPL_MMC_BOOT
  99 #endif
 100
 101 #endif /* CONFIG_RAMBOOT_PBL */
 102
 103 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 104 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 105 #endif
 106
 107 #ifdef CONFIG_MTD_NOR_FLASH
 108 #define CONFIG_FLASH_CFI_DRIVER
 109 #define CONFIG_SYS_FLASH_CFI
 110 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 111 #endif
 112
 113 /* PCIe Boot - Master */
 114 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 115 /*
 116  * for slave u-boot IMAGE instored in master memory space,
 117  * PHYS must be aligned based on the SIZE
 118  */
 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 121 #ifdef CONFIG_PHYS_64BIT
 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 124 #else
 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 126 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 127 #endif
 128 /*
 129  * for slave UCODE and ENV instored in master memory space,
 130  * PHYS must be aligned based on the SIZE
 131  */
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 134 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 135 #else
 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 137 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 138 #endif
 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 140 /* slave core release by master*/
 141 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 142 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 143
 144 /* PCIe Boot - Slave */
 145 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 146 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 147 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 148                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 149 /* Set 1M boot space for PCIe boot */
 150 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 151 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 152                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 153 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 154 #endif
 155
 156 #if defined(CONFIG_SPIFLASH)
 157 #define CONFIG_SYS_EXTRA_ENV_RELOC
 158 #define CONFIG_ENV_SPI_BUS              0
 159 #define CONFIG_ENV_SPI_CS               0
 160 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 161 #define CONFIG_ENV_SPI_MODE             0
 162 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 163 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 164 #if defined(CONFIG_TARGET_T1024RDB)
 165 #define CONFIG_ENV_SECT_SIZE            0x10000
 166 #elif defined(CONFIG_TARGET_T1023RDB)
 167 #define CONFIG_ENV_SECT_SIZE            0x40000
 168 #endif
 169 #elif defined(CONFIG_SDCARD)
 170 #define CONFIG_SYS_EXTRA_ENV_RELOC
 171 #define CONFIG_SYS_MMC_ENV_DEV          0
 172 #define CONFIG_ENV_SIZE                 0x2000
 173 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 174 #elif defined(CONFIG_NAND)
 175 #define CONFIG_SYS_EXTRA_ENV_RELOC
 176 #define CONFIG_ENV_SIZE                 0x2000
 177 #if defined(CONFIG_TARGET_T1024RDB)
 178 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 179 #elif defined(CONFIG_TARGET_T1023RDB)
 180 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 181 #endif
 182 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 183 #define CONFIG_ENV_ADDR         0xffe20000
 184 #define CONFIG_ENV_SIZE         0x2000
 185 #elif defined(CONFIG_ENV_IS_NOWHERE)
 186 #define CONFIG_ENV_SIZE         0x2000
 187 #else
 188 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 189 #define CONFIG_ENV_SIZE         0x2000
 190 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 191 #endif
 192
 193 #ifndef __ASSEMBLY__
 194 unsigned long get_board_sys_clk(void);
 195 unsigned long get_board_ddr_clk(void);
 196 #endif
 197
 198 #define CONFIG_SYS_CLK_FREQ     100000000
 199 #define CONFIG_DDR_CLK_FREQ     100000000
 200
 201 /*
 202  * These can be toggled for performance analysis, otherwise use default.
 203  */
 204 #define CONFIG_SYS_CACHE_STASHING
 205 #define CONFIG_BACKSIDE_L2_CACHE
 206 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 207 #define CONFIG_BTB                      /* toggle branch predition */
 208 #define CONFIG_DDR_ECC
 209 #ifdef CONFIG_DDR_ECC
 210 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 211 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 212 #endif
 213
 214 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 215 #define CONFIG_SYS_MEMTEST_END          0x00400000
 216 #define CONFIG_SYS_ALT_MEMTEST
 217
 218 /*
 219  *  Config the L3 Cache as L3 SRAM
 220  */
 221 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 222 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 223 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 224 #ifdef CONFIG_RAMBOOT_PBL
 225 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 226 #endif
 227 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 228 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 229 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 230 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 231
 232 #ifdef CONFIG_PHYS_64BIT
 233 #define CONFIG_SYS_DCSRBAR              0xf0000000
 234 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 235 #endif
 236
 237 /* EEPROM */
 238 #define CONFIG_ID_EEPROM
 239 #define CONFIG_SYS_I2C_EEPROM_NXID
 240 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 242 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 245
 246 /*
 247  * DDR Setup
 248  */
 249 #define CONFIG_VERY_BIG_RAM
 250 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 251 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 252 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 253 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 254 #define CONFIG_FSL_DDR_INTERACTIVE
 255 #if defined(CONFIG_TARGET_T1024RDB)
 256 #define CONFIG_DDR_SPD
 257 #define CONFIG_SYS_SPD_BUS_NUM  0
 258 #define SPD_EEPROM_ADDRESS      0x51
 259 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 260 #elif defined(CONFIG_TARGET_T1023RDB)
 261 #define CONFIG_SYS_DDR_RAW_TIMING
 262 #define CONFIG_SYS_SDRAM_SIZE   2048
 263 #endif
 264
 265 /*
 266  * IFC Definitions
 267  */
 268 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 269 #ifdef CONFIG_PHYS_64BIT
 270 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 271 #else
 272 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 273 #endif
 274
 275 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 276 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 277                                 CSPR_PORT_SIZE_16 | \
 278                                 CSPR_MSEL_NOR | \
 279                                 CSPR_V)
 280 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 281
 282 /* NOR Flash Timing Params */
 283 #if defined(CONFIG_TARGET_T1024RDB)
 284 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 285 #elif defined(CONFIG_TARGET_T1023RDB)
 286 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 287                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 288 #endif
 289 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 290                                 FTIM0_NOR_TEADC(0x5) | \
 291                                 FTIM0_NOR_TEAHC(0x5))
 292 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 293                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 294                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 295 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 296                                 FTIM2_NOR_TCH(0x4) | \
 297                                 FTIM2_NOR_TWPH(0x0E) | \
 298                                 FTIM2_NOR_TWP(0x1c))
 299 #define CONFIG_SYS_NOR_FTIM3    0x0
 300
 301 #define CONFIG_SYS_FLASH_QUIET_TEST
 302 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 303
 304 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 305 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 306 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 307 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 308
 309 #define CONFIG_SYS_FLASH_EMPTY_INFO
 310 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 311
 312 #ifdef CONFIG_TARGET_T1024RDB
 313 /* CPLD on IFC */
 314 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 315 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 316 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 317 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 318                                                 | CSPR_PORT_SIZE_8 \
 319                                                 | CSPR_MSEL_GPCM \
 320                                                 | CSPR_V)
 321 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 322 #define CONFIG_SYS_CSOR2                0x0
 323
 324 /* CPLD Timing parameters for IFC CS2 */
 325 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 326                                                 FTIM0_GPCM_TEADC(0x0e) | \
 327                                                 FTIM0_GPCM_TEAHC(0x0e))
 328 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 329                                                 FTIM1_GPCM_TRAD(0x1f))
 330 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 331                                                 FTIM2_GPCM_TCH(0x8) | \
 332                                                 FTIM2_GPCM_TWP(0x1f))
 333 #define CONFIG_SYS_CS2_FTIM3            0x0
 334 #endif
 335
 336 /* NAND Flash on IFC */
 337 #define CONFIG_NAND_FSL_IFC
 338 #define CONFIG_SYS_NAND_BASE            0xff800000
 339 #ifdef CONFIG_PHYS_64BIT
 340 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 341 #else
 342 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 343 #endif
 344 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 345 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 346                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 347                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 348                                 | CSPR_V)
 349 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 350
 351 #if defined(CONFIG_TARGET_T1024RDB)
 352 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 353                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 354                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 355                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 356                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 357                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 358                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 359 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 360 #elif defined(CONFIG_TARGET_T1023RDB)
 361 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 362                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 363                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 364                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 365                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 366                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 367                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 368 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 369 #endif
 370
 371 #define CONFIG_SYS_NAND_ONFI_DETECTION
 372 /* ONFI NAND Flash mode0 Timing Params */
 373 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 374                                         FTIM0_NAND_TWP(0x18)   | \
 375                                         FTIM0_NAND_TWCHT(0x07) | \
 376                                         FTIM0_NAND_TWH(0x0a))
 377 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 378                                         FTIM1_NAND_TWBE(0x39)  | \
 379                                         FTIM1_NAND_TRR(0x0e)   | \
 380                                         FTIM1_NAND_TRP(0x18))
 381 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 382                                         FTIM2_NAND_TREH(0x0a) | \
 383                                         FTIM2_NAND_TWHRE(0x1e))
 384 #define CONFIG_SYS_NAND_FTIM3           0x0
 385
 386 #define CONFIG_SYS_NAND_DDR_LAW         11
 387 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 388 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 389
 390 #if defined(CONFIG_NAND)
 391 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 392 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 393 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 394 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 395 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 396 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 397 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 398 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 399 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 400 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 401 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 402 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 403 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 404 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 405 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 406 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 407 #else
 408 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 409 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 410 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 411 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 412 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 413 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 414 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 415 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 416 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 417 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 418 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 419 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 420 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 421 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 422 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 423 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 424 #endif
 425
 426 #ifdef CONFIG_SPL_BUILD
 427 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 428 #else
 429 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 430 #endif
 431
 432 #if defined(CONFIG_RAMBOOT_PBL)
 433 #define CONFIG_SYS_RAMBOOT
 434 #endif
 435
 436 #define CONFIG_BOARD_EARLY_INIT_R
 437 #define CONFIG_MISC_INIT_R
 438
 439 #define CONFIG_HWCONFIG
 440
 441 /* define to use L1 as initial stack */
 442 #define CONFIG_L1_INIT_RAM
 443 #define CONFIG_SYS_INIT_RAM_LOCK
 444 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 445 #ifdef CONFIG_PHYS_64BIT
 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 448 /* The assembler doesn't like typecast */
 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 450         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 451           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 452 #else
 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 456 #endif
 457 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 458
 459 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 460                                         GENERATED_GBL_DATA_SIZE)
 461 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 462
 463 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 464 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 465
 466 /* Serial Port */
 467 #define CONFIG_CONS_INDEX       1
 468 #define CONFIG_SYS_NS16550_SERIAL
 469 #define CONFIG_SYS_NS16550_REG_SIZE     1
 470 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 471
 472 #define CONFIG_SYS_BAUDRATE_TABLE       \
 473         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 474
 475 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 476 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 477 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 478 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 479
 480 /* Video */
 481 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 482 #ifdef CONFIG_FSL_DIU_FB
 483 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 484 #define CONFIG_VIDEO_LOGO
 485 #define CONFIG_VIDEO_BMP_LOGO
 486 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 487 /*
 488  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 489  * disable empty flash sector detection, which is I/O-intensive.
 490  */
 491 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 492 #endif
 493
 494 /* I2C */
 495 #define CONFIG_SYS_I2C
 496 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 497 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 498 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 499 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 500 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 501 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 502 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 503
 504 #define I2C_PCA6408_BUS_NUM             1
 505 #define I2C_PCA6408_ADDR                0x20
 506
 507 /* I2C bus multiplexer */
 508 #define I2C_MUX_CH_DEFAULT      0x8
 509
 510 /*
 511  * RTC configuration
 512  */
 513 #define RTC
 514 #define CONFIG_RTC_DS1337       1
 515 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 516
 517 /*
 518  * eSPI - Enhanced SPI
 519  */
 520 #define CONFIG_SPI_FLASH_BAR
 521 #define CONFIG_SF_DEFAULT_SPEED 10000000
 522 #define CONFIG_SF_DEFAULT_MODE  0
 523
 524 /*
 525  * General PCIe
 526  * Memory space is mapped 1-1, but I/O space must start from 0.
 527  */
 528 #define CONFIG_PCIE1            /* PCIE controller 1 */
 529 #define CONFIG_PCIE2            /* PCIE controller 2 */
 530 #define CONFIG_PCIE3            /* PCIE controller 3 */
 531 #ifdef CONFIG_ARCH_T1040
 532 #define CONFIG_PCIE4            /* PCIE controller 4 */
 533 #endif
 534 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 535 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 536 #define CONFIG_PCI_INDIRECT_BRIDGE
 537
 538 #ifdef CONFIG_PCI
 539 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 540 #ifdef CONFIG_PCIE1
 541 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 542 #ifdef CONFIG_PHYS_64BIT
 543 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 544 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 545 #else
 546 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 547 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 548 #endif
 549 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 550 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 551 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 552 #ifdef CONFIG_PHYS_64BIT
 553 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 554 #else
 555 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 556 #endif
 557 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 558 #endif
 559
 560 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 561 #ifdef CONFIG_PCIE2
 562 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 563 #ifdef CONFIG_PHYS_64BIT
 564 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 565 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 566 #else
 567 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 568 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 569 #endif
 570 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 571 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 572 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 573 #ifdef CONFIG_PHYS_64BIT
 574 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 575 #else
 576 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 577 #endif
 578 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 579 #endif
 580
 581 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 582 #ifdef CONFIG_PCIE3
 583 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 584 #ifdef CONFIG_PHYS_64BIT
 585 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 586 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 587 #else
 588 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 589 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 590 #endif
 591 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 592 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 593 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 594 #ifdef CONFIG_PHYS_64BIT
 595 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 596 #else
 597 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 598 #endif
 599 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 600 #endif
 601
 602 /* controller 4, Base address 203000, to be removed */
 603 #ifdef CONFIG_PCIE4
 604 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 605 #ifdef CONFIG_PHYS_64BIT
 606 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 607 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 608 #else
 609 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 610 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 611 #endif
 612 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 613 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 614 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 615 #ifdef CONFIG_PHYS_64BIT
 616 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 617 #else
 618 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 619 #endif
 620 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 621 #endif
 622
 623 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 624 #endif  /* CONFIG_PCI */
 625
 626 /*
 627  * USB
 628  */
 629 #define CONFIG_HAS_FSL_DR_USB
 630
 631 #ifdef CONFIG_HAS_FSL_DR_USB
 632 #define CONFIG_USB_EHCI_FSL
 633 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 634 #endif
 635
 636 /*
 637  * SDHC
 638  */
 639 #ifdef CONFIG_MMC
 640 #define CONFIG_FSL_ESDHC
 641 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 642 #endif
 643
 644 /* Qman/Bman */
 645 #ifndef CONFIG_NOBQFMAN
 646 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 647 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 648 #ifdef CONFIG_PHYS_64BIT
 649 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 650 #else
 651 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 652 #endif
 653 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 654 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 655 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 656 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 657 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 658 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 659                                         CONFIG_SYS_BMAN_CENA_SIZE)
 660 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 661 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 662 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 663 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 664 #ifdef CONFIG_PHYS_64BIT
 665 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 666 #else
 667 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 668 #endif
 669 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 670 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 671 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 672 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 673 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 674 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 675                                         CONFIG_SYS_QMAN_CENA_SIZE)
 676 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 677 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 678
 679 #define CONFIG_SYS_DPAA_FMAN
 680
 681 #ifdef CONFIG_TARGET_T1024RDB
 682 #define CONFIG_QE
 683 #define CONFIG_U_QE
 684 #endif
 685 /* Default address of microcode for the Linux FMan driver */
 686 #if defined(CONFIG_SPIFLASH)
 687 /*
 688  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 689  * env, so we got 0x110000.
 690  */
 691 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 692 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 693 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 694 #elif defined(CONFIG_SDCARD)
 695 /*
 696  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 697  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 698  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 699  */
 700 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 701 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 702 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 703 #elif defined(CONFIG_NAND)
 704 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 705 #if defined(CONFIG_TARGET_T1024RDB)
 706 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 707 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 708 #elif defined(CONFIG_TARGET_T1023RDB)
 709 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 710 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 711 #endif
 712 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 713 /*
 714  * Slave has no ucode locally, it can fetch this from remote. When implementing
 715  * in two corenet boards, slave's ucode could be stored in master's memory
 716  * space, the address can be mapped from slave TLB->slave LAW->
 717  * slave SRIO or PCIE outbound window->master inbound window->
 718  * master LAW->the ucode address in master's memory space.
 719  */
 720 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 721 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 722 #else
 723 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 724 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 725 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 726 #endif
 727 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 728 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 729 #endif /* CONFIG_NOBQFMAN */
 730
 731 #ifdef CONFIG_SYS_DPAA_FMAN
 732 #define CONFIG_FMAN_ENET
 733 #define CONFIG_PHYLIB_10G
 734 #define CONFIG_PHY_REALTEK
 735 #define CONFIG_PHY_AQUANTIA
 736 #if defined(CONFIG_TARGET_T1024RDB)
 737 #define RGMII_PHY1_ADDR         0x2
 738 #define RGMII_PHY2_ADDR         0x6
 739 #define SGMII_AQR_PHY_ADDR      0x2
 740 #define FM1_10GEC1_PHY_ADDR     0x1
 741 #elif defined(CONFIG_TARGET_T1023RDB)
 742 #define RGMII_PHY1_ADDR         0x1
 743 #define SGMII_RTK_PHY_ADDR      0x3
 744 #define SGMII_AQR_PHY_ADDR      0x2
 745 #endif
 746 #endif
 747
 748 #ifdef CONFIG_FMAN_ENET
 749 #define CONFIG_MII              /* MII PHY management */
 750 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 751 #endif
 752
 753 /*
 754  * Dynamic MTD Partition support with mtdparts
 755  */
 756 #ifdef CONFIG_MTD_NOR_FLASH
 757 #define CONFIG_MTD_DEVICE
 758 #define CONFIG_MTD_PARTITIONS
 759 #define CONFIG_FLASH_CFI_MTD
 760 #endif
 761
 762 /*
 763  * Environment
 764  */
 765 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 766 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 767
 768 /*
 769  * Miscellaneous configurable options
 770  */
 771 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 772 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 773 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 774 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 775
 776 /*
 777  * For booting Linux, the board info and command line data
 778  * have to be in the first 64 MB of memory, since this is
 779  * the maximum mapped by the Linux kernel during initialization.
 780  */
 781 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 782 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 783
 784 #ifdef CONFIG_CMD_KGDB
 785 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 786 #endif
 787
 788 /*
 789  * Environment Configuration
 790  */
 791 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 792 #define CONFIG_BOOTFILE         "uImage"
 793 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 794 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 795 #define __USB_PHY_TYPE          utmi
 796
 797 #ifdef CONFIG_ARCH_T1024
 798 #define CONFIG_BOARDNAME t1024rdb
 799 #define BANK_INTLV cs0_cs1
 800 #else
 801 #define CONFIG_BOARDNAME t1023rdb
 802 #define BANK_INTLV  null
 803 #endif
 804
 805 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 806         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 807         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 808         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 809         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 810         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 811         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 812         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 813         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 814         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 815         "netdev=eth0\0"                                         \
 816         "tftpflash=tftpboot $loadaddr $uboot && "               \
 817         "protect off $ubootaddr +$filesize && "                 \
 818         "erase $ubootaddr +$filesize && "                       \
 819         "cp.b $loadaddr $ubootaddr $filesize && "               \
 820         "protect on $ubootaddr +$filesize && "                  \
 821         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 822         "consoledev=ttyS0\0"                                    \
 823         "ramdiskaddr=2000000\0"                                 \
 824         "fdtaddr=1e00000\0"                                     \
 825         "bdev=sda3\0"
 826
 827 #define CONFIG_LINUX                                    \
 828         "setenv bootargs root=/dev/ram rw "             \
 829         "console=$consoledev,$baudrate $othbootargs;"   \
 830         "setenv ramdiskaddr 0x02000000;"                \
 831         "setenv fdtaddr 0x00c00000;"                    \
 832         "setenv loadaddr 0x1000000;"                    \
 833         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 834
 835 #define CONFIG_NFSBOOTCOMMAND                   \
 836         "setenv bootargs root=/dev/nfs rw "     \
 837         "nfsroot=$serverip:$rootpath "          \
 838         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 839         "console=$consoledev,$baudrate $othbootargs;"   \
 840         "tftp $loadaddr $bootfile;"             \
 841         "tftp $fdtaddr $fdtfile;"               \
 842         "bootm $loadaddr - $fdtaddr"
 843
 844 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 845
 846 #include <asm/fsl_secure_boot.h>
 847
 848 #endif  /* __T1024RDB_H */