include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 RDB board configuration file
   8  */
   9
  10 #ifndef __T1024RDB_H
  11 #define __T1024RDB_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 /* support deep sleep */
  28 #ifdef CONFIG_ARCH_T1024
  29 #define CONFIG_DEEP_SLEEP
  30 #endif
  31
  32 #ifdef CONFIG_RAMBOOT_PBL
  33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_PAD_TO               0x40000
  36 #define CONFIG_SPL_MAX_SIZE             0x28000
  37 #define RESET_VECTOR_OFFSET             0x27FFC
  38 #define BOOT_PAGE_OFFSET                0x27000
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_SKIP_RELOCATE
  41 #define CONFIG_SPL_COMMON_INIT_DDR
  42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  43 #endif
  44
  45 #ifdef CONFIG_NAND
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  47 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  48 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  50 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  51 #if defined(CONFIG_TARGET_T1024RDB)
  52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  53 #elif defined(CONFIG_TARGET_T1023RDB)
  54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  55 #endif
  56 #endif
  57
  58 #ifdef CONFIG_SPIFLASH
  59 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  60 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  65 #ifndef CONFIG_SPL_BUILD
  66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67 #endif
  68 #if defined(CONFIG_TARGET_T1024RDB)
  69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  70 #elif defined(CONFIG_TARGET_T1023RDB)
  71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  72 #endif
  73 #endif
  74
  75 #ifdef CONFIG_SDCARD
  76 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  77 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  78 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  79 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  80 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  81 #ifndef CONFIG_SPL_BUILD
  82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83 #endif
  84 #if defined(CONFIG_TARGET_T1024RDB)
  85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  86 #elif defined(CONFIG_TARGET_T1023RDB)
  87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  88 #endif
  89 #endif
  90
  91 #endif /* CONFIG_RAMBOOT_PBL */
  92
  93 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  94 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  95 #endif
  96
  97 /* PCIe Boot - Master */
  98 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  99 /*
 100  * for slave u-boot IMAGE instored in master memory space,
 101  * PHYS must be aligned based on the SIZE
 102  */
 103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 105 #ifdef CONFIG_PHYS_64BIT
 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 108 #else
 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 111 #endif
 112 /*
 113  * for slave UCODE and ENV instored in master memory space,
 114  * PHYS must be aligned based on the SIZE
 115  */
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 119 #else
 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 121 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 122 #endif
 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 124 /* slave core release by master*/
 125 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 126 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 127
 128 /* PCIe Boot - Slave */
 129 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 131 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 132                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 133 /* Set 1M boot space for PCIe boot */
 134 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 135 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 136                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 137 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 138 #endif
 139
 140 #if defined(CONFIG_SPIFLASH)
 141 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 142 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 143 #if defined(CONFIG_TARGET_T1024RDB)
 144 #define CONFIG_ENV_SECT_SIZE            0x10000
 145 #elif defined(CONFIG_TARGET_T1023RDB)
 146 #define CONFIG_ENV_SECT_SIZE            0x40000
 147 #endif
 148 #elif defined(CONFIG_SDCARD)
 149 #define CONFIG_SYS_MMC_ENV_DEV          0
 150 #define CONFIG_ENV_SIZE                 0x2000
 151 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 152 #elif defined(CONFIG_NAND)
 153 #define CONFIG_ENV_SIZE                 0x2000
 154 #if defined(CONFIG_TARGET_T1024RDB)
 155 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 156 #elif defined(CONFIG_TARGET_T1023RDB)
 157 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 158 #endif
 159 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 160 #define CONFIG_ENV_ADDR         0xffe20000
 161 #define CONFIG_ENV_SIZE         0x2000
 162 #elif defined(CONFIG_ENV_IS_NOWHERE)
 163 #define CONFIG_ENV_SIZE         0x2000
 164 #else
 165 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 166 #define CONFIG_ENV_SIZE         0x2000
 167 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 168 #endif
 169
 170 #ifndef __ASSEMBLY__
 171 unsigned long get_board_sys_clk(void);
 172 unsigned long get_board_ddr_clk(void);
 173 #endif
 174
 175 #define CONFIG_SYS_CLK_FREQ     100000000
 176 #define CONFIG_DDR_CLK_FREQ     100000000
 177
 178 /*
 179  * These can be toggled for performance analysis, otherwise use default.
 180  */
 181 #define CONFIG_SYS_CACHE_STASHING
 182 #define CONFIG_BACKSIDE_L2_CACHE
 183 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 184 #define CONFIG_BTB                      /* toggle branch predition */
 185 #define CONFIG_DDR_ECC
 186 #ifdef CONFIG_DDR_ECC
 187 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 188 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 189 #endif
 190
 191 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 192 #define CONFIG_SYS_MEMTEST_END          0x00400000
 193
 194 /*
 195  *  Config the L3 Cache as L3 SRAM
 196  */
 197 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 198 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 199 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 200 #ifdef CONFIG_RAMBOOT_PBL
 201 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 202 #endif
 203 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 204 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 205 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 206
 207 #ifdef CONFIG_PHYS_64BIT
 208 #define CONFIG_SYS_DCSRBAR              0xf0000000
 209 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 210 #endif
 211
 212 /* EEPROM */
 213 #define CONFIG_ID_EEPROM
 214 #define CONFIG_SYS_I2C_EEPROM_NXID
 215 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 216 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 220
 221 /*
 222  * DDR Setup
 223  */
 224 #define CONFIG_VERY_BIG_RAM
 225 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 226 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 227 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 228 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 229 #if defined(CONFIG_TARGET_T1024RDB)
 230 #define CONFIG_DDR_SPD
 231 #define CONFIG_SYS_SPD_BUS_NUM  0
 232 #define SPD_EEPROM_ADDRESS      0x51
 233 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 234 #elif defined(CONFIG_TARGET_T1023RDB)
 235 #define CONFIG_SYS_DDR_RAW_TIMING
 236 #define CONFIG_SYS_SDRAM_SIZE   2048
 237 #endif
 238
 239 /*
 240  * IFC Definitions
 241  */
 242 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 243 #ifdef CONFIG_PHYS_64BIT
 244 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 245 #else
 246 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 247 #endif
 248
 249 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 250 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 251                                 CSPR_PORT_SIZE_16 | \
 252                                 CSPR_MSEL_NOR | \
 253                                 CSPR_V)
 254 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 255
 256 /* NOR Flash Timing Params */
 257 #if defined(CONFIG_TARGET_T1024RDB)
 258 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 259 #elif defined(CONFIG_TARGET_T1023RDB)
 260 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 261                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 262 #endif
 263 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 264                                 FTIM0_NOR_TEADC(0x5) | \
 265                                 FTIM0_NOR_TEAHC(0x5))
 266 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 267                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 268                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 269 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 270                                 FTIM2_NOR_TCH(0x4) | \
 271                                 FTIM2_NOR_TWPH(0x0E) | \
 272                                 FTIM2_NOR_TWP(0x1c))
 273 #define CONFIG_SYS_NOR_FTIM3    0x0
 274
 275 #define CONFIG_SYS_FLASH_QUIET_TEST
 276 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 277
 278 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 279 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 280 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 281 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 282
 283 #define CONFIG_SYS_FLASH_EMPTY_INFO
 284 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 285
 286 #ifdef CONFIG_TARGET_T1024RDB
 287 /* CPLD on IFC */
 288 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 289 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 290 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 291 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 292                                                 | CSPR_PORT_SIZE_8 \
 293                                                 | CSPR_MSEL_GPCM \
 294                                                 | CSPR_V)
 295 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 296 #define CONFIG_SYS_CSOR2                0x0
 297
 298 /* CPLD Timing parameters for IFC CS2 */
 299 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 300                                                 FTIM0_GPCM_TEADC(0x0e) | \
 301                                                 FTIM0_GPCM_TEAHC(0x0e))
 302 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 303                                                 FTIM1_GPCM_TRAD(0x1f))
 304 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 305                                                 FTIM2_GPCM_TCH(0x8) | \
 306                                                 FTIM2_GPCM_TWP(0x1f))
 307 #define CONFIG_SYS_CS2_FTIM3            0x0
 308 #endif
 309
 310 /* NAND Flash on IFC */
 311 #define CONFIG_NAND_FSL_IFC
 312 #define CONFIG_SYS_NAND_BASE            0xff800000
 313 #ifdef CONFIG_PHYS_64BIT
 314 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 315 #else
 316 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 317 #endif
 318 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 319 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 320                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 321                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 322                                 | CSPR_V)
 323 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 324
 325 #if defined(CONFIG_TARGET_T1024RDB)
 326 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 327                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 328                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 329                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 330                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 331                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 332                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 333 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 334 #elif defined(CONFIG_TARGET_T1023RDB)
 335 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 336                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 337                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 338                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 339                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 340                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 341                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 342 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 343 #endif
 344
 345 #define CONFIG_SYS_NAND_ONFI_DETECTION
 346 /* ONFI NAND Flash mode0 Timing Params */
 347 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 348                                         FTIM0_NAND_TWP(0x18)   | \
 349                                         FTIM0_NAND_TWCHT(0x07) | \
 350                                         FTIM0_NAND_TWH(0x0a))
 351 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 352                                         FTIM1_NAND_TWBE(0x39)  | \
 353                                         FTIM1_NAND_TRR(0x0e)   | \
 354                                         FTIM1_NAND_TRP(0x18))
 355 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 356                                         FTIM2_NAND_TREH(0x0a) | \
 357                                         FTIM2_NAND_TWHRE(0x1e))
 358 #define CONFIG_SYS_NAND_FTIM3           0x0
 359
 360 #define CONFIG_SYS_NAND_DDR_LAW         11
 361 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 362 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 363
 364 #if defined(CONFIG_NAND)
 365 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 366 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 367 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 368 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 369 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 370 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 371 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 372 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 373 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 374 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 375 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 376 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 377 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 378 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 379 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 380 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 381 #else
 382 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 383 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 384 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 385 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 386 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 387 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 388 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 389 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 390 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 391 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 392 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 393 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 394 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 395 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 396 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 397 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 398 #endif
 399
 400 #ifdef CONFIG_SPL_BUILD
 401 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 402 #else
 403 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 404 #endif
 405
 406 #if defined(CONFIG_RAMBOOT_PBL)
 407 #define CONFIG_SYS_RAMBOOT
 408 #endif
 409
 410 #define CONFIG_HWCONFIG
 411
 412 /* define to use L1 as initial stack */
 413 #define CONFIG_L1_INIT_RAM
 414 #define CONFIG_SYS_INIT_RAM_LOCK
 415 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 416 #ifdef CONFIG_PHYS_64BIT
 417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 419 /* The assembler doesn't like typecast */
 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 421         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 422           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 423 #else
 424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 427 #endif
 428 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 429
 430 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 431                                         GENERATED_GBL_DATA_SIZE)
 432 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 433
 434 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 435 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 436
 437 /* Serial Port */
 438 #define CONFIG_SYS_NS16550_SERIAL
 439 #define CONFIG_SYS_NS16550_REG_SIZE     1
 440 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 441
 442 #define CONFIG_SYS_BAUDRATE_TABLE       \
 443         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 444
 445 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 446 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 447 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 448 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 449
 450 /* Video */
 451 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 452 #ifdef CONFIG_FSL_DIU_FB
 453 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 454 #define CONFIG_VIDEO_LOGO
 455 #define CONFIG_VIDEO_BMP_LOGO
 456 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 457 /*
 458  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 459  * disable empty flash sector detection, which is I/O-intensive.
 460  */
 461 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 462 #endif
 463
 464 /* I2C */
 465 #define CONFIG_SYS_I2C
 466 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 467 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 468 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 469 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 470 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 471 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 472 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 473
 474 #define I2C_PCA6408_BUS_NUM             1
 475 #define I2C_PCA6408_ADDR                0x20
 476
 477 /* I2C bus multiplexer */
 478 #define I2C_MUX_CH_DEFAULT      0x8
 479
 480 /*
 481  * RTC configuration
 482  */
 483 #define RTC
 484 #define CONFIG_RTC_DS1337       1
 485 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 486
 487 /*
 488  * eSPI - Enhanced SPI
 489  */
 490
 491 /*
 492  * General PCIe
 493  * Memory space is mapped 1-1, but I/O space must start from 0.
 494  */
 495 #define CONFIG_PCIE1            /* PCIE controller 1 */
 496 #define CONFIG_PCIE2            /* PCIE controller 2 */
 497 #define CONFIG_PCIE3            /* PCIE controller 3 */
 498 #ifdef CONFIG_ARCH_T1040
 499 #define CONFIG_PCIE4            /* PCIE controller 4 */
 500 #endif
 501 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 502 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 503 #define CONFIG_PCI_INDIRECT_BRIDGE
 504
 505 #ifdef CONFIG_PCI
 506 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 507 #ifdef CONFIG_PCIE1
 508 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 509 #ifdef CONFIG_PHYS_64BIT
 510 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 511 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 512 #else
 513 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 514 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 515 #endif
 516 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 517 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 518 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 519 #ifdef CONFIG_PHYS_64BIT
 520 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 521 #else
 522 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 523 #endif
 524 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 525 #endif
 526
 527 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 528 #ifdef CONFIG_PCIE2
 529 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 530 #ifdef CONFIG_PHYS_64BIT
 531 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 532 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 533 #else
 534 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 535 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 536 #endif
 537 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 538 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 539 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 540 #ifdef CONFIG_PHYS_64BIT
 541 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 542 #else
 543 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 544 #endif
 545 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 546 #endif
 547
 548 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 549 #ifdef CONFIG_PCIE3
 550 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 551 #ifdef CONFIG_PHYS_64BIT
 552 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 553 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 554 #else
 555 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 556 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 557 #endif
 558 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 559 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 560 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 561 #ifdef CONFIG_PHYS_64BIT
 562 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 563 #else
 564 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 565 #endif
 566 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 567 #endif
 568
 569 /* controller 4, Base address 203000, to be removed */
 570 #ifdef CONFIG_PCIE4
 571 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 572 #ifdef CONFIG_PHYS_64BIT
 573 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 574 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 575 #else
 576 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 577 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 578 #endif
 579 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 580 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 581 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 582 #ifdef CONFIG_PHYS_64BIT
 583 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 584 #else
 585 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 586 #endif
 587 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 588 #endif
 589
 590 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 591 #endif  /* CONFIG_PCI */
 592
 593 /*
 594  * USB
 595  */
 596 #define CONFIG_HAS_FSL_DR_USB
 597
 598 #ifdef CONFIG_HAS_FSL_DR_USB
 599 #define CONFIG_USB_EHCI_FSL
 600 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 601 #endif
 602
 603 /*
 604  * SDHC
 605  */
 606 #ifdef CONFIG_MMC
 607 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 608 #endif
 609
 610 /* Qman/Bman */
 611 #ifndef CONFIG_NOBQFMAN
 612 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 613 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 614 #ifdef CONFIG_PHYS_64BIT
 615 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 616 #else
 617 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 618 #endif
 619 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 620 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 621 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 622 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 623 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 624 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 625                                         CONFIG_SYS_BMAN_CENA_SIZE)
 626 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 627 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 628 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 629 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 630 #ifdef CONFIG_PHYS_64BIT
 631 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 632 #else
 633 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 634 #endif
 635 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 636 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 637 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 638 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 639 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 640 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 641                                         CONFIG_SYS_QMAN_CENA_SIZE)
 642 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 643 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 644
 645 #define CONFIG_SYS_DPAA_FMAN
 646
 647 /* Default address of microcode for the Linux FMan driver */
 648 #if defined(CONFIG_SPIFLASH)
 649 /*
 650  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 651  * env, so we got 0x110000.
 652  */
 653 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 654 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 655 #elif defined(CONFIG_SDCARD)
 656 /*
 657  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 658  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 659  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 660  */
 661 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 662 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 663 #elif defined(CONFIG_NAND)
 664 #if defined(CONFIG_TARGET_T1024RDB)
 665 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 666 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 667 #elif defined(CONFIG_TARGET_T1023RDB)
 668 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 669 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 670 #endif
 671 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 672 /*
 673  * Slave has no ucode locally, it can fetch this from remote. When implementing
 674  * in two corenet boards, slave's ucode could be stored in master's memory
 675  * space, the address can be mapped from slave TLB->slave LAW->
 676  * slave SRIO or PCIE outbound window->master inbound window->
 677  * master LAW->the ucode address in master's memory space.
 678  */
 679 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 680 #else
 681 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 682 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 683 #endif
 684 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 685 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 686 #endif /* CONFIG_NOBQFMAN */
 687
 688 #ifdef CONFIG_SYS_DPAA_FMAN
 689 #define CONFIG_PHY_REALTEK
 690 #if defined(CONFIG_TARGET_T1024RDB)
 691 #define RGMII_PHY1_ADDR         0x2
 692 #define RGMII_PHY2_ADDR         0x6
 693 #define SGMII_AQR_PHY_ADDR      0x2
 694 #define FM1_10GEC1_PHY_ADDR     0x1
 695 #elif defined(CONFIG_TARGET_T1023RDB)
 696 #define RGMII_PHY1_ADDR         0x1
 697 #define SGMII_RTK_PHY_ADDR      0x3
 698 #define SGMII_AQR_PHY_ADDR      0x2
 699 #endif
 700 #endif
 701
 702 #ifdef CONFIG_FMAN_ENET
 703 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 704 #endif
 705
 706 /*
 707  * Dynamic MTD Partition support with mtdparts
 708  */
 709
 710 /*
 711  * Environment
 712  */
 713 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 714 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 715
 716 /*
 717  * Miscellaneous configurable options
 718  */
 719 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 720
 721 /*
 722  * For booting Linux, the board info and command line data
 723  * have to be in the first 64 MB of memory, since this is
 724  * the maximum mapped by the Linux kernel during initialization.
 725  */
 726 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 727 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 728
 729 #ifdef CONFIG_CMD_KGDB
 730 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 731 #endif
 732
 733 /*
 734  * Environment Configuration
 735  */
 736 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 737 #define CONFIG_BOOTFILE         "uImage"
 738 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 739 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 740 #define __USB_PHY_TYPE          utmi
 741
 742 #ifdef CONFIG_ARCH_T1024
 743 #define CONFIG_BOARDNAME t1024rdb
 744 #define BANK_INTLV cs0_cs1
 745 #else
 746 #define CONFIG_BOARDNAME t1023rdb
 747 #define BANK_INTLV  null
 748 #endif
 749
 750 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 751         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 752         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 753         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 754         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 755         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 756         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 757         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 758         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 759         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 760         "netdev=eth0\0"                                         \
 761         "tftpflash=tftpboot $loadaddr $uboot && "               \
 762         "protect off $ubootaddr +$filesize && "                 \
 763         "erase $ubootaddr +$filesize && "                       \
 764         "cp.b $loadaddr $ubootaddr $filesize && "               \
 765         "protect on $ubootaddr +$filesize && "                  \
 766         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 767         "consoledev=ttyS0\0"                                    \
 768         "ramdiskaddr=2000000\0"                                 \
 769         "fdtaddr=1e00000\0"                                     \
 770         "bdev=sda3\0"
 771
 772 #define CONFIG_LINUX                                    \
 773         "setenv bootargs root=/dev/ram rw "             \
 774         "console=$consoledev,$baudrate $othbootargs;"   \
 775         "setenv ramdiskaddr 0x02000000;"                \
 776         "setenv fdtaddr 0x00c00000;"                    \
 777         "setenv loadaddr 0x1000000;"                    \
 778         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 779
 780 #define CONFIG_NFSBOOTCOMMAND                   \
 781         "setenv bootargs root=/dev/nfs rw "     \
 782         "nfsroot=$serverip:$rootpath "          \
 783         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 784         "console=$consoledev,$baudrate $othbootargs;"   \
 785         "tftp $loadaddr $bootfile;"             \
 786         "tftp $fdtaddr $fdtfile;"               \
 787         "bootm $loadaddr - $fdtaddr"
 788
 789 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 790
 791 #include <asm/fsl_secure_boot.h>
 792
 793 #endif  /* __T1024RDB_H */