2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T1024/T1023 RDB board configuration file
14 #if defined(CONFIG_T1023RDB)
16 #define CONFIG_SYS_NO_FLASH
20 /* High Level Configuration Options */
21 #define CONFIG_SYS_GENERIC_BOARD
22 #define CONFIG_DISPLAY_BOARDINFO
24 #define CONFIG_E500 /* BOOKE e500 family */
25 #define CONFIG_E500MC /* BOOKE e500mc family */
26 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
27 #define CONFIG_MP /* support multiple processors */
28 #define CONFIG_PHYS_64BIT
29 #define CONFIG_ENABLE_36BIT_PHYS
31 #ifdef CONFIG_PHYS_64BIT
32 #define CONFIG_ADDR_MAP 1
33 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
36 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
37 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
38 #define CONFIG_FSL_IFC /* Enable IFC Support */
40 #define CONFIG_FSL_LAW /* Use common FSL init code */
41 #define CONFIG_ENV_OVERWRITE
43 /* support deep sleep */
44 #ifdef CONFIG_PPC_T1024
45 #define CONFIG_DEEP_SLEEP
47 #if defined(CONFIG_DEEP_SLEEP)
48 #define CONFIG_SILENT_CONSOLE
49 #define CONFIG_BOARD_EARLY_INIT_F
52 #ifdef CONFIG_RAMBOOT_PBL
53 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
54 #if defined(CONFIG_T1024RDB)
55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
56 #elif defined(CONFIG_T1023RDB)
57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
59 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
60 #define CONFIG_SPL_ENV_SUPPORT
61 #define CONFIG_SPL_SERIAL_SUPPORT
62 #define CONFIG_SPL_FLUSH_IMAGE
63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
64 #define CONFIG_SPL_LIBGENERIC_SUPPORT
65 #define CONFIG_SPL_LIBCOMMON_SUPPORT
66 #define CONFIG_SPL_I2C_SUPPORT
67 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
68 #define CONFIG_FSL_LAW /* Use common FSL init code */
69 #define CONFIG_SYS_TEXT_BASE 0x30001000
70 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
71 #define CONFIG_SPL_PAD_TO 0x40000
72 #define CONFIG_SPL_MAX_SIZE 0x28000
73 #define RESET_VECTOR_OFFSET 0x27FFC
74 #define BOOT_PAGE_OFFSET 0x27000
75 #ifdef CONFIG_SPL_BUILD
76 #define CONFIG_SPL_SKIP_RELOCATE
77 #define CONFIG_SPL_COMMON_INIT_DDR
78 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
79 #define CONFIG_SYS_NO_FLASH
83 #define CONFIG_SPL_NAND_SUPPORT
84 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
85 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
86 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
87 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
89 #define CONFIG_SPL_NAND_BOOT
92 #ifdef CONFIG_SPIFLASH
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
94 #define CONFIG_SPL_SPI_SUPPORT
95 #define CONFIG_SPL_SPI_FLASH_SUPPORT
96 #define CONFIG_SPL_SPI_FLASH_MINIMAL
97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
98 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
99 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
100 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
101 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
102 #ifndef CONFIG_SPL_BUILD
103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
105 #define CONFIG_SPL_SPI_BOOT
109 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
110 #define CONFIG_SPL_MMC_SUPPORT
111 #define CONFIG_SPL_MMC_MINIMAL
112 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
113 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
114 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
115 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
116 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
117 #ifndef CONFIG_SPL_BUILD
118 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
120 #define CONFIG_SPL_MMC_BOOT
123 #endif /* CONFIG_RAMBOOT_PBL */
125 #ifndef CONFIG_SYS_TEXT_BASE
126 #define CONFIG_SYS_TEXT_BASE 0xeff40000
129 #ifndef CONFIG_RESET_VECTOR_ADDRESS
130 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
133 #ifndef CONFIG_SYS_NO_FLASH
134 #define CONFIG_FLASH_CFI_DRIVER
135 #define CONFIG_SYS_FLASH_CFI
136 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
139 /* PCIe Boot - Master */
140 #define CONFIG_SRIO_PCIE_BOOT_MASTER
142 * for slave u-boot IMAGE instored in master memory space,
143 * PHYS must be aligned based on the SIZE
145 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
146 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
149 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
151 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
152 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
155 * for slave UCODE and ENV instored in master memory space,
156 * PHYS must be aligned based on the SIZE
158 #ifdef CONFIG_PHYS_64BIT
159 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
160 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
162 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
163 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
165 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
166 /* slave core release by master*/
167 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
168 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
170 /* PCIe Boot - Slave */
171 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
172 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
173 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
174 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
175 /* Set 1M boot space for PCIe boot */
176 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
177 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
178 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
179 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
180 #define CONFIG_SYS_NO_FLASH
183 #if defined(CONFIG_SPIFLASH)
184 #define CONFIG_SYS_EXTRA_ENV_RELOC
185 #define CONFIG_ENV_IS_IN_SPI_FLASH
186 #define CONFIG_ENV_SPI_BUS 0
187 #define CONFIG_ENV_SPI_CS 0
188 #define CONFIG_ENV_SPI_MAX_HZ 10000000
189 #define CONFIG_ENV_SPI_MODE 0
190 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
191 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
192 #if defined(CONFIG_T1024RDB)
193 #define CONFIG_ENV_SECT_SIZE 0x10000
194 #elif defined(CONFIG_T1023RDB)
195 #define CONFIG_ENV_SECT_SIZE 0x40000
197 #elif defined(CONFIG_SDCARD)
198 #define CONFIG_SYS_EXTRA_ENV_RELOC
199 #define CONFIG_ENV_IS_IN_MMC
200 #define CONFIG_SYS_MMC_ENV_DEV 0
201 #define CONFIG_ENV_SIZE 0x2000
202 #define CONFIG_ENV_OFFSET (512 * 0x800)
203 #elif defined(CONFIG_NAND)
204 #define CONFIG_SYS_EXTRA_ENV_RELOC
205 #define CONFIG_ENV_IS_IN_NAND
206 #define CONFIG_ENV_SIZE 0x2000
207 #if defined(CONFIG_T1024RDB)
208 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
209 #elif defined(CONFIG_T1023RDB)
210 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
212 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
213 #define CONFIG_ENV_IS_IN_REMOTE
214 #define CONFIG_ENV_ADDR 0xffe20000
215 #define CONFIG_ENV_SIZE 0x2000
216 #elif defined(CONFIG_ENV_IS_NOWHERE)
217 #define CONFIG_ENV_SIZE 0x2000
219 #define CONFIG_ENV_IS_IN_FLASH
220 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
221 #define CONFIG_ENV_SIZE 0x2000
222 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
227 unsigned long get_board_sys_clk(void);
228 unsigned long get_board_ddr_clk(void);
231 #define CONFIG_SYS_CLK_FREQ 100000000
232 #define CONFIG_DDR_CLK_FREQ 100000000
235 * These can be toggled for performance analysis, otherwise use default.
237 #define CONFIG_SYS_CACHE_STASHING
238 #define CONFIG_BACKSIDE_L2_CACHE
239 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
240 #define CONFIG_BTB /* toggle branch predition */
241 #define CONFIG_DDR_ECC
242 #ifdef CONFIG_DDR_ECC
243 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
244 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
247 #define CONFIG_CMD_MEMTEST
248 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
249 #define CONFIG_SYS_MEMTEST_END 0x00400000
250 #define CONFIG_SYS_ALT_MEMTEST
251 #define CONFIG_PANIC_HANG /* do not reset board on panic */
254 * Config the L3 Cache as L3 SRAM
256 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
257 #define CONFIG_SYS_L3_SIZE (256 << 10)
258 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
259 #ifdef CONFIG_RAMBOOT_PBL
260 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
262 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
263 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
264 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
265 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
267 #ifdef CONFIG_PHYS_64BIT
268 #define CONFIG_SYS_DCSRBAR 0xf0000000
269 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
273 #define CONFIG_ID_EEPROM
274 #define CONFIG_SYS_I2C_EEPROM_NXID
275 #define CONFIG_SYS_EEPROM_BUS_NUM 0
276 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
277 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
278 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
279 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
284 #define CONFIG_VERY_BIG_RAM
285 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
286 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
287 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
288 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
289 #define CONFIG_FSL_DDR_INTERACTIVE
290 #if defined(CONFIG_T1024RDB)
291 #define CONFIG_DDR_SPD
292 #define CONFIG_SYS_FSL_DDR3
293 #define CONFIG_SYS_SPD_BUS_NUM 0
294 #define SPD_EEPROM_ADDRESS 0x51
295 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
296 #elif defined(CONFIG_T1023RDB)
297 #define CONFIG_SYS_FSL_DDR4
298 #define CONFIG_SYS_DDR_RAW_TIMING
299 #define CONFIG_SYS_SDRAM_SIZE 2048
305 #define CONFIG_SYS_FLASH_BASE 0xe8000000
306 #ifdef CONFIG_PHYS_64BIT
307 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
309 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
312 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
313 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
314 CSPR_PORT_SIZE_16 | \
317 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
319 /* NOR Flash Timing Params */
320 #if defined(CONFIG_T1024RDB)
321 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
322 #elif defined(CONFIG_T1023RDB)
323 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
324 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
326 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
327 FTIM0_NOR_TEADC(0x5) | \
328 FTIM0_NOR_TEAHC(0x5))
329 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
330 FTIM1_NOR_TRAD_NOR(0x1A) |\
331 FTIM1_NOR_TSEQRAD_NOR(0x13))
332 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
333 FTIM2_NOR_TCH(0x4) | \
334 FTIM2_NOR_TWPH(0x0E) | \
336 #define CONFIG_SYS_NOR_FTIM3 0x0
338 #define CONFIG_SYS_FLASH_QUIET_TEST
339 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
341 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
342 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
343 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
344 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
346 #define CONFIG_SYS_FLASH_EMPTY_INFO
347 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
349 #ifdef CONFIG_T1024RDB
351 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
352 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
353 #define CONFIG_SYS_CSPR2_EXT (0xf)
354 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
358 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
359 #define CONFIG_SYS_CSOR2 0x0
361 /* CPLD Timing parameters for IFC CS2 */
362 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
363 FTIM0_GPCM_TEADC(0x0e) | \
364 FTIM0_GPCM_TEAHC(0x0e))
365 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
366 FTIM1_GPCM_TRAD(0x1f))
367 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
368 FTIM2_GPCM_TCH(0x8) | \
369 FTIM2_GPCM_TWP(0x1f))
370 #define CONFIG_SYS_CS2_FTIM3 0x0
373 /* NAND Flash on IFC */
374 #define CONFIG_NAND_FSL_IFC
375 #define CONFIG_SYS_NAND_BASE 0xff800000
376 #ifdef CONFIG_PHYS_64BIT
377 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
379 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
381 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
382 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
383 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
384 | CSPR_MSEL_NAND /* MSEL = NAND */ \
386 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
388 #if defined(CONFIG_T1024RDB)
389 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
390 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
391 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
392 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
393 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
394 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
395 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
396 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
397 #elif defined(CONFIG_T1023RDB)
398 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
399 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
400 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
401 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
402 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
403 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
404 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
405 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
408 #define CONFIG_SYS_NAND_ONFI_DETECTION
409 /* ONFI NAND Flash mode0 Timing Params */
410 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
411 FTIM0_NAND_TWP(0x18) | \
412 FTIM0_NAND_TWCHT(0x07) | \
413 FTIM0_NAND_TWH(0x0a))
414 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
415 FTIM1_NAND_TWBE(0x39) | \
416 FTIM1_NAND_TRR(0x0e) | \
417 FTIM1_NAND_TRP(0x18))
418 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
419 FTIM2_NAND_TREH(0x0a) | \
420 FTIM2_NAND_TWHRE(0x1e))
421 #define CONFIG_SYS_NAND_FTIM3 0x0
423 #define CONFIG_SYS_NAND_DDR_LAW 11
424 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
425 #define CONFIG_SYS_MAX_NAND_DEVICE 1
426 #define CONFIG_CMD_NAND
428 #if defined(CONFIG_NAND)
429 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
430 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
431 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
432 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
433 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
434 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
435 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
436 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
437 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
438 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
439 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
440 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
441 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
442 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
443 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
444 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
446 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
447 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
448 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
449 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
450 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
451 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
452 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
453 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
454 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
455 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
456 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
457 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
458 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
459 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
460 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
461 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
464 #ifdef CONFIG_SPL_BUILD
465 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
467 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
470 #if defined(CONFIG_RAMBOOT_PBL)
471 #define CONFIG_SYS_RAMBOOT
474 #define CONFIG_BOARD_EARLY_INIT_R
475 #define CONFIG_MISC_INIT_R
477 #define CONFIG_HWCONFIG
479 /* define to use L1 as initial stack */
480 #define CONFIG_L1_INIT_RAM
481 #define CONFIG_SYS_INIT_RAM_LOCK
482 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
483 #ifdef CONFIG_PHYS_64BIT
484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
486 /* The assembler doesn't like typecast */
487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
488 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
489 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
491 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
492 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
493 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
495 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
497 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
498 GENERATED_GBL_DATA_SIZE)
499 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
501 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
502 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
505 #define CONFIG_CONS_INDEX 1
506 #define CONFIG_SYS_NS16550
507 #define CONFIG_SYS_NS16550_SERIAL
508 #define CONFIG_SYS_NS16550_REG_SIZE 1
509 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
511 #define CONFIG_SYS_BAUDRATE_TABLE \
512 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
514 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
515 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
516 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
517 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
518 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
520 /* Use the HUSH parser */
521 #define CONFIG_SYS_HUSH_PARSER
522 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
525 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
526 #ifdef CONFIG_FSL_DIU_FB
527 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
529 #define CONFIG_CMD_BMP
530 #define CONFIG_CFB_CONSOLE
531 #define CONFIG_VIDEO_SW_CURSOR
532 #define CONFIG_VGA_AS_SINGLE_DEVICE
533 #define CONFIG_VIDEO_LOGO
534 #define CONFIG_VIDEO_BMP_LOGO
535 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
537 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
538 * disable empty flash sector detection, which is I/O-intensive.
540 #undef CONFIG_SYS_FLASH_EMPTY_INFO
543 /* pass open firmware flat tree */
544 #define CONFIG_OF_LIBFDT
545 #define CONFIG_OF_BOARD_SETUP
546 #define CONFIG_OF_STDOUT_VIA_ALIAS
548 /* new uImage format support */
550 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
553 #define CONFIG_SYS_I2C
554 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
555 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
556 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
557 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
558 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
559 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
560 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
562 #define I2C_MUX_PCA_ADDR 0x77
563 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
566 /* I2C bus multiplexer */
567 #define I2C_MUX_CH_DEFAULT 0x8
573 #define CONFIG_RTC_DS1337 1
574 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
577 * eSPI - Enhanced SPI
579 #define CONFIG_FSL_ESPI
580 #if defined(CONFIG_T1024RDB)
581 #define CONFIG_SPI_FLASH_STMICRO
582 #elif defined(CONFIG_T1023RDB)
583 #define CONFIG_SPI_FLASH_SPANSION
585 #define CONFIG_CMD_SF
586 #define CONFIG_SPI_FLASH_BAR
587 #define CONFIG_SF_DEFAULT_SPEED 10000000
588 #define CONFIG_SF_DEFAULT_MODE 0
592 * Memory space is mapped 1-1, but I/O space must start from 0.
594 #define CONFIG_PCI /* Enable PCI/PCIE */
595 #define CONFIG_PCIE1 /* PCIE controler 1 */
596 #define CONFIG_PCIE2 /* PCIE controler 2 */
597 #define CONFIG_PCIE3 /* PCIE controler 3 */
598 #ifdef CONFIG_PPC_T1040
599 #define CONFIG_PCIE4 /* PCIE controler 4 */
601 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
602 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
603 #define CONFIG_PCI_INDIRECT_BRIDGE
606 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
608 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
609 #ifdef CONFIG_PHYS_64BIT
610 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
611 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
613 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
614 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
616 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
617 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
618 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
619 #ifdef CONFIG_PHYS_64BIT
620 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
622 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
624 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
627 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
629 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
630 #ifdef CONFIG_PHYS_64BIT
631 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
632 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
634 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
635 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
637 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
638 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
639 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
640 #ifdef CONFIG_PHYS_64BIT
641 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
643 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
645 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
648 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
650 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
651 #ifdef CONFIG_PHYS_64BIT
652 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
653 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
655 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
656 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
658 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
659 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
660 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
661 #ifdef CONFIG_PHYS_64BIT
662 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
664 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
666 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
669 /* controller 4, Base address 203000, to be removed */
671 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
672 #ifdef CONFIG_PHYS_64BIT
673 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
674 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
676 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
677 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
679 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
680 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
681 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
682 #ifdef CONFIG_PHYS_64BIT
683 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
685 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
687 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
690 #define CONFIG_PCI_PNP /* do pci plug-and-play */
692 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
693 #define CONFIG_DOS_PARTITION
694 #endif /* CONFIG_PCI */
699 #define CONFIG_HAS_FSL_DR_USB
701 #ifdef CONFIG_HAS_FSL_DR_USB
702 #define CONFIG_USB_EHCI
703 #define CONFIG_CMD_USB
704 #define CONFIG_USB_STORAGE
705 #define CONFIG_USB_EHCI_FSL
706 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
707 #define CONFIG_CMD_EXT2
715 #define CONFIG_FSL_ESDHC
716 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
717 #define CONFIG_CMD_MMC
718 #define CONFIG_GENERIC_MMC
719 #define CONFIG_CMD_EXT2
720 #define CONFIG_CMD_FAT
721 #define CONFIG_DOS_PARTITION
725 #ifndef CONFIG_NOBQFMAN
726 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
727 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
728 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
729 #ifdef CONFIG_PHYS_64BIT
730 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
732 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
734 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
735 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
736 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
737 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
738 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
739 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
740 CONFIG_SYS_BMAN_CENA_SIZE)
741 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
742 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
743 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
744 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
745 #ifdef CONFIG_PHYS_64BIT
746 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
748 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
750 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
751 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
752 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
753 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
754 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
755 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
756 CONFIG_SYS_QMAN_CENA_SIZE)
757 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
758 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
760 #define CONFIG_SYS_DPAA_FMAN
764 /* Default address of microcode for the Linux FMan driver */
765 #if defined(CONFIG_SPIFLASH)
767 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
768 * env, so we got 0x110000.
770 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
771 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
772 #define CONFIG_SYS_QE_FW_ADDR 0x130000
773 #elif defined(CONFIG_SDCARD)
775 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
776 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
777 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
779 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
780 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
781 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
782 #elif defined(CONFIG_NAND)
783 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
784 #if defined(CONFIG_T1024RDB)
785 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
786 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
787 #elif defined(CONFIG_T1023RDB)
788 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
789 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
791 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
793 * Slave has no ucode locally, it can fetch this from remote. When implementing
794 * in two corenet boards, slave's ucode could be stored in master's memory
795 * space, the address can be mapped from slave TLB->slave LAW->
796 * slave SRIO or PCIE outbound window->master inbound window->
797 * master LAW->the ucode address in master's memory space.
799 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
800 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
802 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
803 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
804 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
806 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
807 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
808 #endif /* CONFIG_NOBQFMAN */
810 #ifdef CONFIG_SYS_DPAA_FMAN
811 #define CONFIG_FMAN_ENET
812 #define CONFIG_PHYLIB_10G
813 #define CONFIG_PHY_REALTEK
814 #define CONFIG_PHY_AQUANTIA
815 #if defined(CONFIG_T1024RDB)
816 #define RGMII_PHY1_ADDR 0x2
817 #define RGMII_PHY2_ADDR 0x6
818 #define SGMII_AQR_PHY_ADDR 0x2
819 #define FM1_10GEC1_PHY_ADDR 0x1
820 #elif defined(CONFIG_T1023RDB)
821 #define RGMII_PHY1_ADDR 0x1
822 #define SGMII_RTK_PHY_ADDR 0x3
823 #define SGMII_AQR_PHY_ADDR 0x2
827 #ifdef CONFIG_FMAN_ENET
828 #define CONFIG_MII /* MII PHY management */
829 #define CONFIG_ETHPRIME "FM1@DTSEC4"
830 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
834 * Dynamic MTD Partition support with mtdparts
836 #ifndef CONFIG_SYS_NO_FLASH
837 #define CONFIG_MTD_DEVICE
838 #define CONFIG_MTD_PARTITIONS
839 #define CONFIG_CMD_MTDPARTS
840 #define CONFIG_FLASH_CFI_MTD
841 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
843 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
844 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
845 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
846 "1m(uboot),5m(kernel),128k(dtb),-(user)"
852 #define CONFIG_LOADS_ECHO /* echo on for serial download */
853 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
856 * Command line configuration.
858 #define CONFIG_CMD_DATE
859 #define CONFIG_CMD_DHCP
860 #define CONFIG_CMD_EEPROM
861 #define CONFIG_CMD_ELF
862 #define CONFIG_CMD_ERRATA
863 #define CONFIG_CMD_GREPENV
864 #define CONFIG_CMD_IRQ
865 #define CONFIG_CMD_I2C
866 #define CONFIG_CMD_MII
867 #define CONFIG_CMD_PING
868 #define CONFIG_CMD_REGINFO
871 #define CONFIG_CMD_PCI
875 * Miscellaneous configurable options
877 #define CONFIG_SYS_LONGHELP /* undef to save memory */
878 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
879 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
880 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
881 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
882 #ifdef CONFIG_CMD_KGDB
883 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
885 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
887 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
888 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
889 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
892 * For booting Linux, the board info and command line data
893 * have to be in the first 64 MB of memory, since this is
894 * the maximum mapped by the Linux kernel during initialization.
896 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
897 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
899 #ifdef CONFIG_CMD_KGDB
900 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
904 * Environment Configuration
906 #define CONFIG_ROOTPATH "/opt/nfsroot"
907 #define CONFIG_BOOTFILE "uImage"
908 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
909 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
910 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
911 #define CONFIG_BAUDRATE 115200
912 #define __USB_PHY_TYPE utmi
914 #ifdef CONFIG_PPC_T1024
915 #define CONFIG_BOARDNAME t1024rdb
916 #define BANK_INTLV cs0_cs1
918 #define CONFIG_BOARDNAME t1023rdb
919 #define BANK_INTLV null
922 #define CONFIG_EXTRA_ENV_SETTINGS \
923 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
924 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
925 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
926 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
927 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
928 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
929 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
930 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
931 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
933 "tftpflash=tftpboot $loadaddr $uboot && " \
934 "protect off $ubootaddr +$filesize && " \
935 "erase $ubootaddr +$filesize && " \
936 "cp.b $loadaddr $ubootaddr $filesize && " \
937 "protect on $ubootaddr +$filesize && " \
938 "cmp.b $loadaddr $ubootaddr $filesize\0" \
939 "consoledev=ttyS0\0" \
940 "ramdiskaddr=2000000\0" \
944 #define CONFIG_LINUX \
945 "setenv bootargs root=/dev/ram rw " \
946 "console=$consoledev,$baudrate $othbootargs;" \
947 "setenv ramdiskaddr 0x02000000;" \
948 "setenv fdtaddr 0x00c00000;" \
949 "setenv loadaddr 0x1000000;" \
950 "bootm $loadaddr $ramdiskaddr $fdtaddr"
953 #define CONFIG_NFSBOOTCOMMAND \
954 "setenv bootargs root=/dev/nfs rw " \
955 "nfsroot=$serverip:$rootpath " \
956 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
957 "console=$consoledev,$baudrate $othbootargs;" \
958 "tftp $loadaddr $bootfile;" \
959 "tftp $fdtaddr $fdtfile;" \
960 "bootm $loadaddr - $fdtaddr"
962 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
964 #ifdef CONFIG_SECURE_BOOT
965 #include <asm/fsl_secure_boot.h>
968 #endif /* __T1024RDB_H */