2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T1024/T1023 RDB board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_E500 /* BOOKE e500 family */
18 #define CONFIG_E500MC /* BOOKE e500mc family */
19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
20 #define CONFIG_MP /* support multiple processors */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #ifdef CONFIG_PHYS_64BIT
24 #define CONFIG_ADDR_MAP 1
25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
30 #define CONFIG_FSL_IFC /* Enable IFC Support */
32 #define CONFIG_FSL_LAW /* Use common FSL init code */
33 #define CONFIG_ENV_OVERWRITE
35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
37 /* support deep sleep */
38 #ifdef CONFIG_PPC_T1024
39 #define CONFIG_DEEP_SLEEP
41 #if defined(CONFIG_DEEP_SLEEP)
42 #define CONFIG_SILENT_CONSOLE
43 #define CONFIG_BOARD_EARLY_INIT_F
46 #ifdef CONFIG_RAMBOOT_PBL
47 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
48 #if defined(CONFIG_T1024RDB)
49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
50 #elif defined(CONFIG_T1023RDB)
51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
53 #define CONFIG_SPL_SERIAL_SUPPORT
54 #define CONFIG_SPL_FLUSH_IMAGE
55 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
56 #define CONFIG_FSL_LAW /* Use common FSL init code */
57 #define CONFIG_SYS_TEXT_BASE 0x30001000
58 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
59 #define CONFIG_SPL_PAD_TO 0x40000
60 #define CONFIG_SPL_MAX_SIZE 0x28000
61 #define RESET_VECTOR_OFFSET 0x27FFC
62 #define BOOT_PAGE_OFFSET 0x27000
63 #ifdef CONFIG_SPL_BUILD
64 #define CONFIG_SPL_SKIP_RELOCATE
65 #define CONFIG_SPL_COMMON_INIT_DDR
66 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
67 #define CONFIG_SYS_NO_FLASH
71 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
72 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
73 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
74 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
76 #define CONFIG_SPL_NAND_BOOT
79 #ifdef CONFIG_SPIFLASH
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
81 #define CONFIG_SPL_SPI_SUPPORT
82 #define CONFIG_SPL_SPI_FLASH_SUPPORT
83 #define CONFIG_SPL_SPI_FLASH_MINIMAL
84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
89 #ifndef CONFIG_SPL_BUILD
90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
92 #define CONFIG_SPL_SPI_BOOT
96 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
97 #define CONFIG_SPL_MMC_MINIMAL
98 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
99 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
100 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
101 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
102 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
103 #ifndef CONFIG_SPL_BUILD
104 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
106 #define CONFIG_SPL_MMC_BOOT
109 #endif /* CONFIG_RAMBOOT_PBL */
111 #ifndef CONFIG_SYS_TEXT_BASE
112 #define CONFIG_SYS_TEXT_BASE 0xeff40000
115 #ifndef CONFIG_RESET_VECTOR_ADDRESS
116 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
119 #ifndef CONFIG_SYS_NO_FLASH
120 #define CONFIG_FLASH_CFI_DRIVER
121 #define CONFIG_SYS_FLASH_CFI
122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
125 /* PCIe Boot - Master */
126 #define CONFIG_SRIO_PCIE_BOOT_MASTER
128 * for slave u-boot IMAGE instored in master memory space,
129 * PHYS must be aligned based on the SIZE
131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
133 #ifdef CONFIG_PHYS_64BIT
134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
138 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
141 * for slave UCODE and ENV instored in master memory space,
142 * PHYS must be aligned based on the SIZE
144 #ifdef CONFIG_PHYS_64BIT
145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
149 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
152 /* slave core release by master*/
153 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
154 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
156 /* PCIe Boot - Slave */
157 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
158 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
159 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
160 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
161 /* Set 1M boot space for PCIe boot */
162 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
163 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
164 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
165 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
166 #define CONFIG_SYS_NO_FLASH
169 #if defined(CONFIG_SPIFLASH)
170 #define CONFIG_SYS_EXTRA_ENV_RELOC
171 #define CONFIG_ENV_IS_IN_SPI_FLASH
172 #define CONFIG_ENV_SPI_BUS 0
173 #define CONFIG_ENV_SPI_CS 0
174 #define CONFIG_ENV_SPI_MAX_HZ 10000000
175 #define CONFIG_ENV_SPI_MODE 0
176 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
177 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
178 #if defined(CONFIG_T1024RDB)
179 #define CONFIG_ENV_SECT_SIZE 0x10000
180 #elif defined(CONFIG_T1023RDB)
181 #define CONFIG_ENV_SECT_SIZE 0x40000
183 #elif defined(CONFIG_SDCARD)
184 #define CONFIG_SYS_EXTRA_ENV_RELOC
185 #define CONFIG_ENV_IS_IN_MMC
186 #define CONFIG_SYS_MMC_ENV_DEV 0
187 #define CONFIG_ENV_SIZE 0x2000
188 #define CONFIG_ENV_OFFSET (512 * 0x800)
189 #elif defined(CONFIG_NAND)
190 #define CONFIG_SYS_EXTRA_ENV_RELOC
191 #define CONFIG_ENV_IS_IN_NAND
192 #define CONFIG_ENV_SIZE 0x2000
193 #if defined(CONFIG_T1024RDB)
194 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
195 #elif defined(CONFIG_T1023RDB)
196 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
198 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
199 #define CONFIG_ENV_IS_IN_REMOTE
200 #define CONFIG_ENV_ADDR 0xffe20000
201 #define CONFIG_ENV_SIZE 0x2000
202 #elif defined(CONFIG_ENV_IS_NOWHERE)
203 #define CONFIG_ENV_SIZE 0x2000
205 #define CONFIG_ENV_IS_IN_FLASH
206 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
207 #define CONFIG_ENV_SIZE 0x2000
208 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
212 unsigned long get_board_sys_clk(void);
213 unsigned long get_board_ddr_clk(void);
216 #define CONFIG_SYS_CLK_FREQ 100000000
217 #define CONFIG_DDR_CLK_FREQ 100000000
220 * These can be toggled for performance analysis, otherwise use default.
222 #define CONFIG_SYS_CACHE_STASHING
223 #define CONFIG_BACKSIDE_L2_CACHE
224 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
225 #define CONFIG_BTB /* toggle branch predition */
226 #define CONFIG_DDR_ECC
227 #ifdef CONFIG_DDR_ECC
228 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
229 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
232 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
233 #define CONFIG_SYS_MEMTEST_END 0x00400000
234 #define CONFIG_SYS_ALT_MEMTEST
235 #define CONFIG_PANIC_HANG /* do not reset board on panic */
238 * Config the L3 Cache as L3 SRAM
240 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
241 #define CONFIG_SYS_L3_SIZE (256 << 10)
242 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
243 #ifdef CONFIG_RAMBOOT_PBL
244 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
246 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
247 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
248 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
249 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
251 #ifdef CONFIG_PHYS_64BIT
252 #define CONFIG_SYS_DCSRBAR 0xf0000000
253 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
257 #define CONFIG_ID_EEPROM
258 #define CONFIG_SYS_I2C_EEPROM_NXID
259 #define CONFIG_SYS_EEPROM_BUS_NUM 0
260 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
261 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
263 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
268 #define CONFIG_VERY_BIG_RAM
269 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
270 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
271 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
272 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
273 #define CONFIG_FSL_DDR_INTERACTIVE
274 #if defined(CONFIG_T1024RDB)
275 #define CONFIG_DDR_SPD
276 #define CONFIG_SYS_FSL_DDR3
277 #define CONFIG_SYS_SPD_BUS_NUM 0
278 #define SPD_EEPROM_ADDRESS 0x51
279 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
280 #elif defined(CONFIG_T1023RDB)
281 #define CONFIG_SYS_FSL_DDR4
282 #define CONFIG_SYS_DDR_RAW_TIMING
283 #define CONFIG_SYS_SDRAM_SIZE 2048
289 #define CONFIG_SYS_FLASH_BASE 0xe8000000
290 #ifdef CONFIG_PHYS_64BIT
291 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
293 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
296 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
297 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
298 CSPR_PORT_SIZE_16 | \
301 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
303 /* NOR Flash Timing Params */
304 #if defined(CONFIG_T1024RDB)
305 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
306 #elif defined(CONFIG_T1023RDB)
307 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
308 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
310 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
311 FTIM0_NOR_TEADC(0x5) | \
312 FTIM0_NOR_TEAHC(0x5))
313 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
314 FTIM1_NOR_TRAD_NOR(0x1A) |\
315 FTIM1_NOR_TSEQRAD_NOR(0x13))
316 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
317 FTIM2_NOR_TCH(0x4) | \
318 FTIM2_NOR_TWPH(0x0E) | \
320 #define CONFIG_SYS_NOR_FTIM3 0x0
322 #define CONFIG_SYS_FLASH_QUIET_TEST
323 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
325 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
326 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
327 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
328 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
330 #define CONFIG_SYS_FLASH_EMPTY_INFO
331 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
333 #ifdef CONFIG_T1024RDB
335 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
336 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
337 #define CONFIG_SYS_CSPR2_EXT (0xf)
338 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
342 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
343 #define CONFIG_SYS_CSOR2 0x0
345 /* CPLD Timing parameters for IFC CS2 */
346 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
347 FTIM0_GPCM_TEADC(0x0e) | \
348 FTIM0_GPCM_TEAHC(0x0e))
349 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
350 FTIM1_GPCM_TRAD(0x1f))
351 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
352 FTIM2_GPCM_TCH(0x8) | \
353 FTIM2_GPCM_TWP(0x1f))
354 #define CONFIG_SYS_CS2_FTIM3 0x0
357 /* NAND Flash on IFC */
358 #define CONFIG_NAND_FSL_IFC
359 #define CONFIG_SYS_NAND_BASE 0xff800000
360 #ifdef CONFIG_PHYS_64BIT
361 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
363 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
365 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
366 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
367 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
368 | CSPR_MSEL_NAND /* MSEL = NAND */ \
370 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
372 #if defined(CONFIG_T1024RDB)
373 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
374 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
375 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
376 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
377 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
378 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
379 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
380 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
381 #elif defined(CONFIG_T1023RDB)
382 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
383 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
384 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
385 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
386 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
387 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
388 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
389 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
392 #define CONFIG_SYS_NAND_ONFI_DETECTION
393 /* ONFI NAND Flash mode0 Timing Params */
394 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
395 FTIM0_NAND_TWP(0x18) | \
396 FTIM0_NAND_TWCHT(0x07) | \
397 FTIM0_NAND_TWH(0x0a))
398 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
399 FTIM1_NAND_TWBE(0x39) | \
400 FTIM1_NAND_TRR(0x0e) | \
401 FTIM1_NAND_TRP(0x18))
402 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
403 FTIM2_NAND_TREH(0x0a) | \
404 FTIM2_NAND_TWHRE(0x1e))
405 #define CONFIG_SYS_NAND_FTIM3 0x0
407 #define CONFIG_SYS_NAND_DDR_LAW 11
408 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
409 #define CONFIG_SYS_MAX_NAND_DEVICE 1
410 #define CONFIG_CMD_NAND
412 #if defined(CONFIG_NAND)
413 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
414 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
415 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
416 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
417 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
418 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
419 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
420 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
421 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
422 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
423 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
424 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
425 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
426 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
427 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
428 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
430 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
431 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
432 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
433 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
434 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
435 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
436 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
437 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
438 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
439 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
440 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
441 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
442 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
443 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
444 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
445 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
448 #ifdef CONFIG_SPL_BUILD
449 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
451 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
454 #if defined(CONFIG_RAMBOOT_PBL)
455 #define CONFIG_SYS_RAMBOOT
458 #define CONFIG_BOARD_EARLY_INIT_R
459 #define CONFIG_MISC_INIT_R
461 #define CONFIG_HWCONFIG
463 /* define to use L1 as initial stack */
464 #define CONFIG_L1_INIT_RAM
465 #define CONFIG_SYS_INIT_RAM_LOCK
466 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
467 #ifdef CONFIG_PHYS_64BIT
468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
470 /* The assembler doesn't like typecast */
471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
472 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
473 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
479 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
481 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
482 GENERATED_GBL_DATA_SIZE)
483 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
485 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
486 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
489 #define CONFIG_CONS_INDEX 1
490 #define CONFIG_SYS_NS16550_SERIAL
491 #define CONFIG_SYS_NS16550_REG_SIZE 1
492 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
494 #define CONFIG_SYS_BAUDRATE_TABLE \
495 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
497 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
498 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
499 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
500 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
501 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
504 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
505 #ifdef CONFIG_FSL_DIU_FB
506 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
508 #define CONFIG_CMD_BMP
509 #define CONFIG_CFB_CONSOLE
510 #define CONFIG_VIDEO_SW_CURSOR
511 #define CONFIG_VGA_AS_SINGLE_DEVICE
512 #define CONFIG_VIDEO_LOGO
513 #define CONFIG_VIDEO_BMP_LOGO
514 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
516 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
517 * disable empty flash sector detection, which is I/O-intensive.
519 #undef CONFIG_SYS_FLASH_EMPTY_INFO
523 #define CONFIG_SYS_I2C
524 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
525 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
526 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
527 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
528 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
529 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
530 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
532 #define I2C_PCA6408_BUS_NUM 1
533 #define I2C_PCA6408_ADDR 0x20
535 /* I2C bus multiplexer */
536 #define I2C_MUX_CH_DEFAULT 0x8
542 #define CONFIG_RTC_DS1337 1
543 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
546 * eSPI - Enhanced SPI
548 #define CONFIG_SPI_FLASH_BAR
549 #define CONFIG_SF_DEFAULT_SPEED 10000000
550 #define CONFIG_SF_DEFAULT_MODE 0
554 * Memory space is mapped 1-1, but I/O space must start from 0.
556 #define CONFIG_PCI /* Enable PCI/PCIE */
557 #define CONFIG_PCIE1 /* PCIE controller 1 */
558 #define CONFIG_PCIE2 /* PCIE controller 2 */
559 #define CONFIG_PCIE3 /* PCIE controller 3 */
560 #ifdef CONFIG_PPC_T1040
561 #define CONFIG_PCIE4 /* PCIE controller 4 */
563 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
564 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
565 #define CONFIG_PCI_INDIRECT_BRIDGE
568 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
570 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
571 #ifdef CONFIG_PHYS_64BIT
572 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
573 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
575 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
576 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
578 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
579 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
580 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
581 #ifdef CONFIG_PHYS_64BIT
582 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
584 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
586 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
589 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
591 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
592 #ifdef CONFIG_PHYS_64BIT
593 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
594 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
596 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
597 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
599 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
600 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
601 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
602 #ifdef CONFIG_PHYS_64BIT
603 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
605 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
607 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
610 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
612 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
613 #ifdef CONFIG_PHYS_64BIT
614 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
615 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
617 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
618 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
620 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
621 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
622 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
623 #ifdef CONFIG_PHYS_64BIT
624 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
626 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
628 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
631 /* controller 4, Base address 203000, to be removed */
633 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
634 #ifdef CONFIG_PHYS_64BIT
635 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
636 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
638 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
639 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
641 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
642 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
643 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
644 #ifdef CONFIG_PHYS_64BIT
645 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
647 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
649 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
652 #define CONFIG_PCI_PNP /* do pci plug-and-play */
653 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
654 #define CONFIG_DOS_PARTITION
655 #endif /* CONFIG_PCI */
660 #define CONFIG_HAS_FSL_DR_USB
662 #ifdef CONFIG_HAS_FSL_DR_USB
663 #define CONFIG_USB_EHCI
664 #define CONFIG_USB_EHCI_FSL
665 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
673 #define CONFIG_FSL_ESDHC
674 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
675 #define CONFIG_GENERIC_MMC
676 #define CONFIG_DOS_PARTITION
680 #ifndef CONFIG_NOBQFMAN
681 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
682 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
683 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
684 #ifdef CONFIG_PHYS_64BIT
685 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
687 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
689 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
690 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
691 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
692 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
693 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
694 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
695 CONFIG_SYS_BMAN_CENA_SIZE)
696 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
697 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
698 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
699 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
700 #ifdef CONFIG_PHYS_64BIT
701 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
703 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
705 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
706 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
707 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
708 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
709 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
710 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
711 CONFIG_SYS_QMAN_CENA_SIZE)
712 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
713 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
715 #define CONFIG_SYS_DPAA_FMAN
717 #ifdef CONFIG_T1024RDB
721 /* Default address of microcode for the Linux FMan driver */
722 #if defined(CONFIG_SPIFLASH)
724 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
725 * env, so we got 0x110000.
727 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
728 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
729 #define CONFIG_SYS_QE_FW_ADDR 0x130000
730 #elif defined(CONFIG_SDCARD)
732 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
733 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
734 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
736 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
737 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
738 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
739 #elif defined(CONFIG_NAND)
740 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
741 #if defined(CONFIG_T1024RDB)
742 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
743 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
744 #elif defined(CONFIG_T1023RDB)
745 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
746 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
748 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
750 * Slave has no ucode locally, it can fetch this from remote. When implementing
751 * in two corenet boards, slave's ucode could be stored in master's memory
752 * space, the address can be mapped from slave TLB->slave LAW->
753 * slave SRIO or PCIE outbound window->master inbound window->
754 * master LAW->the ucode address in master's memory space.
756 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
757 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
759 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
760 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
761 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
763 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
764 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
765 #endif /* CONFIG_NOBQFMAN */
767 #ifdef CONFIG_SYS_DPAA_FMAN
768 #define CONFIG_FMAN_ENET
769 #define CONFIG_PHYLIB_10G
770 #define CONFIG_PHY_REALTEK
771 #define CONFIG_PHY_AQUANTIA
772 #if defined(CONFIG_T1024RDB)
773 #define RGMII_PHY1_ADDR 0x2
774 #define RGMII_PHY2_ADDR 0x6
775 #define SGMII_AQR_PHY_ADDR 0x2
776 #define FM1_10GEC1_PHY_ADDR 0x1
777 #elif defined(CONFIG_T1023RDB)
778 #define RGMII_PHY1_ADDR 0x1
779 #define SGMII_RTK_PHY_ADDR 0x3
780 #define SGMII_AQR_PHY_ADDR 0x2
784 #ifdef CONFIG_FMAN_ENET
785 #define CONFIG_MII /* MII PHY management */
786 #define CONFIG_ETHPRIME "FM1@DTSEC4"
787 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
791 * Dynamic MTD Partition support with mtdparts
793 #ifndef CONFIG_SYS_NO_FLASH
794 #define CONFIG_MTD_DEVICE
795 #define CONFIG_MTD_PARTITIONS
796 #define CONFIG_CMD_MTDPARTS
797 #define CONFIG_FLASH_CFI_MTD
798 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
800 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
801 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
802 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
803 "1m(uboot),5m(kernel),128k(dtb),-(user)"
809 #define CONFIG_LOADS_ECHO /* echo on for serial download */
810 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
813 * Command line configuration.
815 #define CONFIG_CMD_DATE
816 #define CONFIG_CMD_EEPROM
817 #define CONFIG_CMD_ERRATA
818 #define CONFIG_CMD_IRQ
819 #define CONFIG_CMD_REGINFO
822 #define CONFIG_CMD_PCI
826 * Miscellaneous configurable options
828 #define CONFIG_SYS_LONGHELP /* undef to save memory */
829 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
830 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
831 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
832 #ifdef CONFIG_CMD_KGDB
833 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
835 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
837 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
838 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
839 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
842 * For booting Linux, the board info and command line data
843 * have to be in the first 64 MB of memory, since this is
844 * the maximum mapped by the Linux kernel during initialization.
846 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
847 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
849 #ifdef CONFIG_CMD_KGDB
850 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
854 * Environment Configuration
856 #define CONFIG_ROOTPATH "/opt/nfsroot"
857 #define CONFIG_BOOTFILE "uImage"
858 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
859 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
860 #define CONFIG_BAUDRATE 115200
861 #define __USB_PHY_TYPE utmi
863 #ifdef CONFIG_PPC_T1024
864 #define CONFIG_BOARDNAME t1024rdb
865 #define BANK_INTLV cs0_cs1
867 #define CONFIG_BOARDNAME t1023rdb
868 #define BANK_INTLV null
871 #define CONFIG_EXTRA_ENV_SETTINGS \
872 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
873 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
874 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
875 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
876 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
877 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
878 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
879 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
880 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
882 "tftpflash=tftpboot $loadaddr $uboot && " \
883 "protect off $ubootaddr +$filesize && " \
884 "erase $ubootaddr +$filesize && " \
885 "cp.b $loadaddr $ubootaddr $filesize && " \
886 "protect on $ubootaddr +$filesize && " \
887 "cmp.b $loadaddr $ubootaddr $filesize\0" \
888 "consoledev=ttyS0\0" \
889 "ramdiskaddr=2000000\0" \
890 "fdtaddr=1e00000\0" \
893 #define CONFIG_LINUX \
894 "setenv bootargs root=/dev/ram rw " \
895 "console=$consoledev,$baudrate $othbootargs;" \
896 "setenv ramdiskaddr 0x02000000;" \
897 "setenv fdtaddr 0x00c00000;" \
898 "setenv loadaddr 0x1000000;" \
899 "bootm $loadaddr $ramdiskaddr $fdtaddr"
901 #define CONFIG_NFSBOOTCOMMAND \
902 "setenv bootargs root=/dev/nfs rw " \
903 "nfsroot=$serverip:$rootpath " \
904 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
905 "console=$consoledev,$baudrate $othbootargs;" \
906 "tftp $loadaddr $bootfile;" \
907 "tftp $fdtaddr $fdtfile;" \
908 "bootm $loadaddr - $fdtaddr"
910 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
912 /* Hash command with SHA acceleration supported in hardware */
913 #ifdef CONFIG_FSL_CAAM
914 #define CONFIG_CMD_HASH
915 #define CONFIG_SHA_HW_ACCEL
918 #include <asm/fsl_secure_boot.h>
920 #endif /* __T1024RDB_H */