include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 RDB board configuration file
   9  */
  10
  11 #ifndef __T1024RDB_H
  12 #define __T1024RDB_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_ENABLE_36BIT_PHYS
  17
  18 #ifdef CONFIG_PHYS_64BIT
  19 #define CONFIG_ADDR_MAP         1
  20 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  21 #endif
  22
  23 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  24 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  25
  26 #define CONFIG_ENV_OVERWRITE
  27
  28 /* support deep sleep */
  29 #ifdef CONFIG_ARCH_T1024
  30 #define CONFIG_DEEP_SLEEP
  31 #endif
  32
  33 #ifdef CONFIG_RAMBOOT_PBL
  34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  35 #define CONFIG_SPL_FLUSH_IMAGE
  36 #define CONFIG_SPL_PAD_TO               0x40000
  37 #define CONFIG_SPL_MAX_SIZE             0x28000
  38 #define RESET_VECTOR_OFFSET             0x27FFC
  39 #define BOOT_PAGE_OFFSET                0x27000
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SPL_SKIP_RELOCATE
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #endif
  45
  46 #ifdef CONFIG_MTD_RAW_NAND
  47 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  48 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  49 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  50 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  51 #if defined(CONFIG_TARGET_T1024RDB)
  52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  53 #elif defined(CONFIG_TARGET_T1023RDB)
  54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  55 #endif
  56 #endif
  57
  58 #ifdef CONFIG_SPIFLASH
  59 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  60 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  65 #ifndef CONFIG_SPL_BUILD
  66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67 #endif
  68 #if defined(CONFIG_TARGET_T1024RDB)
  69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  70 #elif defined(CONFIG_TARGET_T1023RDB)
  71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  72 #endif
  73 #endif
  74
  75 #ifdef CONFIG_SDCARD
  76 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  77 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  78 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  79 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  80 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  81 #ifndef CONFIG_SPL_BUILD
  82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83 #endif
  84 #if defined(CONFIG_TARGET_T1024RDB)
  85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  86 #elif defined(CONFIG_TARGET_T1023RDB)
  87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  88 #endif
  89 #endif
  90
  91 #endif /* CONFIG_RAMBOOT_PBL */
  92
  93 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  94 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  95 #endif
  96
  97 /* PCIe Boot - Master */
  98 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  99 /*
 100  * for slave u-boot IMAGE instored in master memory space,
 101  * PHYS must be aligned based on the SIZE
 102  */
 103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 105 #ifdef CONFIG_PHYS_64BIT
 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 108 #else
 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 111 #endif
 112 /*
 113  * for slave UCODE and ENV instored in master memory space,
 114  * PHYS must be aligned based on the SIZE
 115  */
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 119 #else
 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 121 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 122 #endif
 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 124 /* slave core release by master*/
 125 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 126 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 127
 128 /* PCIe Boot - Slave */
 129 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 131 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 132                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 133 /* Set 1M boot space for PCIe boot */
 134 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 135 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 136                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 137 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 138 #endif
 139
 140 #if defined(CONFIG_SPIFLASH)
 141 #elif defined(CONFIG_SDCARD)
 142 #define CONFIG_SYS_MMC_ENV_DEV          0
 143 #endif
 144
 145 #ifndef __ASSEMBLY__
 146 unsigned long get_board_sys_clk(void);
 147 unsigned long get_board_ddr_clk(void);
 148 #endif
 149
 150 #define CONFIG_SYS_CLK_FREQ     100000000
 151 #define CONFIG_DDR_CLK_FREQ     100000000
 152
 153 /*
 154  * These can be toggled for performance analysis, otherwise use default.
 155  */
 156 #define CONFIG_SYS_CACHE_STASHING
 157 #define CONFIG_BACKSIDE_L2_CACHE
 158 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 159 #define CONFIG_BTB                      /* toggle branch predition */
 160 #define CONFIG_DDR_ECC
 161 #ifdef CONFIG_DDR_ECC
 162 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 163 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 164 #endif
 165
 166 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 167 #define CONFIG_SYS_MEMTEST_END          0x00400000
 168
 169 /*
 170  *  Config the L3 Cache as L3 SRAM
 171  */
 172 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 173 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 174 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 175 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 176 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 177 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 178 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 179
 180 #ifdef CONFIG_PHYS_64BIT
 181 #define CONFIG_SYS_DCSRBAR              0xf0000000
 182 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 183 #endif
 184
 185 /* EEPROM */
 186 #define CONFIG_ID_EEPROM
 187 #define CONFIG_SYS_I2C_EEPROM_NXID
 188 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 189 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 191 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 192 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 193
 194 /*
 195  * DDR Setup
 196  */
 197 #define CONFIG_VERY_BIG_RAM
 198 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 199 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 200 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 201 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 202 #if defined(CONFIG_TARGET_T1024RDB)
 203 #define CONFIG_DDR_SPD
 204 #define CONFIG_SYS_SPD_BUS_NUM  0
 205 #define SPD_EEPROM_ADDRESS      0x51
 206 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 207 #elif defined(CONFIG_TARGET_T1023RDB)
 208 #define CONFIG_SYS_DDR_RAW_TIMING
 209 #define CONFIG_SYS_SDRAM_SIZE   2048
 210 #endif
 211
 212 /*
 213  * IFC Definitions
 214  */
 215 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 216 #ifdef CONFIG_PHYS_64BIT
 217 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 218 #else
 219 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 220 #endif
 221
 222 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 223 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 224                                 CSPR_PORT_SIZE_16 | \
 225                                 CSPR_MSEL_NOR | \
 226                                 CSPR_V)
 227 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 228
 229 /* NOR Flash Timing Params */
 230 #if defined(CONFIG_TARGET_T1024RDB)
 231 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 232 #elif defined(CONFIG_TARGET_T1023RDB)
 233 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 234                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 235 #endif
 236 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 237                                 FTIM0_NOR_TEADC(0x5) | \
 238                                 FTIM0_NOR_TEAHC(0x5))
 239 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 240                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 241                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 242 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 243                                 FTIM2_NOR_TCH(0x4) | \
 244                                 FTIM2_NOR_TWPH(0x0E) | \
 245                                 FTIM2_NOR_TWP(0x1c))
 246 #define CONFIG_SYS_NOR_FTIM3    0x0
 247
 248 #define CONFIG_SYS_FLASH_QUIET_TEST
 249 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 250
 251 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 252 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 253 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 254 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 255
 256 #define CONFIG_SYS_FLASH_EMPTY_INFO
 257 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 258
 259 #ifdef CONFIG_TARGET_T1024RDB
 260 /* CPLD on IFC */
 261 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 262 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 263 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 264 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 265                                                 | CSPR_PORT_SIZE_8 \
 266                                                 | CSPR_MSEL_GPCM \
 267                                                 | CSPR_V)
 268 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 269 #define CONFIG_SYS_CSOR2                0x0
 270
 271 /* CPLD Timing parameters for IFC CS2 */
 272 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 273                                                 FTIM0_GPCM_TEADC(0x0e) | \
 274                                                 FTIM0_GPCM_TEAHC(0x0e))
 275 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 276                                                 FTIM1_GPCM_TRAD(0x1f))
 277 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 278                                                 FTIM2_GPCM_TCH(0x8) | \
 279                                                 FTIM2_GPCM_TWP(0x1f))
 280 #define CONFIG_SYS_CS2_FTIM3            0x0
 281 #endif
 282
 283 /* NAND Flash on IFC */
 284 #define CONFIG_NAND_FSL_IFC
 285 #define CONFIG_SYS_NAND_BASE            0xff800000
 286 #ifdef CONFIG_PHYS_64BIT
 287 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 288 #else
 289 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 290 #endif
 291 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 292 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 293                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 294                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 295                                 | CSPR_V)
 296 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 297
 298 #if defined(CONFIG_TARGET_T1024RDB)
 299 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 300                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 301                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 302                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 303                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 304                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 305                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 306 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 307 #elif defined(CONFIG_TARGET_T1023RDB)
 308 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 309                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 310                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 311                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 312                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 313                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 314                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 315 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 316 #endif
 317
 318 #define CONFIG_SYS_NAND_ONFI_DETECTION
 319 /* ONFI NAND Flash mode0 Timing Params */
 320 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 321                                         FTIM0_NAND_TWP(0x18)   | \
 322                                         FTIM0_NAND_TWCHT(0x07) | \
 323                                         FTIM0_NAND_TWH(0x0a))
 324 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 325                                         FTIM1_NAND_TWBE(0x39)  | \
 326                                         FTIM1_NAND_TRR(0x0e)   | \
 327                                         FTIM1_NAND_TRP(0x18))
 328 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 329                                         FTIM2_NAND_TREH(0x0a) | \
 330                                         FTIM2_NAND_TWHRE(0x1e))
 331 #define CONFIG_SYS_NAND_FTIM3           0x0
 332
 333 #define CONFIG_SYS_NAND_DDR_LAW         11
 334 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 335 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 336
 337 #if defined(CONFIG_MTD_RAW_NAND)
 338 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 339 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 340 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 341 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 342 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 343 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 344 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 345 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 346 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 347 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 348 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 349 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 350 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 351 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 352 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 353 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 354 #else
 355 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 356 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 357 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 358 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 359 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 360 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 361 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 362 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 363 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 364 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 365 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 366 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 367 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 368 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 369 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 370 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 371 #endif
 372
 373 #ifdef CONFIG_SPL_BUILD
 374 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 375 #else
 376 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 377 #endif
 378
 379 #if defined(CONFIG_RAMBOOT_PBL)
 380 #define CONFIG_SYS_RAMBOOT
 381 #endif
 382
 383 #define CONFIG_HWCONFIG
 384
 385 /* define to use L1 as initial stack */
 386 #define CONFIG_L1_INIT_RAM
 387 #define CONFIG_SYS_INIT_RAM_LOCK
 388 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 389 #ifdef CONFIG_PHYS_64BIT
 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 392 /* The assembler doesn't like typecast */
 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 394         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 395           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 396 #else
 397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 399 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 400 #endif
 401 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 402
 403 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 404                                         GENERATED_GBL_DATA_SIZE)
 405 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 406
 407 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 408 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 409
 410 /* Serial Port */
 411 #define CONFIG_SYS_NS16550_SERIAL
 412 #define CONFIG_SYS_NS16550_REG_SIZE     1
 413 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 414
 415 #define CONFIG_SYS_BAUDRATE_TABLE       \
 416         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 417
 418 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 419 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 420 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 421 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 422
 423 /* Video */
 424 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 425 #ifdef CONFIG_FSL_DIU_FB
 426 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 427 #define CONFIG_VIDEO_LOGO
 428 #define CONFIG_VIDEO_BMP_LOGO
 429 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 430 /*
 431  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 432  * disable empty flash sector detection, which is I/O-intensive.
 433  */
 434 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 435 #endif
 436
 437 /* I2C */
 438 #ifndef CONFIG_DM_I2C
 439 #define CONFIG_SYS_I2C
 440 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 441 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 442 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 443 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 444 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 445 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 446 #else
 447 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 448 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 449 #endif
 450
 451 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 452 #define I2C_PCA6408_BUS_NUM             1
 453 #define I2C_PCA6408_ADDR                0x20
 454
 455 /* I2C bus multiplexer */
 456 #define I2C_MUX_CH_DEFAULT      0x8
 457
 458 /*
 459  * RTC configuration
 460  */
 461 #define RTC
 462 #define CONFIG_RTC_DS1337       1
 463 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 464
 465 /*
 466  * eSPI - Enhanced SPI
 467  */
 468
 469 /*
 470  * General PCIe
 471  * Memory space is mapped 1-1, but I/O space must start from 0.
 472  */
 473 #define CONFIG_PCIE1            /* PCIE controller 1 */
 474 #define CONFIG_PCIE2            /* PCIE controller 2 */
 475 #define CONFIG_PCIE3            /* PCIE controller 3 */
 476 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 477
 478 #ifdef CONFIG_PCI
 479 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 480 #ifdef CONFIG_PCIE1
 481 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 482 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 483 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 484 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 485 #endif
 486
 487 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 488 #ifdef CONFIG_PCIE2
 489 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 490 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 491 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 492 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 493 #endif
 494
 495 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 496 #ifdef CONFIG_PCIE3
 497 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 498 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 499 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 500 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 501 #endif
 502
 503 #if !defined(CONFIG_DM_PCI)
 504 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 505 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 506 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 507 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 508 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 509 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 510 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 511 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 512 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 513 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 514 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 515 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 516 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 517 #define CONFIG_PCI_INDIRECT_BRIDGE
 518 #endif
 519
 520 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 521 #endif  /* CONFIG_PCI */
 522
 523 /*
 524  * USB
 525  */
 526 #define CONFIG_HAS_FSL_DR_USB
 527
 528 #ifdef CONFIG_HAS_FSL_DR_USB
 529 #define CONFIG_USB_EHCI_FSL
 530 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 531 #endif
 532
 533 /*
 534  * SDHC
 535  */
 536 #ifdef CONFIG_MMC
 537 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 538 #endif
 539
 540 /* Qman/Bman */
 541 #ifndef CONFIG_NOBQFMAN
 542 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 543 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 544 #ifdef CONFIG_PHYS_64BIT
 545 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 546 #else
 547 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 548 #endif
 549 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 550 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 551 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 552 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 553 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 554 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 555                                         CONFIG_SYS_BMAN_CENA_SIZE)
 556 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 557 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 558 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 559 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 560 #ifdef CONFIG_PHYS_64BIT
 561 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 562 #else
 563 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 564 #endif
 565 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 566 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 567 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 568 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 569 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 570 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 571                                         CONFIG_SYS_QMAN_CENA_SIZE)
 572 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 573 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 574
 575 #define CONFIG_SYS_DPAA_FMAN
 576
 577 /* Default address of microcode for the Linux FMan driver */
 578 #if defined(CONFIG_SPIFLASH)
 579 /*
 580  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 581  * env, so we got 0x110000.
 582  */
 583 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 584 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 585 #elif defined(CONFIG_SDCARD)
 586 /*
 587  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 588  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 589  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 590  */
 591 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 592 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 593 #elif defined(CONFIG_MTD_RAW_NAND)
 594 #if defined(CONFIG_TARGET_T1024RDB)
 595 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 596 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 597 #elif defined(CONFIG_TARGET_T1023RDB)
 598 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 599 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 600 #endif
 601 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 602 /*
 603  * Slave has no ucode locally, it can fetch this from remote. When implementing
 604  * in two corenet boards, slave's ucode could be stored in master's memory
 605  * space, the address can be mapped from slave TLB->slave LAW->
 606  * slave SRIO or PCIE outbound window->master inbound window->
 607  * master LAW->the ucode address in master's memory space.
 608  */
 609 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 610 #else
 611 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 612 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 613 #endif
 614 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 615 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 616 #endif /* CONFIG_NOBQFMAN */
 617
 618 #ifdef CONFIG_SYS_DPAA_FMAN
 619 #if defined(CONFIG_TARGET_T1024RDB)
 620 #define RGMII_PHY1_ADDR         0x2
 621 #define RGMII_PHY2_ADDR         0x6
 622 #define SGMII_AQR_PHY_ADDR      0x2
 623 #define FM1_10GEC1_PHY_ADDR     0x1
 624 #elif defined(CONFIG_TARGET_T1023RDB)
 625 #define RGMII_PHY1_ADDR         0x1
 626 #define SGMII_RTK_PHY_ADDR      0x3
 627 #define SGMII_AQR_PHY_ADDR      0x2
 628 #endif
 629 #endif
 630
 631 #ifdef CONFIG_FMAN_ENET
 632 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 633 #endif
 634
 635 /*
 636  * Dynamic MTD Partition support with mtdparts
 637  */
 638
 639 /*
 640  * Environment
 641  */
 642 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 643 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 644
 645 /*
 646  * Miscellaneous configurable options
 647  */
 648 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 649
 650 /*
 651  * For booting Linux, the board info and command line data
 652  * have to be in the first 64 MB of memory, since this is
 653  * the maximum mapped by the Linux kernel during initialization.
 654  */
 655 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 656 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 657
 658 #ifdef CONFIG_CMD_KGDB
 659 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 660 #endif
 661
 662 /*
 663  * Environment Configuration
 664  */
 665 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 666 #define CONFIG_BOOTFILE         "uImage"
 667 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 668 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 669 #define __USB_PHY_TYPE          utmi
 670
 671 #ifdef CONFIG_ARCH_T1024
 672 #define CONFIG_BOARDNAME t1024rdb
 673 #define BANK_INTLV cs0_cs1
 674 #else
 675 #define CONFIG_BOARDNAME t1023rdb
 676 #define BANK_INTLV  null
 677 #endif
 678
 679 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 680         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 681         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 682         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 683         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 684         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 685         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 686         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 687         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 688         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 689         "netdev=eth0\0"                                         \
 690         "tftpflash=tftpboot $loadaddr $uboot && "               \
 691         "protect off $ubootaddr +$filesize && "                 \
 692         "erase $ubootaddr +$filesize && "                       \
 693         "cp.b $loadaddr $ubootaddr $filesize && "               \
 694         "protect on $ubootaddr +$filesize && "                  \
 695         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 696         "consoledev=ttyS0\0"                                    \
 697         "ramdiskaddr=2000000\0"                                 \
 698         "fdtaddr=1e00000\0"                                     \
 699         "bdev=sda3\0"
 700
 701 #define CONFIG_LINUX                                    \
 702         "setenv bootargs root=/dev/ram rw "             \
 703         "console=$consoledev,$baudrate $othbootargs;"   \
 704         "setenv ramdiskaddr 0x02000000;"                \
 705         "setenv fdtaddr 0x00c00000;"                    \
 706         "setenv loadaddr 0x1000000;"                    \
 707         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 708
 709 #define CONFIG_NFSBOOTCOMMAND                   \
 710         "setenv bootargs root=/dev/nfs rw "     \
 711         "nfsroot=$serverip:$rootpath "          \
 712         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 713         "console=$consoledev,$baudrate $othbootargs;"   \
 714         "tftp $loadaddr $bootfile;"             \
 715         "tftp $fdtaddr $fdtfile;"               \
 716         "bootm $loadaddr - $fdtaddr"
 717
 718 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 719
 720 #include <asm/fsl_secure_boot.h>
 721
 722 #endif  /* __T1024RDB_H */