include/configs/T102xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 QDS board configuration file
   8  */
   9
  10 #ifndef __T1024QDS_H
  11 #define __T1024QDS_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 #define CONFIG_DEEP_SLEEP
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  31 #define CONFIG_SPL_FLUSH_IMAGE
  32 #define CONFIG_SPL_PAD_TO               0x40000
  33 #define CONFIG_SPL_MAX_SIZE             0x28000
  34 #define RESET_VECTOR_OFFSET             0x27FFC
  35 #define BOOT_PAGE_OFFSET                0x27000
  36 #ifdef CONFIG_SPL_BUILD
  37 #define CONFIG_SPL_SKIP_RELOCATE
  38 #define CONFIG_SPL_COMMON_INIT_DDR
  39 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  40 #endif
  41
  42 #ifdef CONFIG_NAND
  43 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  44 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  45 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  47 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  49 #endif
  50
  51 #ifdef CONFIG_SPIFLASH
  52 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  53 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  58 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  59 #ifndef CONFIG_SPL_BUILD
  60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  61 #endif
  62 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  63 #endif
  64
  65 #ifdef CONFIG_SDCARD
  66 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  67 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  68 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  69 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  70 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  71 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  72 #ifndef CONFIG_SPL_BUILD
  73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  74 #endif
  75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  76 #endif
  77
  78 #endif /* CONFIG_RAMBOOT_PBL */
  79
  80 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  81 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  82 #endif
  83
  84 /* PCIe Boot - Master */
  85 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  86 /*
  87  * for slave u-boot IMAGE instored in master memory space,
  88  * PHYS must be aligned based on the SIZE
  89  */
  90 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  91 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  92 #ifdef CONFIG_PHYS_64BIT
  93 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  95 #else
  96 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  97 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  98 #endif
  99 /*
 100  * for slave UCODE and ENV instored in master memory space,
 101  * PHYS must be aligned based on the SIZE
 102  */
 103 #ifdef CONFIG_PHYS_64BIT
 104 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 105 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 106 #else
 107 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 108 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 109 #endif
 110 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 111 /* slave core release by master*/
 112 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 113 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 114
 115 /* PCIe Boot - Slave */
 116 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 117 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 118 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 119                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 120 /* Set 1M boot space for PCIe boot */
 121 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 122 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 123                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 124 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 125 #endif
 126
 127 #if defined(CONFIG_SPIFLASH)
 128 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 129 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 130 #define CONFIG_ENV_SECT_SIZE            0x10000
 131 #elif defined(CONFIG_SDCARD)
 132 #define CONFIG_SYS_MMC_ENV_DEV          0
 133 #define CONFIG_ENV_SIZE                 0x2000
 134 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 135 #elif defined(CONFIG_NAND)
 136 #define CONFIG_ENV_SIZE                 0x2000
 137 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 138 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 139 #define CONFIG_ENV_ADDR         0xffe20000
 140 #define CONFIG_ENV_SIZE         0x2000
 141 #elif defined(CONFIG_ENV_IS_NOWHERE)
 142 #define CONFIG_ENV_SIZE         0x2000
 143 #else
 144 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 145 #define CONFIG_ENV_SIZE         0x2000
 146 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 147 #endif
 148
 149 #ifndef __ASSEMBLY__
 150 unsigned long get_board_sys_clk(void);
 151 unsigned long get_board_ddr_clk(void);
 152 #endif
 153
 154 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 155 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 156
 157 /*
 158  * These can be toggled for performance analysis, otherwise use default.
 159  */
 160 #define CONFIG_SYS_CACHE_STASHING
 161 #define CONFIG_BACKSIDE_L2_CACHE
 162 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 163 #define CONFIG_BTB                      /* toggle branch predition */
 164 #define CONFIG_DDR_ECC
 165 #ifdef CONFIG_DDR_ECC
 166 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 167 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 168 #endif
 169
 170 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 171 #define CONFIG_SYS_MEMTEST_END          0x00400000
 172
 173 /*
 174  *  Config the L3 Cache as L3 SRAM
 175  */
 176 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 177 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 178 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 179 #ifdef CONFIG_RAMBOOT_PBL
 180 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 181 #endif
 182 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 183 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 184 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 185
 186 #ifdef CONFIG_PHYS_64BIT
 187 #define CONFIG_SYS_DCSRBAR              0xf0000000
 188 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 189 #endif
 190
 191 /* EEPROM */
 192 #define CONFIG_ID_EEPROM
 193 #define CONFIG_SYS_I2C_EEPROM_NXID
 194 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 195 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 196 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 197 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 198 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 199
 200 /*
 201  * DDR Setup
 202  */
 203 #define CONFIG_VERY_BIG_RAM
 204 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 205 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 206 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 207 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 208 #define CONFIG_DDR_SPD
 209
 210 #define CONFIG_SYS_SPD_BUS_NUM  0
 211 #define SPD_EEPROM_ADDRESS      0x51
 212
 213 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 214
 215 /*
 216  * IFC Definitions
 217  */
 218 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 219 #ifdef CONFIG_PHYS_64BIT
 220 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 221 #else
 222 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 223 #endif
 224
 225 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 226 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 227                                 + 0x8000000) | \
 228                                 CSPR_PORT_SIZE_16 | \
 229                                 CSPR_MSEL_NOR | \
 230                                 CSPR_V)
 231 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 232 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 233                                 CSPR_PORT_SIZE_16 | \
 234                                 CSPR_MSEL_NOR | \
 235                                 CSPR_V)
 236 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 237 /* NOR Flash Timing Params */
 238 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 239 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 240                                 FTIM0_NOR_TEADC(0x5) | \
 241                                 FTIM0_NOR_TEAHC(0x5))
 242 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 243                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 244                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 245 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 246                                 FTIM2_NOR_TCH(0x4) | \
 247                                 FTIM2_NOR_TWPH(0x0E) | \
 248                                 FTIM2_NOR_TWP(0x1c))
 249 #define CONFIG_SYS_NOR_FTIM3    0x0
 250
 251 #define CONFIG_SYS_FLASH_QUIET_TEST
 252 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 253
 254 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 255 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 256 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 257 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 258
 259 #define CONFIG_SYS_FLASH_EMPTY_INFO
 260 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 261                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 262 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 263 #define QIXIS_BASE              0xffdf0000
 264 #ifdef CONFIG_PHYS_64BIT
 265 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 266 #else
 267 #define QIXIS_BASE_PHYS         QIXIS_BASE
 268 #endif
 269 #define QIXIS_LBMAP_SWITCH              0x06
 270 #define QIXIS_LBMAP_MASK                0x0f
 271 #define QIXIS_LBMAP_SHIFT               0
 272 #define QIXIS_LBMAP_DFLTBANK            0x00
 273 #define QIXIS_LBMAP_ALTBANK             0x04
 274 #define QIXIS_RST_CTL_RESET             0x31
 275 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 276 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 277 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 278 #define QIXIS_RST_FORCE_MEM             0x01
 279
 280 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 281 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 282                                 | CSPR_PORT_SIZE_8 \
 283                                 | CSPR_MSEL_GPCM \
 284                                 | CSPR_V)
 285 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 286 #define CONFIG_SYS_CSOR3        0x0
 287 /* QIXIS Timing parameters for IFC CS3 */
 288 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 289                                         FTIM0_GPCM_TEADC(0x0e) | \
 290                                         FTIM0_GPCM_TEAHC(0x0e))
 291 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 292                                         FTIM1_GPCM_TRAD(0x3f))
 293 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 294                                         FTIM2_GPCM_TCH(0x8) | \
 295                                         FTIM2_GPCM_TWP(0x1f))
 296 #define CONFIG_SYS_CS3_FTIM3            0x0
 297
 298 #define CONFIG_NAND_FSL_IFC
 299 #define CONFIG_SYS_NAND_BASE            0xff800000
 300 #ifdef CONFIG_PHYS_64BIT
 301 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 302 #else
 303 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 304 #endif
 305 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 306 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 307                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 308                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 309                                 | CSPR_V)
 310 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 311
 312 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 313                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 314                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 315                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 316                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 317                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 318                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 319
 320 #define CONFIG_SYS_NAND_ONFI_DETECTION
 321
 322 /* ONFI NAND Flash mode0 Timing Params */
 323 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 324                                         FTIM0_NAND_TWP(0x18)   | \
 325                                         FTIM0_NAND_TWCHT(0x07) | \
 326                                         FTIM0_NAND_TWH(0x0a))
 327 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 328                                         FTIM1_NAND_TWBE(0x39)  | \
 329                                         FTIM1_NAND_TRR(0x0e)   | \
 330                                         FTIM1_NAND_TRP(0x18))
 331 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 332                                         FTIM2_NAND_TREH(0x0a) | \
 333                                         FTIM2_NAND_TWHRE(0x1e))
 334 #define CONFIG_SYS_NAND_FTIM3           0x0
 335
 336 #define CONFIG_SYS_NAND_DDR_LAW         11
 337 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 338 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 339
 340 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 341
 342 #if defined(CONFIG_NAND)
 343 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 344 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 345 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 346 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 347 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 348 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 349 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 350 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 351 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 352 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 353 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 354 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 355 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 356 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 357 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 358 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 359 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 360 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 361 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 362 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 363 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 364 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 365 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 366 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 367 #else
 368 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 369 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 370 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 371 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 372 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 373 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 374 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 375 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 376 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 377 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 378 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 379 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 380 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 381 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 382 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 383 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 384 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 385 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 386 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 387 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 388 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 389 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 390 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 391 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 392 #endif
 393
 394 #ifdef CONFIG_SPL_BUILD
 395 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 396 #else
 397 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 398 #endif
 399
 400 #if defined(CONFIG_RAMBOOT_PBL)
 401 #define CONFIG_SYS_RAMBOOT
 402 #endif
 403
 404 #define CONFIG_HWCONFIG
 405
 406 /* define to use L1 as initial stack */
 407 #define CONFIG_L1_INIT_RAM
 408 #define CONFIG_SYS_INIT_RAM_LOCK
 409 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 410 #ifdef CONFIG_PHYS_64BIT
 411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 413 /* The assembler doesn't like typecast */
 414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 415         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 416           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 417 #else
 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 421 #endif
 422 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 423
 424 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 425                                         GENERATED_GBL_DATA_SIZE)
 426 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 427
 428 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 429 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 430
 431 /* Serial Port */
 432 #define CONFIG_SYS_NS16550_SERIAL
 433 #define CONFIG_SYS_NS16550_REG_SIZE     1
 434 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 435
 436 #define CONFIG_SYS_BAUDRATE_TABLE       \
 437         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 438
 439 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 440 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 441 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 442 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 443
 444 /* Video */
 445 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 446 #define CONFIG_FSL_DIU_FB
 447 #ifdef CONFIG_FSL_DIU_FB
 448 #define CONFIG_FSL_DIU_CH7301
 449 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 450 #define CONFIG_VIDEO_LOGO
 451 #define CONFIG_VIDEO_BMP_LOGO
 452 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 453 /*
 454  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 455  * disable empty flash sector detection, which is I/O-intensive.
 456  */
 457 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 458 #endif
 459 #endif
 460
 461 /* I2C */
 462 #define CONFIG_SYS_I2C
 463 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 464 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 465 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 466 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 467 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 468 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 469 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 470
 471 #define I2C_MUX_PCA_ADDR                0x77
 472 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 473 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 474 #define I2C_RETIMER_ADDR                0x18
 475
 476 /* I2C bus multiplexer */
 477 #define I2C_MUX_CH_DEFAULT      0x8
 478 #define I2C_MUX_CH_DIU          0xC
 479 #define I2C_MUX_CH5             0xD
 480 #define I2C_MUX_CH7             0xF
 481
 482 /* LDI/DVI Encoder for display */
 483 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 484 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 485
 486 /*
 487  * RTC configuration
 488  */
 489 #define RTC
 490 #define CONFIG_RTC_DS3231       1
 491 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 492
 493 /*
 494  * eSPI - Enhanced SPI
 495  */
 496
 497 /*
 498  * General PCIe
 499  * Memory space is mapped 1-1, but I/O space must start from 0.
 500  */
 501 #define CONFIG_PCIE1            /* PCIE controller 1 */
 502 #define CONFIG_PCIE2            /* PCIE controller 2 */
 503 #define CONFIG_PCIE3            /* PCIE controller 3 */
 504 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 505 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 506 #define CONFIG_PCI_INDIRECT_BRIDGE
 507
 508 #ifdef CONFIG_PCI
 509 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 510 #ifdef CONFIG_PCIE1
 511 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 512 #ifdef CONFIG_PHYS_64BIT
 513 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 514 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 515 #else
 516 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 517 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 518 #endif
 519 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 520 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 521 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 522 #ifdef CONFIG_PHYS_64BIT
 523 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 524 #else
 525 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 526 #endif
 527 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 528 #endif
 529
 530 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 531 #ifdef CONFIG_PCIE2
 532 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 533 #ifdef CONFIG_PHYS_64BIT
 534 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 535 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 536 #else
 537 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 538 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 539 #endif
 540 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 541 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 542 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 543 #ifdef CONFIG_PHYS_64BIT
 544 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 545 #else
 546 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 547 #endif
 548 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 549 #endif
 550
 551 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 552 #ifdef CONFIG_PCIE3
 553 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 554 #ifdef CONFIG_PHYS_64BIT
 555 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 556 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 557 #else
 558 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 559 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 560 #endif
 561 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 562 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 563 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 564 #ifdef CONFIG_PHYS_64BIT
 565 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 566 #else
 567 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 568 #endif
 569 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 570 #endif
 571
 572 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 573 #endif  /* CONFIG_PCI */
 574
 575 /*
 576  *SATA
 577  */
 578 #define CONFIG_FSL_SATA_V2
 579 #ifdef CONFIG_FSL_SATA_V2
 580 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 581 #define CONFIG_SATA1
 582 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 583 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 584 #define CONFIG_LBA48
 585 #endif
 586
 587 /*
 588  * USB
 589  */
 590 #define CONFIG_HAS_FSL_DR_USB
 591
 592 #ifdef CONFIG_HAS_FSL_DR_USB
 593 #define CONFIG_USB_EHCI_FSL
 594 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 595 #endif
 596
 597 /*
 598  * SDHC
 599  */
 600 #ifdef CONFIG_MMC
 601 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 602 #endif
 603
 604 /* Qman/Bman */
 605 #ifndef CONFIG_NOBQFMAN
 606 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 607 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 608 #ifdef CONFIG_PHYS_64BIT
 609 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 610 #else
 611 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 612 #endif
 613 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 614 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 615 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 616 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 617 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 618 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 619                                         CONFIG_SYS_BMAN_CENA_SIZE)
 620 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 621 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 622 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 623 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 624 #ifdef CONFIG_PHYS_64BIT
 625 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 626 #else
 627 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 628 #endif
 629 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 630 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 631 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 632 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 633 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 634 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 635                                         CONFIG_SYS_QMAN_CENA_SIZE)
 636 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 637 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 638
 639 #define CONFIG_SYS_DPAA_FMAN
 640
 641 /* Default address of microcode for the Linux FMan driver */
 642 #if defined(CONFIG_SPIFLASH)
 643 /*
 644  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 645  * env, so we got 0x110000.
 646  */
 647 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 648 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 649 #elif defined(CONFIG_SDCARD)
 650 /*
 651  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 652  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 653  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 654  */
 655 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 656 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 657 #elif defined(CONFIG_NAND)
 658 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 659 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 660 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 661 /*
 662  * Slave has no ucode locally, it can fetch this from remote. When implementing
 663  * in two corenet boards, slave's ucode could be stored in master's memory
 664  * space, the address can be mapped from slave TLB->slave LAW->
 665  * slave SRIO or PCIE outbound window->master inbound window->
 666  * master LAW->the ucode address in master's memory space.
 667  */
 668 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 669 #else
 670 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 671 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 672 #endif
 673 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 674 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 675 #endif /* CONFIG_NOBQFMAN */
 676
 677 #ifdef CONFIG_SYS_DPAA_FMAN
 678 #define CONFIG_PHYLIB_10G
 679 #define CONFIG_PHY_VITESSE
 680 #define CONFIG_PHY_REALTEK
 681 #define CONFIG_PHY_TERANETICS
 682 #define RGMII_PHY1_ADDR         0x1
 683 #define RGMII_PHY2_ADDR         0x2
 684 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 685 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 686 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 687 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 688 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 689 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 690 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 691 #endif
 692
 693 #ifdef CONFIG_FMAN_ENET
 694 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 695 #endif
 696
 697 /*
 698  * Dynamic MTD Partition support with mtdparts
 699  */
 700
 701 /*
 702  * Environment
 703  */
 704 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 705 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 706
 707 /*
 708  * Miscellaneous configurable options
 709  */
 710 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 711
 712 /*
 713  * For booting Linux, the board info and command line data
 714  * have to be in the first 64 MB of memory, since this is
 715  * the maximum mapped by the Linux kernel during initialization.
 716  */
 717 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 718 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 719
 720 #ifdef CONFIG_CMD_KGDB
 721 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 722 #endif
 723
 724 /*
 725  * Environment Configuration
 726  */
 727 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 728 #define CONFIG_BOOTFILE         "uImage"
 729 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 730 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 731 #define __USB_PHY_TYPE          utmi
 732
 733 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 734         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 735         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 736         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 737         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 738         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 739         "netdev=eth0\0"                                         \
 740         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 741         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 742         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 743         "tftpflash=tftpboot $loadaddr $uboot && "               \
 744         "protect off $ubootaddr +$filesize && "                 \
 745         "erase $ubootaddr +$filesize && "                       \
 746         "cp.b $loadaddr $ubootaddr $filesize && "               \
 747         "protect on $ubootaddr +$filesize && "                  \
 748         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 749         "consoledev=ttyS0\0"                                    \
 750         "ramdiskaddr=2000000\0"                                 \
 751         "fdtaddr=d00000\0"                                      \
 752         "bdev=sda3\0"
 753
 754 #define CONFIG_LINUX                                    \
 755         "setenv bootargs root=/dev/ram rw "             \
 756         "console=$consoledev,$baudrate $othbootargs;"   \
 757         "setenv ramdiskaddr 0x02000000;"                \
 758         "setenv fdtaddr 0x00c00000;"                    \
 759         "setenv loadaddr 0x1000000;"                    \
 760         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 761
 762 #define CONFIG_NFSBOOTCOMMAND                   \
 763         "setenv bootargs root=/dev/nfs rw "     \
 764         "nfsroot=$serverip:$rootpath "          \
 765         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 766         "console=$consoledev,$baudrate $othbootargs;"   \
 767         "tftp $loadaddr $bootfile;"             \
 768         "tftp $fdtaddr $fdtfile;"               \
 769         "bootm $loadaddr - $fdtaddr"
 770
 771 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 772
 773 #include <asm/fsl_secure_boot.h>
 774
 775 #endif  /* __T1024QDS_H */