include/configs/T102xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 QDS board configuration file
   9  */
  10
  11 #ifndef __T1024QDS_H
  12 #define __T1024QDS_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_ENABLE_36BIT_PHYS
  17
  18 #ifdef CONFIG_PHYS_64BIT
  19 #define CONFIG_ADDR_MAP         1
  20 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  21 #endif
  22
  23 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  24 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  25
  26 #define CONFIG_ENV_OVERWRITE
  27
  28 #define CONFIG_DEEP_SLEEP
  29
  30 #ifdef CONFIG_RAMBOOT_PBL
  31 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  32 #define CONFIG_SPL_FLUSH_IMAGE
  33 #define CONFIG_SPL_PAD_TO               0x40000
  34 #define CONFIG_SPL_MAX_SIZE             0x28000
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SPL_SKIP_RELOCATE
  39 #define CONFIG_SPL_COMMON_INIT_DDR
  40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  41 #endif
  42
  43 #ifdef CONFIG_MTD_RAW_NAND
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  47 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  49 #endif
  50
  51 #ifdef CONFIG_SPIFLASH
  52 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  53 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  58 #ifndef CONFIG_SPL_BUILD
  59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  60 #endif
  61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  62 #endif
  63
  64 #ifdef CONFIG_SDCARD
  65 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  66 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  67 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  68 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  69 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  70 #ifndef CONFIG_SPL_BUILD
  71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  72 #endif
  73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  74 #endif
  75
  76 #endif /* CONFIG_RAMBOOT_PBL */
  77
  78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  79 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  80 #endif
  81
  82 /* PCIe Boot - Master */
  83 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  84 /*
  85  * for slave u-boot IMAGE instored in master memory space,
  86  * PHYS must be aligned based on the SIZE
  87  */
  88 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  89 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  90 #ifdef CONFIG_PHYS_64BIT
  91 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  92 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  93 #else
  94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  95 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  96 #endif
  97 /*
  98  * for slave UCODE and ENV instored in master memory space,
  99  * PHYS must be aligned based on the SIZE
 100  */
 101 #ifdef CONFIG_PHYS_64BIT
 102 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 103 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 104 #else
 105 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 106 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 107 #endif
 108 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 109 /* slave core release by master*/
 110 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 111 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 112
 113 /* PCIe Boot - Slave */
 114 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 115 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 116 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 117                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 118 /* Set 1M boot space for PCIe boot */
 119 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 120 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 121                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 123 #endif
 124
 125 #if defined(CONFIG_SPIFLASH)
 126 #elif defined(CONFIG_SDCARD)
 127 #define CONFIG_SYS_MMC_ENV_DEV          0
 128 #endif
 129
 130 #ifndef __ASSEMBLY__
 131 unsigned long get_board_sys_clk(void);
 132 unsigned long get_board_ddr_clk(void);
 133 #endif
 134
 135 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 136 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 137
 138 /*
 139  * These can be toggled for performance analysis, otherwise use default.
 140  */
 141 #define CONFIG_SYS_CACHE_STASHING
 142 #define CONFIG_BACKSIDE_L2_CACHE
 143 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 144 #define CONFIG_BTB                      /* toggle branch predition */
 145 #define CONFIG_DDR_ECC
 146 #ifdef CONFIG_DDR_ECC
 147 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 148 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 149 #endif
 150
 151 /*
 152  *  Config the L3 Cache as L3 SRAM
 153  */
 154 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 155 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 156 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 157 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 158 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 159 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 160 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 161
 162 #ifdef CONFIG_PHYS_64BIT
 163 #define CONFIG_SYS_DCSRBAR              0xf0000000
 164 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 165 #endif
 166
 167 /* EEPROM */
 168 #define CONFIG_ID_EEPROM
 169 #define CONFIG_SYS_I2C_EEPROM_NXID
 170 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 171 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 172 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 173 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 174 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 175
 176 /*
 177  * DDR Setup
 178  */
 179 #define CONFIG_VERY_BIG_RAM
 180 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 181 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 182 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 183 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 184 #define CONFIG_DDR_SPD
 185
 186 #define CONFIG_SYS_SPD_BUS_NUM  0
 187 #define SPD_EEPROM_ADDRESS      0x51
 188
 189 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 190
 191 /*
 192  * IFC Definitions
 193  */
 194 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 195 #ifdef CONFIG_PHYS_64BIT
 196 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 197 #else
 198 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 199 #endif
 200
 201 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 202 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 203                                 + 0x8000000) | \
 204                                 CSPR_PORT_SIZE_16 | \
 205                                 CSPR_MSEL_NOR | \
 206                                 CSPR_V)
 207 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 208 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 209                                 CSPR_PORT_SIZE_16 | \
 210                                 CSPR_MSEL_NOR | \
 211                                 CSPR_V)
 212 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 213 /* NOR Flash Timing Params */
 214 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 215 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 216                                 FTIM0_NOR_TEADC(0x5) | \
 217                                 FTIM0_NOR_TEAHC(0x5))
 218 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 219                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 220                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 221 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 222                                 FTIM2_NOR_TCH(0x4) | \
 223                                 FTIM2_NOR_TWPH(0x0E) | \
 224                                 FTIM2_NOR_TWP(0x1c))
 225 #define CONFIG_SYS_NOR_FTIM3    0x0
 226
 227 #define CONFIG_SYS_FLASH_QUIET_TEST
 228 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 229
 230 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 231 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 232 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 233 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 234
 235 #define CONFIG_SYS_FLASH_EMPTY_INFO
 236 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 237                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 238 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 239 #define QIXIS_BASE              0xffdf0000
 240 #ifdef CONFIG_PHYS_64BIT
 241 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 242 #else
 243 #define QIXIS_BASE_PHYS         QIXIS_BASE
 244 #endif
 245 #define QIXIS_LBMAP_SWITCH              0x06
 246 #define QIXIS_LBMAP_MASK                0x0f
 247 #define QIXIS_LBMAP_SHIFT               0
 248 #define QIXIS_LBMAP_DFLTBANK            0x00
 249 #define QIXIS_LBMAP_ALTBANK             0x04
 250 #define QIXIS_RST_CTL_RESET             0x31
 251 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 252 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 253 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 254 #define QIXIS_RST_FORCE_MEM             0x01
 255
 256 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 257 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 258                                 | CSPR_PORT_SIZE_8 \
 259                                 | CSPR_MSEL_GPCM \
 260                                 | CSPR_V)
 261 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 262 #define CONFIG_SYS_CSOR3        0x0
 263 /* QIXIS Timing parameters for IFC CS3 */
 264 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 265                                         FTIM0_GPCM_TEADC(0x0e) | \
 266                                         FTIM0_GPCM_TEAHC(0x0e))
 267 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 268                                         FTIM1_GPCM_TRAD(0x3f))
 269 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 270                                         FTIM2_GPCM_TCH(0x8) | \
 271                                         FTIM2_GPCM_TWP(0x1f))
 272 #define CONFIG_SYS_CS3_FTIM3            0x0
 273
 274 #define CONFIG_NAND_FSL_IFC
 275 #define CONFIG_SYS_NAND_BASE            0xff800000
 276 #ifdef CONFIG_PHYS_64BIT
 277 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 278 #else
 279 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 280 #endif
 281 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 282 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 283                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 284                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 285                                 | CSPR_V)
 286 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 287
 288 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 289                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 290                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 291                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 292                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 293                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 294                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 295
 296 #define CONFIG_SYS_NAND_ONFI_DETECTION
 297
 298 /* ONFI NAND Flash mode0 Timing Params */
 299 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 300                                         FTIM0_NAND_TWP(0x18)   | \
 301                                         FTIM0_NAND_TWCHT(0x07) | \
 302                                         FTIM0_NAND_TWH(0x0a))
 303 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 304                                         FTIM1_NAND_TWBE(0x39)  | \
 305                                         FTIM1_NAND_TRR(0x0e)   | \
 306                                         FTIM1_NAND_TRP(0x18))
 307 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 308                                         FTIM2_NAND_TREH(0x0a) | \
 309                                         FTIM2_NAND_TWHRE(0x1e))
 310 #define CONFIG_SYS_NAND_FTIM3           0x0
 311
 312 #define CONFIG_SYS_NAND_DDR_LAW         11
 313 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 314 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 315
 316 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 317
 318 #if defined(CONFIG_MTD_RAW_NAND)
 319 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 320 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 321 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 322 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 323 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 324 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 325 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 326 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 327 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 328 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 329 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 330 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 331 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 332 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 333 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 334 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 335 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 336 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 337 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 338 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 339 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 340 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 341 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 342 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 343 #else
 344 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 345 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 346 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 347 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 348 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 349 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 350 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 351 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 352 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 353 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 354 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 355 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 356 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 357 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 358 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 359 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 360 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 361 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 362 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 363 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 364 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 365 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 366 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 367 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 368 #endif
 369
 370 #ifdef CONFIG_SPL_BUILD
 371 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 372 #else
 373 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 374 #endif
 375
 376 #if defined(CONFIG_RAMBOOT_PBL)
 377 #define CONFIG_SYS_RAMBOOT
 378 #endif
 379
 380 #define CONFIG_HWCONFIG
 381
 382 /* define to use L1 as initial stack */
 383 #define CONFIG_L1_INIT_RAM
 384 #define CONFIG_SYS_INIT_RAM_LOCK
 385 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 386 #ifdef CONFIG_PHYS_64BIT
 387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 389 /* The assembler doesn't like typecast */
 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 391         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 392           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 393 #else
 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 396 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 397 #endif
 398 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 399
 400 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 401                                         GENERATED_GBL_DATA_SIZE)
 402 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 403
 404 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 405 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 406
 407 /* Serial Port */
 408 #define CONFIG_SYS_NS16550_SERIAL
 409 #define CONFIG_SYS_NS16550_REG_SIZE     1
 410 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 411
 412 #define CONFIG_SYS_BAUDRATE_TABLE       \
 413         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 414
 415 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 416 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 417 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 418 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 419
 420 /* Video */
 421 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 422 #define CONFIG_FSL_DIU_FB
 423 #ifdef CONFIG_FSL_DIU_FB
 424 #define CONFIG_FSL_DIU_CH7301
 425 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 426 #define CONFIG_VIDEO_LOGO
 427 #define CONFIG_VIDEO_BMP_LOGO
 428 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 429 /*
 430  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 431  * disable empty flash sector detection, which is I/O-intensive.
 432  */
 433 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 434 #endif
 435 #endif
 436
 437 /* I2C */
 438 #ifndef CONFIG_DM_I2C
 439 #define CONFIG_SYS_I2C
 440 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 441 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 442 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 443 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 444 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 445 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 446 #else
 447 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 448 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 449 #endif
 450
 451 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 452
 453 #define I2C_MUX_PCA_ADDR                0x77
 454 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 455 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 456 #define I2C_RETIMER_ADDR                0x18
 457
 458 /* I2C bus multiplexer */
 459 #define I2C_MUX_CH_DEFAULT      0x8
 460 #define I2C_MUX_CH_DIU          0xC
 461 #define I2C_MUX_CH5             0xD
 462 #define I2C_MUX_CH7             0xF
 463
 464 /* LDI/DVI Encoder for display */
 465 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 466 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 467 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
 468
 469 /*
 470  * RTC configuration
 471  */
 472 #define RTC
 473 #define CONFIG_RTC_DS3231       1
 474 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 475
 476 /*
 477  * eSPI - Enhanced SPI
 478  */
 479
 480 /*
 481  * General PCIe
 482  * Memory space is mapped 1-1, but I/O space must start from 0.
 483  */
 484 #define CONFIG_PCIE1            /* PCIE controller 1 */
 485 #define CONFIG_PCIE2            /* PCIE controller 2 */
 486 #define CONFIG_PCIE3            /* PCIE controller 3 */
 487 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 488 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 489 #define CONFIG_PCI_INDIRECT_BRIDGE
 490
 491 #ifdef CONFIG_PCI
 492 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 493 #ifdef CONFIG_PCIE1
 494 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 495 #ifdef CONFIG_PHYS_64BIT
 496 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 497 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 498 #else
 499 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 500 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 501 #endif
 502 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 503 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 504 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 505 #ifdef CONFIG_PHYS_64BIT
 506 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 507 #else
 508 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 509 #endif
 510 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 511 #endif
 512
 513 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 514 #ifdef CONFIG_PCIE2
 515 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 516 #ifdef CONFIG_PHYS_64BIT
 517 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 518 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 519 #else
 520 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 521 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 522 #endif
 523 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 524 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 525 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 526 #ifdef CONFIG_PHYS_64BIT
 527 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 528 #else
 529 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 530 #endif
 531 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 532 #endif
 533
 534 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 535 #ifdef CONFIG_PCIE3
 536 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 537 #ifdef CONFIG_PHYS_64BIT
 538 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 539 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 540 #else
 541 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 542 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 543 #endif
 544 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 545 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 546 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 547 #ifdef CONFIG_PHYS_64BIT
 548 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 549 #else
 550 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 551 #endif
 552 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 553 #endif
 554
 555 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 556 #endif  /* CONFIG_PCI */
 557
 558 /*
 559  *SATA
 560  */
 561 #define CONFIG_FSL_SATA_V2
 562 #ifdef CONFIG_FSL_SATA_V2
 563 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 564 #define CONFIG_SATA1
 565 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 566 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 567 #define CONFIG_LBA48
 568 #endif
 569
 570 /*
 571  * USB
 572  */
 573 #define CONFIG_HAS_FSL_DR_USB
 574
 575 #ifdef CONFIG_HAS_FSL_DR_USB
 576 #define CONFIG_USB_EHCI_FSL
 577 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 578 #endif
 579
 580 /*
 581  * SDHC
 582  */
 583 #ifdef CONFIG_MMC
 584 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 585 #endif
 586
 587 /* Qman/Bman */
 588 #ifndef CONFIG_NOBQFMAN
 589 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 590 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 591 #ifdef CONFIG_PHYS_64BIT
 592 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 593 #else
 594 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 595 #endif
 596 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 597 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 598 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 599 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 600 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 601 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 602                                         CONFIG_SYS_BMAN_CENA_SIZE)
 603 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 604 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 605 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 606 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 607 #ifdef CONFIG_PHYS_64BIT
 608 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 609 #else
 610 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 611 #endif
 612 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 613 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 614 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 615 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 616 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 617 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 618                                         CONFIG_SYS_QMAN_CENA_SIZE)
 619 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 620 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 621
 622 #define CONFIG_SYS_DPAA_FMAN
 623
 624 /* Default address of microcode for the Linux FMan driver */
 625 #if defined(CONFIG_SPIFLASH)
 626 /*
 627  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 628  * env, so we got 0x110000.
 629  */
 630 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 631 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 632 #elif defined(CONFIG_SDCARD)
 633 /*
 634  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 635  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 636  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 637  */
 638 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 639 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 640 #elif defined(CONFIG_MTD_RAW_NAND)
 641 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 642 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 643 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 644 /*
 645  * Slave has no ucode locally, it can fetch this from remote. When implementing
 646  * in two corenet boards, slave's ucode could be stored in master's memory
 647  * space, the address can be mapped from slave TLB->slave LAW->
 648  * slave SRIO or PCIE outbound window->master inbound window->
 649  * master LAW->the ucode address in master's memory space.
 650  */
 651 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 652 #else
 653 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 654 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 655 #endif
 656 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 657 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 658 #endif /* CONFIG_NOBQFMAN */
 659
 660 #ifdef CONFIG_SYS_DPAA_FMAN
 661 #define RGMII_PHY1_ADDR         0x1
 662 #define RGMII_PHY2_ADDR         0x2
 663 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 664 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 665 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 666 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 667 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 668 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 669 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 670 #endif
 671
 672 #ifdef CONFIG_FMAN_ENET
 673 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 674 #endif
 675
 676 /*
 677  * Dynamic MTD Partition support with mtdparts
 678  */
 679
 680 /*
 681  * Environment
 682  */
 683 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 684 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 685
 686 /*
 687  * Miscellaneous configurable options
 688  */
 689 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 690
 691 /*
 692  * For booting Linux, the board info and command line data
 693  * have to be in the first 64 MB of memory, since this is
 694  * the maximum mapped by the Linux kernel during initialization.
 695  */
 696 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 697 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 698
 699 #ifdef CONFIG_CMD_KGDB
 700 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 701 #endif
 702
 703 /*
 704  * Environment Configuration
 705  */
 706 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 707 #define CONFIG_BOOTFILE         "uImage"
 708 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 709 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 710 #define __USB_PHY_TYPE          utmi
 711
 712 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 713         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 714         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 715         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 716         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 717         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 718         "netdev=eth0\0"                                         \
 719         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 720         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 721         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 722         "tftpflash=tftpboot $loadaddr $uboot && "               \
 723         "protect off $ubootaddr +$filesize && "                 \
 724         "erase $ubootaddr +$filesize && "                       \
 725         "cp.b $loadaddr $ubootaddr $filesize && "               \
 726         "protect on $ubootaddr +$filesize && "                  \
 727         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 728         "consoledev=ttyS0\0"                                    \
 729         "ramdiskaddr=2000000\0"                                 \
 730         "fdtaddr=d00000\0"                                      \
 731         "bdev=sda3\0"
 732
 733 #define CONFIG_LINUX                                    \
 734         "setenv bootargs root=/dev/ram rw "             \
 735         "console=$consoledev,$baudrate $othbootargs;"   \
 736         "setenv ramdiskaddr 0x02000000;"                \
 737         "setenv fdtaddr 0x00c00000;"                    \
 738         "setenv loadaddr 0x1000000;"                    \
 739         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 740
 741 #define CONFIG_NFSBOOTCOMMAND                   \
 742         "setenv bootargs root=/dev/nfs rw "     \
 743         "nfsroot=$serverip:$rootpath "          \
 744         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 745         "console=$consoledev,$baudrate $othbootargs;"   \
 746         "tftp $loadaddr $bootfile;"             \
 747         "tftp $fdtaddr $fdtfile;"               \
 748         "bootm $loadaddr - $fdtaddr"
 749
 750 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 751
 752 #include <asm/fsl_secure_boot.h>
 753
 754 #endif  /* __T1024QDS_H */